Plurality Of Memory Devices (e.g., Array, Etc.) Patents (Class 714/6.2)
  • Patent number: 8543862
    Abstract: A computer is programmed to execute a diagnostic procedure either on a pre-set schedule or asynchronously in response to an event, such as an error message, or a user command. When executed, the diagnostic procedure automatically checks for integrity of one or more portions of data in the computer, to identify any failure(s). In some embodiments, the failure(s) may be displayed to a human, after revalidation to exclude any failure that no longer exists.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: September 24, 2013
    Assignee: Oracle International Corporation
    Inventors: Mark Dilman, Michael James Stewart, Wei-Ming Hu, Balasubrahmanyam Kuchibhotla, Margaret Susairaj, Hubert Ken Sun
  • Patent number: 8539300
    Abstract: An information recording and reproducing apparatus writes user data received from an external device into a recording medium and reads the user data from the recording medium so as to transmit the user data to the external terminal.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: September 17, 2013
    Assignee: Panasonic Corporation
    Inventor: Takeshi Otsuka
  • Publication number: 20130238928
    Abstract: A video server has a table generator, a rebuild processor, and a rebuild controller. The table generator generates a management table of content data ID that specifies the content data and the write location of the content data in the storage unit where the content data are recorded. When a problem takes place in at least one of the storage devices, the rebuild processor executes a rebuild process to recover the content data of the troubled storage device. When a rebuild start request is generated by the rebuild processor, the rebuild controller controls the start and stop of the rebuild process by referring to the management table.
    Type: Application
    Filed: January 29, 2013
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki WATANABE, Toshiki Mori, Naoko Satoh
  • Publication number: 20130238929
    Abstract: Examples are disclosed for facilitating recovery from failures associated with a storage array having a plurality of storage devices.
    Type: Application
    Filed: November 2, 2011
    Publication date: September 12, 2013
    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventors: Junwei Cao, Xiao Lin
  • Patent number: 8533409
    Abstract: This specification discloses a method of managing data snapshot images in a storage system. The method includes the steps of: establishing a section allocation system that includes at least a media extent; establishing a section allocation table and a block association set in the media extent, wherein the section allocation table has a field containing information pointing to the block association set and the block association set corresponds to a Source Volume as the basis for performing a snapshot backup thereof; establishing a block association table in the block association set, wherein the block association table is used to store cross-reference information in order to correspond to backup data with the original storage addresses; and copying the data before updating the data into the section association set, when the data in the Source-Volume need to be updated.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: September 10, 2013
    Assignee: Infortrend Technology, Inc.
    Inventors: Michael Gordon Schnapp, Ching-Te Pang, Chien-Hsin Chiang
  • Patent number: 8533527
    Abstract: A RAID-group converting apparatus converts two RAID groups into one RAID group. The RAID-group converting apparatus includes: a data-reading unit that reads at least non-parity data from data including the non-parity data and parity data, for each stripe from a plurality of recording media belonging to the two RAID groups; a parity-generating unit that generates two parities using the data belonging to a same stripe read by the data-reading unit; and a parity-writing unit that writes the two parities generated by the parity-generating unit into a parity storage area belonging to the same stripe.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: September 10, 2013
    Assignee: Fujitsu Limited
    Inventors: Hidejirou Daikokuya, Mikio Ito, Kazuhiko Ikeuchi
  • Publication number: 20130227344
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Application
    Filed: January 29, 2013
    Publication date: August 29, 2013
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Patent number: 8522073
    Abstract: A system, method, and computer program product replace a failed node storing data relating to a portion of a data file. An indication of a new storage node to replace the failed node is received at each of a plurality of available storage nodes. The available storage nodes each contain a plurality of shares generated from a data file. These shares may have been generated based on pieces of the data file using erasure coding techniques. A replacement share is generated at each of the plurality of available storage nodes. The replacement shares are generated by creating a linear combination of the shares at each node using random coefficients. The generated replacement shares are then sent from the plurality of storage nodes to the indicated new storage node. These replacement shares may later be used to reconstruct the data file.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: August 27, 2013
    Assignee: BitTorrent, Inc.
    Inventor: Bram Cohen
  • Patent number: 8522099
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 8522074
    Abstract: A method begins by a processing module receiving a first request to store a program. The method continues with the processing module determining first error coding dispersal storage function parameters and encoding a data segment of the program. The method continues with the processing module determining whether a second request to store the program is received. The method continues with the processing module encoding a second data segment of the program in accordance with the first error coding dispersal storage function parameters when the second request is not received. The method continues with the processing module changing the first error coding dispersal storage function parameters based on the another request to produce second error coding dispersal storage function parameters when the second request is received. The method continues with the processing module encoding the second data segment in accordance with the second error coding dispersal storage function parameters.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: August 27, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Timothy W. Markison, Gary W. Grube, S. Christopher Gladwin, Alan E. Holmes, Wesley Leggette, Jason K. Resch
  • Patent number: 8516299
    Abstract: A dispersed storage device for use within a dispersed storage network operates to select a set of dispersed storage units for storage of a data object by slicing an encoded data segment of a data object into error coded data slices, determining slice metadata for the error coded data slices, determining memory characteristics of dispersed storage units capable of storing the error coded data slices and selecting the set of dispersed storage units for storing the error coded data slices based on the slice metadata and the memory characteristics.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: August 20, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, S. Christopher Gladwin
  • Patent number: 8510595
    Abstract: A controller configures a plurality of solid state disks as a redundant array of independent disks (RAID), wherein the plurality of solid state disks store a plurality of blocks, and wherein storage areas of the plurality of solid state disks corresponding to at least some blocks of the plurality of blocks have different amounts of estimated life expectancies. The controller includes in data structures associated with a block that is to be stored in the storage areas of the plurality of solid state disks an indication that the block includes parity information corresponding to the RAID, wherein parity information comprises information corresponding to an error correction mechanism to protect against a disk failure.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Andrew Dale Walls, Daniel Frank Moertl
  • Patent number: 8504896
    Abstract: A method of operating a nonvolatile memory device including a memory cell array having first and second main cells for storing external input data, first spare cells for storing data for error correction code (ECC) processing on the data stored in the first and second main cells and second spare cells for storing data for ECC processing on the data stored in the first and second main cells which involves reading the data stored in the first spare cells, reading the data stored in the second main cells and the data stored in the second spare cells, and performing the ECC processing on the data read from the second main cells using the data read from the first spare cells and the data read from the second spare cells.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: August 6, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang Kyu Lee, Seung Jae Chung
  • Patent number: 8504847
    Abstract: A data element can be encoded into multiple encoded data elements using an encoding algorithm that includes an encoding function and one or more encoder constant. The encoded data elements can be organized into multiple pillars, each having a respective pillar number. Each of the pillars is sent to a different storage unit of a distributed storage network. To recover the original data element, the encoded data elements are retrieved from storage, and the encoder constant is recovered using multiple encoded data elements. Recovering the encoder constant allows the encoding algorithm originally used to encode the data elements to be determined, and used to recover the original data element. The security of the stored data is enhanced, because an encoded data element from a single pillar is insufficient to identify the encoder constant.
    Type: Grant
    Filed: April 18, 2010
    Date of Patent: August 6, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, Wesley Leggette
  • Publication number: 20130198560
    Abstract: A method begins by a dispersed storage (DS) processing module ingesting a plurality of data blocks of a large amount of data. The method continues with the DS processing module temporarily storing the plurality of data blocks and determining whether to not permanently store the plurality of data blocks. When the plurality of data blocks is to be permanently stored, the method continues with the DS processing module storing the plurality of data blocks and generating a group of partial redundancy data. When the plurality of data blocks is not to be permanently stored, the method continues with the DS processing module creating a new plurality of data blocks from other data blocks that are to be permanently stored and generating the group of partial redundancy data based on the new plurality of data blocks.
    Type: Application
    Filed: December 6, 2012
    Publication date: August 1, 2013
    Applicant: CLEVERSAFE, INC.
    Inventor: Cleversafe, Inc.
  • Patent number: 8495416
    Abstract: A system comprising an interface, a plurality of storage arrays, a data processing module, and a switch module. The interface receives data blocks from a host via a network. The data processing module connected between the interface and the plurality of storage arrays, wherein the data processing module is configured to (i) determine which ones of the data blocks each of a plurality of target processing modules of the storage arrays is to perform error checking and correcting processing, and (ii) transfer each of the data blocks from the interface to a respectively assigned one of the plurality of target processing modules. The switch module provides communication paths between the data processing module and the plurality of storage arrays.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: July 23, 2013
    Assignee: Marvell World Trade Ltd.
    Inventor: Pantas Sutardja
  • Patent number: 8495435
    Abstract: An apparatus, system, method, and machine-readable medium are disclosed. In one embodiment the apparatus includes an address swap cache. The apparatus also includes memory segment swap logic that is capable of detecting a reproducible fault at a first address targeting a memory segment. Once detected, the logic remaps the first address targeting the faulty memory segment with a second address targeting another memory segment. The logic stores the two addresses in an entry in the address swap cache. Then the memory segment swap logic receives a memory transaction that is targeting the first physical address and use the address to perform a lookup process in the address swap cache to determine if an entry exists that has the faulty address. If an entry does exist for that address, the logic then swaps the second address into the memory transaction for the first address.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: July 23, 2013
    Assignee: Intel Corporation
    Inventors: Tonia G. Morris, Lawrence D. Blankenbeckler
  • Patent number: 8489940
    Abstract: Methods and apparatus for managing exchange IDs for multiple asynchronous dependent I/O operations generated for virtual Fibre Channel (FC) target volumes. Features and aspects hereof allocate a range of exchange identifier (X_ID) values used in issuing a plurality of physical I/O operations to a plurality of physical FC target devices that comprise the virtual FC target volume. The plurality of physical I/O operations are dependent upon one another for completion of the original request to the virtual FC target volume and allow substantially parallel operation of the plurality of physical FC target devices. A primary X_ID is selected from the range of allocated X_ID values for communications with the attached host system that generated the original request to the virtual FC target volume.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: July 16, 2013
    Assignee: NetApp, Inc.
    Inventors: Howard Young, Srinivasa Nagaraja Rao
  • Patent number: 8489944
    Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: July 16, 2013
    Assignee: Intel Corporation
    Inventors: Warren Morrow, Pete Vogt, Dennis W. Brzezinski
  • Patent number: 8489943
    Abstract: A system for generating test signals to test characteristics of input-output (IO) cells includes a memory and a processor coupled together through an integrated circuit (IC) chip. The IC chip includes a controller configured to exchange signals between the memory and the processor through IO cells of the IC chip. The IC chip further includes a protocol sequence generator for generating test signals for testing characteristics of the IO cells.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 16, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Anil K. Dwivedi, Akhilesh Chandra, Ajay Arun Kulkarni
  • Patent number: 8489932
    Abstract: There is provided a server system that collects memory information at the time of occurrence of a failure if a failure occurs in the operating system so as to enable failure analysis. Stall monitoring of a firmware is performed by hardware and, if a stall is detected, a reset is performed. A memory has a memory area used by a boot loader of the firmware and a memory area used by another part of the firmware. It is determined based on a reset factor retained in a device whether the reset is a normal reset or a reset associated with the stall detection. In the case where the reset is a reset associated with the stall detection, information of the memory area of the memory used by the another part of the firmware at the time of occurrence of the stall is collected.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 16, 2013
    Assignee: NEC Corporation
    Inventor: Yutaka Hirata
  • Patent number: 8484536
    Abstract: Methods, systems, and apparatus, including computer program products, featuring generating a plurality of error-correcting code chunks from a plurality of data chunks. The error-correcting code chunks can be used to reconstruct one or more of the data chunks. The data chunks are allocated to a local group of storage nodes. The error correcting code chunks are allocated between the local group of storage nodes and one or more remote groups of storage nodes. Each remote group of storage nodes is allocated one or more unique error-correcting code chunks from the error-correcting code chunks. Any of the error-correcting code chunks not allocated to a remote group of storage nodes are allocated to the local group of storage nodes.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: July 9, 2013
    Assignee: Google Inc.
    Inventor: Robert Cypher
  • Patent number: 8479078
    Abstract: A distributed storage network generates a plurality of data segments from a data object and stores each of the plurality of data segments as a plurality of encoded data slices generated from an error encoding dispersal function. When the distributed storage network receives a modification request for the data object, it determines a size of the plurality of data segments of the data object from a segment size field and identifies one of the plurality of data segments requiring modification. The identified data segment is reconstructed from the plurality of encoded data slices and modified in accordance with the modification request.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: July 2, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, Bart Cilfone
  • Patent number: 8479040
    Abstract: Provided are a storage system and its control method having superb functionality of being able to notify an administrator of the extent of impact of a pool fault in an easy and prompt manner. The foregoing storage system and its control method manage a storage area provided by a storage medium by dividing it into multiple pools, provide a virtual logical device to a host system, dynamically allocate a storage area to the logical device according to a data write request from the host system for writing data into the logical device, move data that was written into the logical device to another pool according to the access status from host system to such data, identify, when a fault occurs in any one of the pools, an extent of impact of the fault based on the correspondence relationship of the logical device and the pool, and notify the identified extent of impact of the fault to an administrator.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: July 2, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Daisuke Shinohara, Yukinori Sakashita
  • Patent number: 8473778
    Abstract: Embodiments of the present invention relate to systems, methods and computer storage media for erasure coding data in a distributed computing environment. A sealed extent is identified that is comprised of two or more data blocks and two or more index blocks. The sealed extent is optimized for erasure coding by grouping the two or more data blocks within the optimized sealed extent together and grouping the two or more index blocks within the optimized sealed extent together. The optimized extent may also be erasure coded, which includes creating data fragments and coding fragments. The data fragments and the coding fragments may also be stored in the distributed computing environment. Additional embodiments include monitoring statistical information to determine if replication, erasure coding or a hybrid storage plan should be utilized.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: June 25, 2013
    Assignee: Microsoft Corporation
    Inventors: Huseyin Simitci, Yikang Xu, Haiyong Wang, Aaron William Ogus, Bradley Gene Calder
  • Patent number: 8468384
    Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 18, 2013
    Assignee: Thomson Licensing
    Inventors: Thomas Brune, Michael Drexler, Dieter Haupt
  • Patent number: 8468385
    Abstract: Method and system for managing error related events while a system is processing input/output (“I/O”) requests for accessing storage space is provided. Various components are involved in processing the I/O requests. Some of these components may also have sub-components. Events related to the various components are classified with respect to their severity levels. Threshold values for a frequency of these events is set and stored in a data structure at a memory location. When an event occurs, the severity level and the threshold value for the event are determined from the data structure. The actual frequency is then compared to the stored threshold value. If the threshold value is violated and there is an alternate path to route the I/O request, then the affected component is restricted and the alternate path is used to route the I/O request.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: June 18, 2013
    Assignee: Netapp, Inc.
    Inventors: Sridhar Balachandriah, Bhaskar Singhal
  • Patent number: 8464095
    Abstract: In general, embodiments of the invention relate to storing data by receiving a request to write data, in response the request, selecting a first RAID grid location in a RAID grid to write the data, determining a first physical address in persistent storage corresponding to the first RAID grid location, generating a first page comprising the data and first out-of-band (OOB), wherein the first OOB comprises a first grid geometry for the RAID grid, and a first stripe membership for the page within the RAID grid, and writing the first page to a first physical location in persistent storage corresponding to the first physical address.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: June 11, 2013
    Assignee: DSSD, Inc.
    Inventor: Jeffrey S. Bonwick
  • Publication number: 20130145207
    Abstract: Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 6, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Micron Technology, Inc.
  • Patent number: 8458512
    Abstract: In order to enable a rewrite of stored data to be omitted and to reduce a processing time of error concealment even if an error is detected in a process for sequentially storing variable-length data in a memory and the rewrite of the stored data is necessary, variable-length data from which an error is not detected is sequentially stored at and after a predetermined position in the memory, and error information that includes a restoration address that corresponds to an area in which variable-length data from which an error is detected is to be stored and that specifies variable-length data stored earliest in the memory from among data to be replaced with error concealment data is stored at a position preceding the predetermined position, when the error is detected.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: June 4, 2013
    Assignee: Fujitsu Limited
    Inventors: Hirofumi Nagaoka, Yasuhiro Watanabe, Taro Hagiya
  • Publication number: 20130138999
    Abstract: An internode put requesting unit detects a time-out with respect to a put request issued to the next node in the order of a multiplexing chain and notifies a put/get executing unit of the time-out. The put/get executing unit sends an error to the previous node in the order of the multiplexing chain or a client and instructs a put-failed-data synchronizing unit to synchronize data failed to be put, and the put-failed-data synchronizing unit performs a synchronization process. A primary makes other put requests wait until completion of the synchronization process. Furthermore, when having received the error, the client issues a get request to the tail end of the multiplexing chain.
    Type: Application
    Filed: September 6, 2012
    Publication date: May 30, 2013
    Applicant: Fujitsu Limited
    Inventors: Masahisa TAMURA, Yasuo Noguchi, Toshihiro Ozawa, Munenori Maeda, Tatsuo Kumano, Ken Iizawa, Jun Kato
  • Publication number: 20130138995
    Abstract: A method for managing multiple nodes hosting multiple memory segments, including: identifying a failure of a first node hosting a first memory segment storing a hypervisor; identifying a second memory segment storing a shadow of the hypervisor and hosted by a second node; intercepting, after the failure, a hypervisor access request (HAR) generated by a core of a third node and comprising a physical memory address comprising multiple node identification (ID) bits identifying the first node; modifying the multiple node ID bits of the physical memory address to identify the second node; and accessing a location in the shadow of the hypervisor specified by the physical address of the HAR after the multiple node ID bits are modified.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: Oracle International Corporation
    Inventors: Ramaswamy Sivaramakrishnan, Jiejun Lu, Aaron S. Wynn
  • Patent number: 8453010
    Abstract: A method for recovering data from a failed tape cartridge is presented. The reliability of a tape cartridge is assessed via the number of read errors encountered. If the number or read errors is excessive, the tape cartridge is deemed unreliable and the tape cartridge is restricted from storing anymore data. A search is performed to look for duplicate data and if found a copy of the duplicate data is stored to a replacement tape cartridge. The replacement tape cartridge assumes all identity of the original failed tape cartridge.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 28, 2013
    Assignee: Spectra Logic Corp.
    Inventors: Nathan Christopher Thompson, Matthew Thomas Starr, Walter Wong
  • Patent number: 8452933
    Abstract: Data written in the primary logical volume of the first storage device are transmitted to the third storage device via the second storage device, the data being written in the same location as the primary logical volume within the secondary logical volume in the third storage device; when transmission of the data stops among the first to the third storage devices, the respective second storage device and the third storage device manage locations in the secondary logical volume where the data held thereby are to be written; and, when transmission of the data resumes among the first to the third storage devices, the locations in the secondary logical volume managed by the respective second and the third storage devices are aggregated, the data to be written in the respective aggregated location in the secondary logical volume being transmitted from the first storage device to the third storage device via the second storage device.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: May 28, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Shintaro Inoue, Katsuhiro Okumoto
  • Patent number: 8448018
    Abstract: The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 21, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 8448020
    Abstract: A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: May 21, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Steven Mark Hoffman, Jason K. Resch, Gary W. Grube, Timothy W. Markison
  • Publication number: 20130124915
    Abstract: A remote copy system includes a first storage device performing data transmission/reception with a host computer, a second storage device receiving data from the first storage device, and a third storage device receiving data from the second storage device. The first storage device includes a logical volume, the second storage device includes a logical volume being a virtual volume, and the third storage device includes a logical volume. The first storage system changes the state of a first pair of the logical volumes based on the state of a second pair of the logical volumes. With such a remote copy system and a method for use therein, any data backup failure can be prevented.
    Type: Application
    Filed: January 3, 2013
    Publication date: May 16, 2013
    Applicant: Hitachi, Ltd., Intellectual Property Group
    Inventor: Hitachi, Ltd., Intellectual Property Group
  • Publication number: 20130117604
    Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 9, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Chang Wan Ha
  • Patent number: 8433947
    Abstract: A computer executes a data allocation control program to control allocation of data in a plurality of disk nodes. A redundancy restoration module executes a redundancy restoration procedure by commanding disk nodes to create a new copy of redundancy-lost data. An error message reception module receives a write error message indicating a write error in a storage device during the redundancy restoration procedure and records an identifier of the faulty storage device in an error record memory. A copy command module identifies accessed data in the faulty storage device and commands a relevant disk node to create a copy of the identified data in the faulty storage device in the case where there is no redundant copy of the data.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: April 30, 2013
    Assignee: Fujitsu Limited
    Inventors: Yasuo Noguchi, Hideki Sakurai
  • Patent number: 8433869
    Abstract: In one aspect, a method includes forming a virtualized grid consistency group to replicate a logical unit, running a first grid copy on a first data protection appliance (DPA) replicating a first portion of the logical unit, running a second grid copy on a second DPA replicating a second portion of the logical unit, sending IOs to the first DPA if the IOs are to a first set of offsets and sending IOs to the second DPA if the IOs are to a second set of offsets.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: April 30, 2013
    Assignee: EMC International Company
    Inventors: Assaf Natanzon, Yuval Aharoni
  • Patent number: 8429444
    Abstract: A multipurpose storage system based upon a distributed hashing mechanism with transactional support and failover capability is disclosed. According to one embodiment, a system comprises a client system in communication with a network, a secondary storage system in communication with the network, and a supervisor system in communication with the network. The supervisor system assigns a unique identifier to a first node system and places the first node system in communication with the network in a location computed by using hashing. The client system stores a data object on the first node system.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: April 23, 2013
    Assignee: Scality, S.A.
    Inventors: Vianney Rancurel, Olivier Lemarie, Giorgio Regni, Alain Tauch, Benoit Artuso, Jonathan Gramain, Bertrand Demiddelaer
  • Patent number: 8423822
    Abstract: A storage system, method and program product, the system comprising: storage devices; and a controller configured to: provide virtual volumes to a host computer; manage logical units on the storage device and storage pools; allocate, in response to receiving a write request to a virtual volume, a storage region of the storage pools; and store data related to the write request in the storage region allocated, wherein the controller is further configured to: allocate first storage region in first storage pool to first virtual volume based on first size of the first storage region or the first virtual volume; allocate a second storage region in a second storage pool to a second virtual volume of the plurality of virtual volumes based on a second size of the second storage region or the second virtual volume.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: April 16, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Takahito Sato
  • Patent number: 8423724
    Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: April 16, 2013
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Kelvin Marino, Michael Rubino, Mike H. Amidi
  • Patent number: 8423841
    Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: April 16, 2013
    Assignee: Marvell International Ltd.
    Inventors: Winston Lee, Albert Wu, Chorng-Lii Liou
  • Patent number: 8412876
    Abstract: A storage device with multiple storage units, which is applicable to a system end. The storage device is a hard disk drive (HDD) or solid state disk (SSD) with a standard size. The storage device includes a first storage unit and at least one memory storage unit. The memory storage unit and the first storage unit serve to back up and update each other. The storage device further includes a multiplex control unit and a power control unit connected to the multiplex control unit. According to the decision of the multiplex control unit, the power control unit controls turning on/off of the first storage unit and the memory storage unit.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: April 2, 2013
    Assignee: Felicity Taiwan Corporation
    Inventor: Chun-Te Yu
  • Patent number: 8412979
    Abstract: An apparatus, system, and method are disclosed for data storage with progressive redundant array of independent drives (“RAID”). A storage request receiver module, a striping module, a parity-mirror module, and a parity progression module are included. The storage request receiver module receives a request to store data of a file or of an object. The striping module calculates a stripe pattern for the data. The stripe pattern includes one or more stripes, and each stripe includes a set of N data segments. The striping module writes the N data segments to N storage devices. Each data segment is written to a separate storage device within a set of storage devices assigned to the stripe. The parity-mirror module writes a set of N data segments to one or more parity-mirror storage devices within the set of storage devices. The parity progression module calculates a parity data segment on each parity-mirror device in response to a storage consolidation operation, and stores the parity data segments.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 2, 2013
    Assignee: Fusion-IO, Inc.
    Inventors: David Flynn, David Atkisson, Jonathan Thatcher, Michael Zappe
  • Publication number: 20130080826
    Abstract: Disclosed herein is a semiconductor device that includes a verification circuit and an error processing circuit. the verification circuit verifies second bits of an external command to generate the verification result signal. The error processing circuit supplies a follow-up signal to a bank control circuit after a lapse of a first period and a second period when the verification result signal indicates a fail state during a write operation. The first period corresponds to a write latency indicating a period between when a write command is generated and when a data associated with the write command is supplied from outside. The second period corresponds to a write recovery latency indicating a period between when the bank control circuit issues a write execution signal to start writing the data to memory cells and when the write operation is completed.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 28, 2013
    Applicant: Elpida Memory, INC.
    Inventor: Elpida Memory, INC.
  • Patent number: 8407517
    Abstract: A system comprising a plurality of storage systems, which uses storage devices of multiple levels of reliability. The reliability as a whole system is increased by keeping the error code for the relatively low reliability storage disks in the relatively high reliability storage system. The error code is calculated using hash functions and the value is used to compare with the hash value of the data read from the relatively low reliability storage disks.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: March 26, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Kawaguchi, Akira Yamamoto
  • Publication number: 20130073895
    Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).
    Type: Application
    Filed: November 13, 2012
    Publication date: March 21, 2013
    Applicant: LSI CORPORATION
    Inventor: LSI CORPORATION
  • Publication number: 20130067272
    Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.
    Type: Application
    Filed: November 8, 2012
    Publication date: March 14, 2013
    Applicant: THOMSON LICENSING
    Inventor: Thomson Licensing