Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

Abstract: A non-volatile memory system may be configured to generate a codeword with first-type parity bits and one or more second-type parity bits. If a storage location in which the codeword is to be stored includes one or more bad memory cells, the bit sequence of the codeword may be arranged so that at least some of the second-type parity bits are stored in the bad memory cells. During decoding, a first set of syndrome values may be determined for a first set of check nodes and a second set of syndrome values may be determined for a second set of check nodes. In some examples, a syndrome weight used for determining if convergence is achieved may be calculated using check nodes that are unassociated with the second-type parity bits.

Abstract: Apparatuses and methods related to column repair in memory are described. The sensing circuitry of an apparatus can include a first sensing component, a second sensing component, and a third sensing component. The second sensing component can include a defective sense amplifier that is column repaired. The apparatus can include a controller configured to use the sensing circuitry to shift data from the first sensing component to the third sensing component by transferring the data through the second sensing component. The second sensing component can be physically located between the first sensing component and the third sensing component.

Abstract: A repair device and a semiconductor device are disclosed, which relate to a technology for supporting a plurality of post package repairs (PPRs). The repair device may include a plurality of PPR fuse sets. The repair device may be configured such that if any one of the plurality of PPR fuse sets is selected, the remaining PPR fuse sets may be initialized.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.

Abstract: A storage control device configured to control a storage device including a plurality of groups each of which includes a plurality of storage regions, the storage control device includes a memory and a processor coupled to the memory and configured to store, into the memory, information associated with each of the plurality of groups and indicating whether an error region in which an error is detected is included in at least one of the plurality of storage regions of each of the plurality of groups, identify a first group including the error region from the plurality of groups based on the information associated with the plurality of groups, read data from a plurality of storage regions included in the identified first group, and identify the error region included in the first group based on the read data.

Abstract: Systems, apparatuses and methods provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, the technology identifies whether the redundant portion includes one or more remaining memory cells, and in response to an identification that the redundant portion includes the one or more remaining memory cells, the one or more remaining memory cells in the redundant portion are substituted for the one or more failed memory cells.

Abstract: Systems, apparatuses and methods may provide for initiating an erase of a block of non-volatile memory in response to an erase command, wherein the block includes a plurality of sub-blocks. Additionally, a failure of the erase with respect to a first subset of the plurality of sub-blocks may be tracked on an individual sub-block basis, wherein the erase is successful with respect to a second subset of the plurality of sub-blocks. In one example, use of the second subset of the plurality of sub-blocks is permitted, whereas use of the first subset of the plurality of sub-blocks is prevented.

Abstract: An error in a physical memory realization at a physical memory address is detected. A first physical memory line corresponding to the physical memory address is determined. It is ensured that a duplicate of data content associated with the first physical memory line is associated with a second physical memory line. The physical memory address is remapped to use the second physical memory line for data content.

Abstract: An authenticating service of a chip having an intrinsic identifier (ID) is provided. The authenticating device includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

Abstract: A data storage device includes a nonvolatile solid-state memory comprising a plurality of blocks and a controller configured to maintain age data associated with each of a plurality of memory units, wherein each memory unit comprises one or more of the plurality of blocks, determine a capacity of the nonvolatile solid-state memory, and perform a wear leveling operation on a first memory unit of the plurality of memory units based at least in part on the age data associated with the first memory unit and the capacity of the nonvolatile solid-state memory.

Abstract: A memory access method, a storage-class memory, and a computer system are provided. The computer system includes a memory controller and a hybrid memory, and the hybrid memory includes a dynamic random access memory (DRAM) and a storage-class memory (SCM). The memory controller sends a first access instruction to the DRAM and the SCM. When determining that a first memory cell set that is of the DRAM and to which a first address in the received first access instruction points includes a memory cell whose retention time is shorter than a refresh cycle of the DRAM, the SCM may obtain a second address having a mapping relationship with the first address. Further, the SCM converts, according to the second address, the first access instruction into a second access instruction for accessing the SCM, to implement access to the SCM.

Abstract: A method and system for file transfer over a messaging infrastructure are provided. The method includes dividing a file into multiple portions. The method includes generating for a current portion of a file, except for the first portion in a file, a first hash summarizing the state of the file up to, but not including, the current portion and a second hash summarizing the state of the file up to and including the current portion. The method includes sending the first and second hashes with the file portion. The second hash may be used at a target for comparing to a first hash of a subsequent file portion, for example, by recreating the second hash from the current state of the received file on the target.

Abstract: A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a first type and a signal presence detect unit configured to provide configuration data associated with a memory package of a second type to the memory controller. The configuration data may be used to configure the memory controller to interface with the memory package of a first type.

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

Abstract: Example apparatus and methods monitor conditions in a tiered storage system. The conditions monitored may include the availability of different numbers and types of devices including an erasure code based object storage system. The conditions monitored may also include the availability and type of devices available to the erasure code based object storage system. A redundancy policy for storing an item using the erasure code based object storage system may be determined based on the conditions. Erasure codes associated with the item may then be stored in the erasure code based object storage system as controlled, at least in part, by the redundancy policy. The redundancy policy for the erasure codes may be updated dynamically in response to changing conditions on the tiered storage system.

Abstract: A memory control circuit has an error determination circuitry to determine whether an error-bit number is larger than a predetermined threshold value set based on a maximum number of error bits correctable by the error correction circuitry, when it is detected by the error detector that an error is contained in data read for verification of data written to the first memory or in data read from the first memory, and an access controller to control access to a second memory having an access priority lower than the first memory when it is determined that the error-bit number is larger than the threshold value, and to control access to the first memory without accessing the second memory when it is determined that the error-bit number is equal to or less than the threshold value.

Abstract: Systems and methods which implement repair bandwidth control techniques, such as may provide a feedback control structure for regulating repair bandwidth in the storage system. Embodiments control a source object repair rate in a storage system by analyzing source objects represented in a repair queue to determine repair rate metrics for the source objects and determining a repair rate based on the repair rate metrics to provide a determined level of recovery of source data stored as by the source objects and to provide a determined level of repair efficiency in the storage system. For example, embodiments may determine a per storage object repair rate (e.g., a repair rate preference for each of a plurality of source objects) and select a particular repair rate (e.g., a maximum repair rate) for use by a repair policy. Thereafter, the repair policy of embodiments may implement repair of one or more source objects in accordance with the repair rate.

Abstract: A method for encoding a video signal includes estimating a space requirement for encoding a tile of a video frame, writing a first value in a first value space of the bitstream, wherein the first value describes a size of a second value space, and defining the second value space in the bitstream, wherein the size of the second value space is based on an estimated space requirement. The method also includes writing encoded content in a content space of the bitstream, determining a size of the content space subsequent to writing encoded content in the content space, and writing a second value in the second value space of the bitstream, wherein the second value describes the size of the content space.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

Abstract: A method of operating a storage controller is provided. The method includes receiving host data for storage within a storage system, the storage system configured as a plurality of sequentially numbered data blocks, each comprising a plurality of pages, storing the host data in a data buffer, and organizing the host data into storage data pages. The method also includes sequentially writing the storage data into page stripes, reading the storage data from the pages, and comparing the read storage data with the host data stored in the data buffer. The method further includes for each page of storage data that fails the comparison, rewriting the storage data for that page into a different page, and when at least some of the storage data within the storage system passes the comparison, transmitting a signal to the host.

Abstract: In a data recovery method, there are a server and a plurality of storage devices each storing a copy of a data block. The server divides each copy of the data block into N segments corresponding to a sequence of N partitions. And then, the server constructs a plurality of different trial data blocks each including N segments corresponding to the sequence of N partitions. After that, the server calculates a check code for each trial data block, and continues to identify a trial data block having a check code identical to a pre-stored standard check code of the data block. At last, the server replaces at least one of the copies of the data block with the identified trial data block having the check code identical to the pre-stored standard check code.

Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.

Abstract: A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Abstract: An error-resilient memory device includes sets of memory blocks and redundant memory blocks for storing a set of data bits. A memory block includes a set of memory cells, each memory cell is adjacent to at least two other memory cells, and a memory block is formed by a matrix of the set of memory cells. In a row-folded implementation, a word line is connected to each memory cell, and a set of bit lines is connected to the corresponding set of memory cells. In a column-folded implementation, a bit line is connected to each memory cell, and a set of word lines is connected to the corresponding set of memory cells. A redundant memory block is used to store the set of data bits when the memory block includes a fault.

Abstract: A semiconductor device may include normal memory cells, redundancy memory cells, a fuse array, and a controller. The normal memory cells may be coupled to a plurality of word lines and bit lines. The redundancy memory cells may be coupled to a plurality of word lines and bit lines, and may replace one or more normal memory cells that are defective. The fuse array may include a redundancy address storage region configured to store addresses of the redundancy memory cells, an error correction information storage region configured to store error correction information for correcting errors of addresses of the redundancy memory cells, stored in the redundancy address storage region, and a weak address storage region configured to store an address of a weak cell among the normal memory cells. The controller may perform a repair operation based on a redundancy address and perform a refresh operation on a weak cell corresponding to the address of the weak cell.

Abstract: A solid state disk (SSD) device has a set of data transfer parameters which regulate I/O operations of the SSD device. The temperature of the SSD device is monitored using temperature readings from a temperature sensor. The temperature of the SSD device satisfies a temperature threshold. A data transfer modification is determined. The data transfer modification is capable of modifying one or more data transfer parameters of the set of data transfer parameters. The set of data transfer parameters is modified using the data transfer modification in response to the temperature of the SSD satisfying the temperature threshold. One or more I/O operations are completed with the SSD device using the modified set of data transfer parameters.

Abstract: Method and apparatus for testing the memory components of an integrated Circuit (IC) using a routing logic and a built-in design for test (DFT) hardware processing device. Based on input provided from an interface controller to the IC, the IC is tested according to one of at least two modes. In a first mode, the built-in DFT hardware processing device executes a test that checks for faults in the physical memory of the IC. In a second mode, the built-in DFT hardware processing device executes a test that checks for faults in the error correction logic of the IC. By using the same routing logic and built-in DFT hardware processing device, tests of the memory components according to the first and second mode can be executed on an automatic and serial basis, even after the manufacture of the IC.

Abstract: A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

Abstract: A solid state disk (SSD) device has a set of data transfer parameters which regulate I/O operations of the SSD device. The temperature of the SSD device is monitored using temperature readings from a temperature sensor. The temperature of the SSD device satisfies a temperature threshold. A data transfer modification is determined. The data transfer modification is capable of modifying one or more data transfer parameters of the set of data transfer parameters. The set of data transfer parameters is modified using the data transfer modification in response to the temperature of the SSD satisfying the temperature threshold. One or more I/O operations are completed with the SSD device using the modified set of data transfer parameters.

Abstract: Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.

Abstract: A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data.

Abstract: Performance improvement features can improve the performance of read processes under the right conditions. In order to selectively use the performance improvement features, the system conducts active read sampling to obtain information about bit error rate and then enables the performance improvement feature(s) for future read processes based on the information about bit error rate.

Abstract: In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode.

Abstract: A solid state disk (SSD) device has a set of data transfer parameters which regulate I/O operations of the SSD device. The temperature of the SSD device is monitored using temperature readings from a temperature sensor. The temperature of the SSD device satisfies a temperature threshold. A data transfer modification is determined. The data transfer modification is capable of modifying one or more data transfer parameters of the set of data transfer parameters. The set of data transfer parameters is modified using the data transfer modification in response to the temperature of the SSD satisfying the temperature threshold. One or more I/O operations are completed with the SSD device using the modified set of data transfer parameters.

Abstract: A solid state disk (SSD) device has a set of data transfer parameters which regulate I/O operations of the SSD device. The temperature of the SSD device is monitored using temperature readings from a temperature sensor. The temperature of the SSD device satisfies a temperature threshold. A data transfer modification is determined. The data transfer modification is capable of modifying one or more data transfer parameters of the set of data transfer parameters. The set of data transfer parameters is modified using the data transfer modification in response to the temperature of the SSD satisfying the temperature threshold. One or more I/O operations are completed with the SSD device using the modified set of data transfer parameters.

Abstract: A method for managing a failed memory module, including: receiving a first request to access a first memory address; identifying a memory module identifier (ID) from an end bit segment of the first memory address in the first request; generating, based on the memory module ID matching the failed memory module, a first revised memory address from the first memory address; and sending the first request with the first revised memory address to a memory controller for interpretation.

Abstract: A method and system are provided for back-up and restoration of data between volatile and flash memory. The method for controlling back-up of data to flash memory includes: organizing back-up data into stripes, wherein a stripe is a set of pages across all available flash memory devices, dies and planes which have the same block and page address; maintaining metadata indicating locations of known bad planes and grown bad planes; using the metadata when writing back-up data to determine which planes to send cache program commands to; and sending cache program commands to three or more stripes of data simultaneously including providing an indication in the stripe that the stripe is handling a cache program command. If a grown bad block is encountered while saving a stripe of data, the stripe of data is re-written to the next available page address avoiding the grown bad block.

Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

Abstract: A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.

Abstract: Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.

Abstract: Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device.

Abstract: An integrated circuit device for correcting errors in data read from memory cells includes a decoder, an encoder and a data management module. The data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing a code-rate used by the encoder, wherein a virtual change to the decoder and the encoder occur to change the code rate.

Abstract: An exemplary embodiment provides an electronic device including a controller, a first flash memory and a second flash memory. The first flash memory stores a first data sector. The second flash memory stores a second data sector, wherein the first data sector and the second data sector are the same, and the first data is stored in a plurality of pages of the first flash memory and the second data is stored in a plurality of pages of the second flash memory. The controller produces a third data according to the first data sector and the second data sector when the controller determines that the first data sector stored in the first flash memory is damaged.

Abstract: A semiconductor storing device and a redundancy method thereof are provided. The semiconductor storing device is for example a NAND flash memory, which includes: a storing array including a storing area and a redundancy storing area with a redundancy element; a page buffer; a row selecting circuit; an ECC circuit; and an I/O buffer. The row selecting circuit transforms defect data included in core data retained by a cache register into redundancy data retained by a redundancy cache register, and provides the transformed data to the ECC circuit, and the data corrected by the ECC circuit as the core data is written to the cache register again. During this period, the row selecting circuit outputs the corrected data retained in the cache register to the I/O buffer.

Abstract: Systems and methods for detection of defects on a magnetic storage medium. The method comprises: (1) receiving incoming detected data generated by reading information recorded on a storage medium, (2) identifying the defects in the storage medium based on comparison between the incoming detected data and a data pattern wherein the data pattern is predetermined; and (3) storing location information indicative of locations of the defects on the storage medium.

Abstract: Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block corresponding to a write access request from a first processor to the persistent memory, a cache controller prevents any read access of a copy of the given data block in an associated cache. The cache controller prevents any read access while detecting an acknowledgment that the given data block is stored in the persistent memory is not yet received. Until the acknowledgment is received, the cache controller allows write access of the copy of the given data block in the associated cache only for a thread in the first processor that originally sent the write access request. The cache controller invalidates any copy of the given data block in any cache levels below the associated cache.

Abstract: Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.

Abstract: A peripheral device and a method for programming the read/writeable memory of the RFID circuitry by communications between either RF antenna or bus communications port controller interface or both. In the peripheral device, an EEPROM, bus communications controller interface, NFC interface, antenna, and logic controller operate to receive and transmit configuration and calibration data between a wireless personal area network circuit and an external wireless personal area network enabled device. The dual interfaced EEPROM is operable to share or partition its EEPROM between an NFC interface and a bus communications controller.