Abstract: A method for flash sparing on a solid state drive (SSD) includes detecting a failure from a primary memory device; determining if a failure threshold for the primary memory device has been reached; and, in the event the failure threshold for the primary memory device has been reached: quiescing the SSD; and updating an entry in a sparing map table to replace the primary memory device with a spare memory device.

Abstract: A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation.

Abstract: A self-repairing memory system includes memory including memory elements and redundant memory elements. The memory elements include a plurality of memory cells. A memory repair module identifies non-operational memory cells and selects at least one memory element including the non-operational memory cells. A first repair sub-circuit soft repairs the memory by substituting the selected memory elements with the redundant memory elements. A second repair sub-circuit hard repairs the memory based on the substitutions.

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.

Abstract: A method and system for a non-volatile memory (NVM) with multiple bits error correction are provided and may include detecting bit errors in a memory element, of a NVM array integrated within a chip, which remain uncorrected after forward error correction. A redundant memory element may be utilized when the errors may be detected utilizing a cyclic redundancy check, may be within the NVM array, and may include secure information. Access to the secure information and/or the chip may be disabled when the errors are detected. The FEC operation may include one or both of an error location operation and a correction operation. The errors may be corrected when a location may be known to include the errors. The NVM array may be partitioned into regions. At least one of the redundant memory elements may be substituted in place of the memory element based on a substitution priority.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.

Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

Abstract: A BISR mode and associated method for testing memory. All redundant elements of the memory including the ones which are not used are tested, and interaction between redundant elements of the memory and adjacent functional memory are checked. Repair information is used to repair the memory. In addition, redundant elements which are not needed to be used for repairing the memory are forced to be used, such as by faking defects to remap good elements with redundant elements.

Abstract: A recording medium having a spare area for defect management and the management information of the spare area, a spare area allocation method, and a defect management method. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated.

Abstract: Provided is a semiconductor memory device in which it is possible to conduct a parallel test by comparison with an expected value after replacement with a redundant cell. The memory device includes a logic circuit for outputting an activated redundant hit signal when at least one determination circuit of determination circuits corresponding to respective ones of a plurality of redundant addresses is activated; a logic circuit for outputting an activated signal when all outputs of the circuits are inactive; and a selector for outputting a test-result mask signal when a redundant area is tested, and outputting the output of the logic circuit when a normal area is tested. The test result is forcibly passed when a memory array is tested and when a redundant address is accessed.

Abstract: A Field Programmable Gate Array (FPGA) circuit capable of operating through at least one fault. The FPGA circuit includes a configuration memory and an embedded microprocessor. The embedded microprocessor having access to the configuration memory, static modules, at least one relocatable module, and at least one spare module. The relocatable module being relocatable from a first target area to a second target area. The relocatable module being relocatable by manipulating a partial bitstream with the embedded microprocessor. The microprocessor calculating a plurality of bitstream changes, to relocate the at least one relocatable module using at least triple modular redundancy (TMR).

Abstract: A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.

Abstract: A redundant controller storage virtualization subsystem performing host-side IO rerouting and dynamic logical media unit reassignment. In one embodiment, the assignment of logical media unit owner can be dynamically reassigned to the receiving storage virtualization controller which was originally not the logical media unit owner such that the receiving storage virtualization controller becomes new logical media unit owner to execute the IO request. In another embodiment, the dynamic logical media unit reassignment can be performed according to the operating condition(s) of the storage virtualization system so as to improve the performance of the storage virtualization system. In a further embodiment, the controller storage virtualization subsystem can perform host-side IO rerouting when the timing for performing dynamic logical media unit reassignment is not reached.

Abstract: A method for writing a logical block into a storage pool includes receiving a request to write the logical block, selecting a block allocation policy, by a file system associated with the storage pool, from a set of allocation policies, obtaining a list of free physical blocks in the storage pool, allocating a physical block from the list of free physical blocks, based on the block allocation policy, and writing the logical block to the physical block.

Abstract: A drive apparatus of the present invention includes a recording/reproduction section and a drive control section. The drive control section performs a process including: determining whether or not replacement management information including a replacement physical address is found in the replacement management information list, the replacement physical address matching the physical address corresponding to the logical address included in the recording instruction, when the replacement management information is not found, as a first time pseudo-overwrite recording for a location indicated by the physical address corresponding to the logical address included in the recording instruction, performing a process; and when the replacement management information is found, as a second time or more pseudo-overwrite recording for a location indicated by the physical address corresponding to the logical address included in the recording instruction, performing a process.

Abstract: A memory repair circuit for repairing one or more failures in an embedded memory includes at least one fuse register and state machine circuitry coupled to the fuse register. The state machine circuitry implements a first state machine operative: (i) to receive status information regarding the one or more failures in the embedded memory; (ii) to determine whether the memory is repairable based on the status information; (iii) when the memory is deemed repairable, to store an address corresponding to a failed memory cell of the memory; (iv) to burn the address corresponding to the failed memory cell into the fuse register using a voltage source supplied to the memory repair circuit; and (v) to verify that the address corresponding to the failed memory cell was burned into the fuse register.

Abstract: A non-volatile storage device on a memory module comprising a plurality of memory devices is used to store the locations of defective parts on the memory module, such as data query (“DQ”) terminals, identified during a testing procedure. After testing, the non-volatile storage device, such as an electrically erasable programmable read only memory (“EEPROM”), may be accessed to determine specific memory devices such as dynamic random access memory (“DRAM”) which need to be repaired or replaced rather than re-testing the specific memory module.

Abstract: A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein.

Abstract: Methods and apparatus dynamically reconfigure storage or channel capacities in a memory system. A fully-buffered dual in-line memory module (DIMM) is configured for a particular storage capacity and a particular channel capacity. An error may be detected at a memory address in some portion of the DIMM. To resolve the problem, the storage capacity or the channel capacity may be reduced and the DIMM may be dynamically reconfigured according to the reduced capacity. For one embodiment the DIMM may be reconfigured by mapping the portion of the DIMM containing the error as unavailable and taking that portion off-line without taking the entire DIMM off-line. For another embodiment the DIMM may be reconfigured by throttling the DIMM at a reduced frequency. The portion of the DIMM containing the error may be retested at the reduced frequency. If no errors are detected, the DIMM may be made available at the reduced frequency.

Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.

Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

Abstract: A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers.

Abstract: Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The supply control circuit isolates a selected memory segment from the supply source when the selected memory segment is defective. The memory device replaces a defective memory segment with a redundant segment. Other embodiments are described and claimed.

Abstract: An address line failure handling apparatus includes a failed address line specifying unit that examines the address line connected to each bit and specifies a failed address line, an address line substituting unit in which an upper address line connected to an upper bit of the memory is connected with a branch address line branched off from a lower address line connected to a lower bit other than the upper bit, and that switches between an input from the upper address line and an input from the branch address line, and outputs any of the inputs to the upper bit, and an address line substitution instructing unit that instructs the address line substituting unit to switch from the upper address line to the branch address line branched off from the failed address line when the failed address line is specified.

Abstract: A method, apparatus and recording medium for managing defects are discussed. According to an embodiment, the method includes allocating at least one spare area to the recording medium, and at least one temporary defect management area to the spare area when a plurality of temporary defect management areas are to be separately provided; recording defect management information on a first temporary defect management area; and recording defect management information on a second temporary defect management area after the first temporary defect management area is full, the second temporary defect management area being allocated to the spare area.

Abstract: A redundancy replacement scheme for a semiconductor device repairing a faulty memory cell in a column select line group with a spare memory cell in the column select line group based on a physical or logical address of the selected row.

Abstract: A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

Abstract: System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region.

Abstract: A semiconductor memory device includes plural banks, defect relief circuits individually provided for these banks, a defective-address storing circuit that stores defective addresses, and a comparing circuit that compares an access-requested address with a defective address. The defective-address storing circuit and the comparing circuit are allocated in common to two banks, respectively. With this arrangement, a chip area can be decreased.

Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: A memory circuit comprises a first memory that stores data in a plurality of memory locations that are associated with memory addresses. A memory interface communicates with said first memory. A second memory communicates with said memory interface and stores memory addresses of defective memory locations that are identified in said first memory.

Abstract: An apparatus according to the present invention is designed to perform formatting processing on an information storage medium. The storage medium has a data storage area including a user data area and a spare area. The user data area is provided to write user data on, while the spare area includes a replacement block to be used as a replacement for a block that has been detected as a defective block. The replacement block stores instruction information that instructs to read data from the defective block when data is read from the replacement block. The apparatus includes a control section for controlling the formatting processing. In performing the formatting processing, the control section updates information stored in the replacement block such that when data is read from the replacement block, the data is not read from the defective block.

Abstract: A memory module comprises first memory that includes memory blocks, second memory, and non-volatile memory. A control module, during testing of at least one of the memory blocks having a first address, stores data from the at least one of the memory blocks in the second memory at a second address and stores the first and second addresses in the non-volatile memory. Content addressable memory (CAM) stores addresses of defective memory locations in the first memory and stores and retrieves data for the defective memory locations.

Abstract: A redundant controller storage virtualization subsystem performing host-side IO rerouting and dynamic logical media unit reassignment. In one embodiment, when a host IO request is received by a storage virtualization controller that is not a logical media unit owner of the logical media unit addressed by the IO request, the IO can be rerouted to the alternate storage virtualization controller, the logical media unit owner, to be executed. In another embodiment, the assignment of logical media unit owner can be dynamically reassigned to the receiving storage virtualization controller which was originally not the logical media unit owner such that the receiving storage virtualization controller becomes new logical media unit owner to execute the IO request. In a further embodiment, the dynamic logical media unit reassignment can be performed according to the operating condition(s) of the storage virtualization system so as to improve the performance of the storage virtualization system.

Abstract: A write-once recording medium recording/reproduction is carried out by performing a process including: determining whether or not replacement management information including a replacement physical address is found in the replacement management information list, the replacement physical address matching the physical address corresponding to the logical address included in the recording instruction, when the replacement management information is not found, as a first time pseudo-overwrite recording for a location indicated by the physical address corresponding to the logical address included in the recording instruction, performing a process; and when the replacement management information is found, as a second time or more pseudo-overwrite recording for a location indicated by the physical address corresponding to the logical address included in the recording instruction, performing a process.

Abstract: A memory circuit includes a memory interface. A first memory receives a first read address from the memory interface. A second memory stores addresses of defective memory locations found in the first memory, receives the first read address from the memory interface, compares the first read address to the addresses stored in the second memory, and, if a matching address is found, reads first data from the second memory. The first memory reads second data from a memory location in the first memory corresponding to the first read address. A multiplexer receives the second data and the first data from the first memory and the second memory, respectively, when the matching address is found, and selectively outputs one of the second data and the first data to the memory interface.

Abstract: A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.

Abstract: For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data.

Abstract: A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as well, deleting the documentation data relating to the over-programmed bits.

Abstract: A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.

Abstract: Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.

Abstract: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms.

Abstract: The present invention discloses a method for performing a defective-area management adaptive to a slipping replacement algorithm in an optical media with segmented sector/blocks, by either keeping buffering a read user data of the sector/block to a buffer memory, regardless of the read sector/block is defective, or keeping buffering the read user data to two different memories based on whether the sector/block is defective, thereby simplifying the complicated steps due to absence of interruption of data buffering, and therefore raising an operating performance.

Abstract: Apparatuses and methods for defect replacement when an optical storage medium is read are provided. When the defect management is LOW, a pick-up head retrieves a set of data from the optical storage medium; a defect detector detects whether there is a defect in the set; if yes, a processor determines whether a replacement for the defect is in the set; and if yes, an interface transmits the replacement from the set.

Abstract: A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN?1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk?1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.

Abstract: A cache memory built in a processor comprising a plurality of independent memory blocks, pass/fail information memory unit memorizing a presence/absence of a failure occurring in each of the memory blocks, and a screening control function substituting a sound memory block for a failed memory block based on a memory content in the pass/fail information memory unit.

Abstract: Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within the underlying circuit. For example, the auxiliary circuit may be tested although it is mounted such that the interconnects are hidden, i.e., inaccessible for testing purposes after assembly using conventional testing systems and methods. The systems and methods further allow for including excess circuits and/or excess interconnects that can be reconfigured to replace parts of the auxiliary circuit and/or micro-scale interconnects found defective during testing.