Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

Abstract: A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.

Abstract: A semiconductor memory device having a bank including a redundancy cell block and a plurality of normal cell blocks includes a plurality of normal data inputting/outputting units configured to respectively input/output data from the normal cell blocks in response to a first input/output strobe signal, a redundancy data inputting/outputting unit configured to input/output data from the redundancy cell block in response to the first input/output strobe signal, and a connection selecting unit configured to selectively connect the normal data inputting/outputting units and the redundancy data inputting/outputting unit to a plurality of local data lines in response to a address.

Abstract: A recording medium, comprising a data area including a segment region and a replacement region; a first control data area storing access control information for controlling access to the segment region; and a second control data area storing defect control information for controlling a defective region of the recording medium, replacing a data of the defective region to the replacement region, wherein the replacement region corresponding to the defective region of the segment region is handled as the segment region to the access control information.

Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.

Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.

Abstract: The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for repairing said faulty elements in said circuitry in response to data received from said fusebox; a data communication path linking said fusebox controller with said fusebox; wherein said data stored in said fusebox is compacted data and said at least one fusebox controller comprises a data expander for expanding said compacted data received from said fusebox via said data communication path prior to repairing any faulty elements in said circuitry.

Abstract: An information recording medium is provided that includes a data area for recording user data and a defect management area for recording a defect list for managing N number of defect areas existing in the data area, where N is an integer satisfying N?0. The defect list includes two or more blocks, and further includes a header located at a fixed position in the defect list and N number of defect entries, located subsequent to the header, including position information on the respective positions of the N number of defect areas. An anchor is located subsequent to the defect entries, and the header includes first update times information representing the number of times that the defect list has been updated. The anchor includes second update times information representing the number of times that the defect list has been updated.

Abstract: A method for repairing a main memory comprises the steps of: utilizing a spare memory to repair a main memory, wherein the spare memory includes a plurality of spare memory units; allocating a spare memory unit; determining whether available permutations of the allocated spare memory unit cover a newly found defect in the main memory; removing permutations of the spare memory unit failing to cover newly found defects in the main memory; and allocating another spare memory unit to repair the newly found defects if available permutations of the allocated spare memory unit fails to cover the newly found defects.

Abstract: An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.

Abstract: A disc defect management method and apparatus using a defect management area that can be updated, and a write once disc incorporating the method. A data area is disposed between a lead-in area and a lead-out area. The disc includes a defect management area (DMA) that is present in at least one of the lead-in area or the lead-out area, wherein defect information and defect management information are repeatedly recorded in the DMA according to a recording operation. Accordingly, the disc defect management method and apparatus enable effective use of the defect management area. The method is also applicable to a multi layer disc having a user data area on each layer. The defect information and the defect management information for an individual defect may include cumulative defect information and defect management information related to previously identified defects.

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract: Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair.

Abstract: Various embodiments herein include one or more of systems, methods, software, and/or data structures to test and evaluate unformatted optical media such as optical tape and optical discs. Advantageously, testing and evaluation can be performed earlier in the manufacturing process of the optical media to locate defects and/or other problems or issues with the optical media that can be addressed before additional manufacturing steps are performed and possible wasted. The systems and methods include at least two optical pickup units (OPUs), a first of which may be dedicated to writing digital data and the second of which may be dedicated to scanning, locating, tracking and/or reading the written data (when the optical media is moving in a first direction) in one of a plurality of manners. Information (e.g.

Abstract: A block management and replacement method for a flash memory is provided. The method includes grouping physical blocks of the flash memory into physical units and dividing the physical units as a usage area and a replacement area, wherein the physical blocks grouped into the same physical unit are accessed by using a multi-planes accessing command. The method also includes when one of the physical block of the physical unit in the usage area is damaged, replacing the physical unit having the damaged physical block with one physical unit selected from the replacement area and recording the undamaged physical block within the replaced physical unit if there is an applicable physical unit in the replacement area; and replacing the damaged physical block with one physical block selected from the replacement area if there is no applicable physical unit but an undamaged physical block in the replacement area.

Abstract: An optical disc 1 includes a defect management area (DMA). A plurality of defective area lists (TDFLs) and structure information (TDDS) are recorded in a temporary defect management area (TDMS) of the defect management area (DMA). The defective area lists (TDFLs) indicate at least one defective area which was detected during an access to the optical disc 1. The structure information (TDDS) includes a plurality of pieces of position information that indicate positions of the defective area lists (TDFLs). The plurality of pieces of position information, corresponding one-to-one to the defective area lists, are arranged in the structure information (TDDS) in an order in which the defective area lists (TDFLs) corresponding thereto are read out.

Abstract: Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be substituted for the failed cell. If two error correcting pointers in the array point to the same cell, a precedence rule dictates the array entry with the higher index (the entry created later) takes precedence. To count the number of error correcting pointers in use, a null pointer address can be employed to indicate that a pointer is inactive, an activation bit can be added, and/or a counter, that represents the number of error correcting pointers that are active. Mechanisms are provided for wear-leveling within the error correction structure, or for pairing this scheme with single-error correcting bits for instances where transient failures may occur. The architecture also employs pointers to correct errors in volatile and non-volatile memories.

Abstract: An aspect of the present disclosure relates to scanning reassigned data storage locations. In one example, a reassignment table is accessed to identify a deallocated data storage location and scan the deallocated data storage location for media defects.

Abstract: A method of and apparatus for managing disc defects in a disc using a temporary defect management area in the disc, and the disc, where the method includes recording in a data area user data; and recording in a temporary defect management area, which is present in at least one of a lead-in area and a lead-out area, which temporary defect information and temporary defect management information regarding the user data recorded in the data area are recorded. Accordingly, the method and apparatus are applicable to recordable discs and capable of effectively using the defect management area.

Abstract: A recording method for use by an apparatus and/or which is encoded on a computer readable medium includes selecting a defect management on mode or a defect management off mode that indicates whether defect management is to be performed or not while data is recorded in the recording medium, recording the data in the recording medium while defect management is performed on the recording medium, if the defect management on mode is selected, and recording the data in the recording medium without defect management, if the defect management off mode is selected.

Abstract: A semiconductor storage device can efficiently perform a refresh operation. A semiconductor storage device is provided which includes a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing. A controlling unit is further included monitoring an error count of data stored in a monitored block selected from the blocks and for refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.

Abstract: The present invention provides a built-in self-repairable memory. The invention repairs a faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses a lesser number of fuses to actually make a repair and thus results in a yield enhancement. The fuse data is stored in a compressed form and then decompressed as a restore happens at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area).

Abstract: An integrated circuit device contains a flash memory, a flash control unit for controlling the rewriting and reading on the flash memory, and a processor unit. The processor unit includes a normal mode and a fail-safe mode as the operating states. In normal mode, when a defect is detected during the verify operation after writing data onto the flash memory then any further use of the flash memory is stopped. In fail-safe-mode, when a defect is detected during the verify operation after writing data onto the flash memory, the error is corrected and flash memory usage continues. The operating state is normal mode, and when the verify operation detects a defect after normal mode erase operation, the operation shifts to fail-safe mode.

Abstract: A replacement data storage circuit stores an address of a defective memory cell. The replacement data storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of replacement data memory cells. The replacement data memory cells are connected to the word lines and the bit lines to store an address of a defective memory cell. Each of the word lines is connected to a plurality of replacement data memory cells and each of the bit lines is connected to one replacement data memory cell.

Abstract: A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved.

Abstract: A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spare building block and away from the building block with the defective entry, and avoiding in using the building block with the defective entry.

Abstract: A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged.

Abstract: During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location.

Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.

Abstract: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses. In at least one of first to n-th redundancy memory circuits, an address to be substituted by a redundant address is recorded and a redundancy selection signal is output when an access address is coincident with the programmed address. It is presupposed that repair addresses are programmed from the first to the n-th redundancy ROM circuits in an ascending order with regards to address. If it is detected under this condition that a redundancy selection signal has been output from the i+1'st redundancy memory circuit while no redundancy selection signal is being output from the i-th redundancy memory circuit, an SR flip-flop is set and the sequence of the substitution decision outputs is decided to be a reversed sequence.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: A semiconductor memory device having a first memory block used when it is determined to be used in a first case, a second memory block used as an alternative of the first memory blocks when it is determined to be used in a second case, a write section that writes determination data into the first memory block for making a determination at the time of the determination and writes the determination data into the second memory block and a read section that reads the determination data written into the first memory block by the write section for making a determination at the time of the determination and reads the determination data written into the second memory block by the write section.

Abstract: A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit.

Abstract: A recording medium and a method and apparatus for managing a defective area on the recording medium are provided. The method includes detecting an existence of a defective area within the data area of the recording medium; replacing the defective area with a replacement area in the spare area if the defective area is detected; writing in the spare area defect management information which cumulatively includes defect list information associated with the defective area detected in the step (a) and any defect list information previously written in the recording medium; and writing onto the recording medium positional information of the defect management information.

Abstract: A drive apparatus of the present invention includes a recording/reproduction section and a drive control section. The drive control section at least performs a process including: receiving a reproduction instruction; determining whether or not the reproduction of a latest replacement management information list has failed in response to the reproduction instruction; controlling the recording/reproduction section to reproduce location information before replacement recorded in the spare area and the user data area when the reproduction of the latest replacement management information list is determined to have failed; generating the latest replacement management information list based on the reproduced location information before replacement; and controlling the recording/reproduction section to record the latest replacement management information list at a predetermined location.

Abstract: An electronic device is provided including an input/output (I/O) interface, a plurality of memory elements, a controller coupled to the I/O interface and the plurality of memory elements. In the device, the controller configured for operating the plurality of memory elements during a normal operating mode of the electronic device, where responsive to receiving a command for replacing a selected memory sector in the electronic device during the normal operating mode, the controller is configured for identifying one or more available spare memory sectors in the electronic device and modifying at least one memory map in the electronic device to replace the selected memory sector with the one of the available spare memory sectors.

Abstract: The present invention is directed to repair a defective bit included in a memory in a semiconductor integrated circuit device for a display controller. The semiconductor integrated circuit device has a display memory capable of storing display data in a storage area, and a repair circuit capable of repairing a defect by replacing an area including a defect in the display memory with a spare storage area provided on the outside of a regular storage area for storing the display data. The device further includes a selector circuit provided on a transmission path of output data from the display memory and selectively replacing output data from the regular storage area with output data from the spare storage area in accordance with a control signal from the repair circuit. By selectively replacing the output data from the regular storage area with output data from the spare storage area in accordance with a control signal from the repair circuit, a defective bit is repaired.

Abstract: A system and method are provided for efficiently initializing a redundant array of independent disks (RAID). The method monitors host write operations and uses that information to select the optimal method to perform a parity reconstruction operation. The bins to which data access write operations have not occurred can be initialized using a zeroing process. In one aspect, the method identifies drives in the RAID array capable of receiving a ‘WriteRepeatedly’ command and leverages that capability to eliminate the need for the RAID disk array controller to provide initialization data for all disk array initialization transfers. This reduces the RAID array controller processor and I/O bandwidth required to initialize the array and further reduces the time to initialize a RAID array. In a different aspect, a method is provided for efficiently selecting a host write process for optimal data redundancy and performance in a RAID array.

Abstract: A reading apparatus for reading an information recording medium is provided. The information recording medium has a user data area for recording data and a spare area for recording replacements corresponding to registered defects of the user data area. The reading apparatus comprising a first storage device for storing the data read from the user data area, a second storage device for storing replacements, and a replacement controller for searching a corresponding replacement in the second storage device when a registered defect is found in the user data area, while reading the corresponding replacement and neighboring replacements thereof from the spare area of the information recording medium and storing the read replacements into the second storage device when the corresponding replacement is failed to be found in the second storage device.

Abstract: A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.

Abstract: A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs four-bit (the number of compressed bits) encoded data ef [3:0] sequentially. This encoded data ef [3:0] can indicate various kinds of failure information about RAM1. The capture circuit 4 latches the encoded data ef [3:0] which satisfies a predetermined latch condition, as latch data cf [3:0]. The capture circuit 4 can perform a serial shift operation of the latch data cf [3:0], and can output serially the latch data cf [3:0] as the serial data output So.

Abstract: A method for detecting disturb phenomena between neighboring blocks in non-volatile memory includes, sequentially erasing and writing test data (pattern) to each block of a plurality of blocks under test in the non-volatile memory at a first time point, dividing the plurality of blocks under test into a first block group and a second block group based on ordinal number included in each block of the plurality of blocks under test, reading data from each block of the first block group at a second time point, and comparing the data with the test data written at the first time point to generate a first detecting result, and determining applicability of each block of the first block group based on the first detecting result.

Abstract: A recording medium, and a method and apparatus for recording and reproducing data to/from the recording medium are disclosed. The recording medium having a data structure for managing a data area of the recording medium includes at least one physical access control (PAC) cluster, the at least one PAC cluster including information for managing logical overwriting to the recording medium, wherein each PAC cluster includes a PAC header, the PAC header being common to each PAC cluster, and a PAC specific information area, the area including information specific to each PAC cluster, wherein the PAC header includes segment information identifying at least one segment area in a user data area of the recording medium.

Abstract: Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials.

Abstract: It is an object to provide a semiconductor storage apparatus managing system for implementing a semiconductor storage apparatus which can be actually utilized in place of a hard disk apparatus. A semiconductor storage apparatus managing system SY for managing an apparatus lifetime of a semiconductor storage apparatus 10 having a semiconductor memory area 15 for storing data and a defective block substituting area 16 for substituting a defective block in the semiconductor memory area 15,includes a storage apparatus side controller 12 for detecting the number of consumed blocks in the defective block substituting area 16 and a host side controller 31 for predicting the apparatus lifetime of the semiconductor storage apparatus 10 based on a result of the detection and giving a notice of a result of the prediction.

Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.