Error Mapping Or Logging Patents (Class 714/723)
  • Patent number: 11436071
    Abstract: Methods, systems, and devices for error correction for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ameen D. Akel, Sean S. Eilert
  • Patent number: 11386973
    Abstract: The present embodiments provides a memory repair solution finding device and method which find a fault by testing a memory and find a repair solution in parallel and dynamically reconfigure the stored fault information to minimize a repair solution searching time with an optimal repair rate.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: July 12, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Sungho Kang, Ha Young Lee
  • Patent number: 11355207
    Abstract: A memory device, and a method of operating the memory device, includes a memory block configured to include a plurality of memory cells that are stacked to be spaced apart from each other on a substrate and to include word lines coupled to the plurality of memory cells, and bit lines and a source line coupled to both ends of strings including the plurality of memory cells, and peripheral circuits configured to perform an erase operation on the memory block, wherein the peripheral circuits are configured to perform the erase operation on the plurality of memory cells included in the memory block, and thereafter perform a defect detection operation on memory cells selected from among the plurality of memory cells depending on sizes of the plurality of memory cells.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang
  • Patent number: 11309054
    Abstract: A test operation condition of a volatile memory device is set such that an error probability is increased based on the test operation condition, compared to a normal operation condition for a normal operation of the volatile memory device. A test mode is set with respect to a test object region corresponding to at least a portion of a memory cell array included in the volatile memory device. A test operation of the volatile memory device is performed based on the test operation condition during the test mode to detect error position information of errors in data stored in the test object region. A runtime repair operation is performed with respect to the volatile memory device based on the error position information.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wonyeoung Jung, Hyunglae Eun, Dong Kim, Inhoon Park
  • Patent number: 11302409
    Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 12, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Xue Pitner, Deepanshu Dutta, Huai-Yuan Tseng, Ravi Kumar, Cynthia Hsu
  • Patent number: 11182232
    Abstract: The present disclosure relates to systems, methods, and computer readable media for identifying and responding to a panic condition on a storage system on a computing node. For example, systems disclosed herein may include establishing recovery instructions between a host system and a storage system in responding to a future instance of a panic condition. The storage system may provide an indication of a self-detected panic condition in a variety of ways. In response to identifying the panic condition, the host system may perform one or more recovery actions in accordance with recovery instructions accessible to the host system. This may include performing resets of specific components and reinitializing communication between the host system and storage system in less invasive ways than slower and more expensive conventional approaches for responding to panic conditions on computing nodes.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: November 23, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ayberk Ozturk, Scott Chao-Chueh Lee, Brennan Alexander Watt, Vishal Jose Mannanal
  • Patent number: 11163714
    Abstract: Embodiments of the present disclosure relate to a method, an apparatus, an electronic device and a computer readable storage medium for determining connection relationships among a plurality of chips. The method includes determining identity information of a plurality of chips managed by a host, the plurality of chips being connected by respective inter-chip communication interfaces for inter-chip communication. The method further includes allowing one or more of the plurality of chips to acquire identity information of other chips connected to the inter-chip communication interface of the one or more chips. The method further includes reading identity information of the other chips by means of a management interface of the one or more chips with regard to communicating with the host, so as to determine connection relationships among the plurality of chips.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 2, 2021
    Inventors: Xianglun Leng, Hefei Zhu, Qingshu Chen, Zhibiao Zhao, Xiaozhang Gong
  • Patent number: 11133068
    Abstract: A memory system includes: a memory device including a memory cell array and a page buffer circuit, the memory device performing a data program operation or a data erase operation, suspending the data program operation or the data erase operation in response to a suspend command, performing a data read operation of storing read data from the memory cell array in the page buffer circuit in response to a read command, and performing a data output operation of outputting the read data stored in the page buffer circuit; and a memory controller outputting a pre-resume command to the memory device between a first time at which the data read operation is complete and a second time at which the data output operation starts.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc
    Inventor: Chung Un Na
  • Patent number: 11056160
    Abstract: As disclosed herein, a non-volatile memory circuit includes an array of memory cells. The non-volatile memory circuit also includes circuitry for performing a hard write to selective bits of addressed cells simultaneously with a normal write to the other bits of the addressed cells during a write operation to the addressed cells.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: July 6, 2021
    Assignee: NXP USA, INC.
    Inventors: Richard Eguchi, Jon Scott Choy, Anirban Roy, Jacob Williams, Kerry Ilgenstein
  • Patent number: 11049586
    Abstract: A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: June 29, 2021
    Assignee: Mythic, Inc.
    Inventors: Malav Parikh, Zainab Nasreen Zaidi, Sergio Schuler, Natarajan Seshan, Raul A. Garibay, Jr., David Fick
  • Patent number: 10970245
    Abstract: An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 6, 2021
    Assignee: ICAT LLC
    Inventor: Robert Catiller
  • Patent number: 10936415
    Abstract: An error correction scheme in flash memory. Methods include extending a lifetime of a memory block, including: receiving an indication that an error occurred during a write operation at a first location in a memory block, the first location associated with a faulty page of the memory block; and performing a modified exclusive OR (XOR) scheme on the memory block by: performing a de-XOR operation that generates recovery data of the faulty page; storing the recovery data in a location different from the faulty page of memory; marking the faulty page for exclusion in future de-XOR operations; and performing a parity calculation that generates an updated parity value that includes all pages of the memory block that have been programmed except for the faulty page.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 2, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chris Yip, Piyush Sagdeo, Gautam Dusija, Vidhu Gupta
  • Patent number: 10866921
    Abstract: The present disclosure includes apparatuses and methods for an operating system cache in a solid state device (SSD). An example apparatus includes the SSD, which includes an In-SSD volatile memory, a non-volatile memory, and an interconnect that couples the non-volatile memory to the In-SSD volatile memory. The SSD also includes a controller configured to receive a request for performance of an operation and to direct that a result of the performance of the operation is accessible in the In-SSD volatile memory as an In-SSD main memory operating system cache.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Juyoung Jung
  • Patent number: 10811120
    Abstract: A method for performing page availability management of a memory device, the associated memory device and electronic device, and page availability management system are provided. The method may include: obtaining a set of page Error Correction Code (ECC) error tables of a non-volatile (NV) memory; based on a predetermined rule, finding respective local risky pages of at least one portion of blocks within a plurality of blocks according to the set of page ECC error tables, respectively, to generate local risky page counts respectively corresponding to page indexes; finding one or more global risky pages corresponding to one or more page indexes of the multiple page indexes according to the local risky page counts; and writing a global risky page table into the memory device, for controlling the memory device to skip using the one or more global risky pages of each of the plurality of blocks.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 20, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Wei Wu
  • Patent number: 10789012
    Abstract: A write method and a write apparatus for a storage device, where the write method includes: acquiring n numerical values that need to be written; determining n bits corresponding to the n numerical values, and information about a stuck-at fault included in the n bits; grouping the n bits into B groups of bits, so that the B groups of bits meet a grouping condition; and correspondingly writing the n numerical values according to information about a stuck-at fault included in each group of bits in the B groups of bits and a numerical value that needs to be written and that is corresponding to the information about the stuck-at fault included in each group of bits in the B groups of bits.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 29, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jiwu Shu, Jie Fan, Guanyu Zhu
  • Patent number: 10720209
    Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Kook Park, Young Hoon Oh, Chi Weon Yoon, Yong Jun Lee, Chea Ouk Lim
  • Patent number: 10698804
    Abstract: According to an aspect of an embodiment, a method of identifying inputs for automated computer-program testing operations may include obtaining a first input for a computer-readable program that is used during execution of the computer-readable program to cause the computer-readable program to take a first path during execution of the computer-readable program. The method may also include obtaining a second input for the computer-readable program that is used during execution of the computer-readable program to cause the computer-readable program to take a second path during execution of the computer-readable program. The method may also include identifying a sequence of values that is common to both the first input and the second input. The method may also include generating a third input that includes the sequence of values and a new value, the third input configured to be used during execution of the computer-readable program.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 30, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Erick Bauman, Praveen Murthy
  • Patent number: 10673946
    Abstract: A method includes identifying characteristics of a plurality of resources of one or more resource levels, where a data segment of a data object is one of a plurality of data types and is stored in memory of a dispersed storage network (DSN) according to a distributed agreement protocol (DAP). The method continues by generating a plurality of sets of DAP configuration information for the plurality of resource levels based on the characteristics. The method continues by receiving a data access request regarding a data segment and determining a data type of the data segment. When the data type is the first data type, the method continues with obtaining a first set of DAP configuration information and performing one or more distributed agreement protocol functions utilizing an identifier of the data and the first set of DAP configuration information to select storage units of the DSN.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: June 2, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Niall J. McShane, Tavis L. Potter, Jason K. Resch
  • Patent number: 10642686
    Abstract: A bit-scale memory correcting method comprises steps: providing a memory with a plurality of memory bytes each having M bits, wherein M is a positive integer; adding a correcting byte to each memory byte, wherein the correcting byte has N correcting bits, and wherein N is a positive integer and smaller than M; detecting whether there is any underperforming bit in all the memory bytes and correcting bytes; if no, terminating memory correction; if yes, using the non-underperforming bits of the correcting byte to replace the underperforming bits of the memory byte, wherein the quantity of the non-underperforming bits of the correcting byte is corresponding to the quantity of the underperforming bits of the memory byte. The present invention proposes a simple and fast memory bit correcting method to decrease the redundant bits for correcting memory bits.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 5, 2020
    Assignee: TARGPS TECHNOLOY CORP.
    Inventor: Chih-Jen Huang
  • Patent number: 10558398
    Abstract: Systems and methods for reducing read latency by storing a redundant copy of data are described. In one embodiment, the systems and methods include identifying data assigned to be written to a page of a storage device, storing the data in a page of a first die of the storage device, and saving at least one codeword from the data to a page of a second die. In some embodiments, the first die is associated with a first channel of the storage device and the second die is associated with a second channel of the storage device.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 11, 2020
    Assignee: Seagate Technology LLC
    Inventors: Kevin A. Gomez, Mark Ish, David S. Ebsen, Daniel J. Benjamin
  • Patent number: 10515041
    Abstract: An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 24, 2019
    Assignee: ICAT LLC
    Inventor: Robert Catiller
  • Patent number: 10229055
    Abstract: The disclosed technology provides for a solid state device that adaptively determines, responsive to receipt of a write command, whether or not to partition one or more individual logical blocks of data between multiple pages of a flash storage device. According to one implementation, the partitioning (e.g., spanning) determination is based on read frequency characteristics and the internal error correction code rate of the data.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: March 12, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Peng Li, David Scott Ebsen
  • Patent number: 10225205
    Abstract: Methods and apparatus for selection of memory locations for data access operations in a dispersed storage network (DSN) are disclosed. In various embodiments, a dispersed storage (DS) processing module of the DSN receives a DSN access request regarding at least one data segment of a data object. The DS processing module determines a DSN address associated with the DSN access request and performs a scoring function using the DSN address and one or more properties of DSN memory to produce a storage scoring resultant. The storage scoring resultant is utilized to identify a set of storage units of the DSN. A set of access requests is then sent to the set of storage units regarding the DSN access request. The scoring function can include, for example, performing deterministic functions, normalizing functions and ranking functions to produce the storage scoring resultant.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jason K. Resch, Greg Dhuse, Manish Motwani, Andrew Baptist, Wesley Leggette, Ravi Khadiwala
  • Patent number: 10216607
    Abstract: Method, computer program product, and system for dynamic tracing, including monitoring a log file, wherein the log file comprises events, wherein an event comprises an event code and an event time stamp, receiving a ranking and rating table (“table”), wherein the table comprises one or more error codes and a ranking for each of the one or more error codes, matching the event code with an error code of the one or more error codes, calculating a rating for the error code, comparing the calculated rating to a rating threshold, enabling an information capture level based on the rating threshold of the calculated rating, in response to enabling the information capture level, copying events from the log file into an abbreviated log file, wherein the copied events include the error code for the calculated rating, creating an alert indicating a changed information capture level, and resetting the dynamic tracing.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Javed Iqbal Abdul, Jose Peter
  • Patent number: 10175977
    Abstract: A computer-implemented method of assisting code review comprises updating a profile to indicate types of errors in a first code base based on a first code version history maintained by a code versioning system for the first code base. The first code version history is a record of changes made to the first code base. The method also includes receiving a second code base developed by a first developer having an association with the profile and displaying the second code base on a display together with assistance data based on the profile. The assistance data indicates focus areas for code review based on the types of errors identified in the profile.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sachin Gupta, Prem S. Jha
  • Patent number: 10153052
    Abstract: An apparatus comprises a memory and a controller. The memory configured to store data. The memory may comprise a write buffer and a plurality of memory dies. Each memory die may have a size less than a total size of the memory and include a plurality of cells. The memory may perform a program operation to write to and verify one or more of the plurality of cells in response to receiving a program command. The controller may be configured to issue the program command to program the plurality of memory dies and to issue the polling status command after issuing the program command to obtain a number of the cells that failed to be verified during the program operation. In response to the polling status command received from the controller, the memory reports a count of a number of bit-lines not having an inhibited state in the write buffer.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 11, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Yu Cai, Yunxiang Wu, Erich F. Haratsch
  • Patent number: 10105189
    Abstract: A method for correcting an error of a nonvolatile memory of an embedded component for an end effector used in a robotic surgical system is provided. The robotic surgical system includes a host controller in communication with the embedded component. The embedded component of the end effector performs a test process to test the nonvolatile memory. The host controller of the robotic surgical system requests a result of the test process from the embedded component of the end effector. The host controller determines that the error of the nonvolatile memory has occurred after requesting the result of the test process from the embedded component of the end effector. The host controller modifies the nonvolatile memory of the embedded component of the end effector to correct the error.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: October 23, 2018
    Assignee: MAKO Surgical Corp.
    Inventors: Stephen Eugene Still, Renbin Zhou
  • Patent number: 10067824
    Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: September 4, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Shao-Wei Yen, Tien-Ching Wang, Yu-Hsiang Lin, Kuo-Hsin Lai, Li-Chun Liang
  • Patent number: 10067032
    Abstract: A method, system, and computer program product are provided for back-up and restoration of data between volatile and flash memory. The method for controlling back-up of data to flash memory includes: organizing back-up data into stripes, wherein a stripe is a set of pages across all available flash memory devices, dies and planes which have the same block and page address; maintaining metadata indicating locations of known bad planes and grown bad planes; using the metadata when writing back-up data to determine which planes to send cache program commands to; and sending cache program commands to three or more stripes of data simultaneously including providing an indication in the stripe that the stripe is handling a cache program command If a grown bad block is encountered whilst saving a stripe of data, the stripe of data is re-written to the next available page address avoiding the grown bad block.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Palmer, Kelvin Wong
  • Patent number: 10067718
    Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 4, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Glennis Eliagh Covington, Kevin M. Brandl, Nienchi Hu, Shannon T. Kesner
  • Patent number: 9997257
    Abstract: A semiconductor device may include a repair address storage circuit, an address comparison circuit, and a word line selection circuit. The repair address storage circuit may store a first repair address and a second repair address. The address comparison circuit may generate a first comparison signal by comparing an input address and the first repair address, and may generate a second comparison signal by comparing the input address and the second repair address. The word line selection circuit may generate a first redundancy word line select signal corresponding to the first comparison signal and a second redundancy word line select signal corresponding to the second comparison signal, based on the first comparison signal and the second comparison signal.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 12, 2018
    Assignee: SK hynix Inc.
    Inventor: Jung Hwan Lee
  • Patent number: 9996304
    Abstract: The present invention provides a data storage device including a flash memory, a plurality of counting control arrays and a controller. The flash memory includes a plurality of chips, each chip has a plurality of pages arranged to be assembled into a super block according to a predetermined order, and each of the super blocks includes the pages of the different chips. The controller keeps the value of a first field of a first counting control array corresponding to a first chip required to be read and writes a second value into the other fields except for the first field of the first counting control array when the first field is a first value, and writes the first value into the first field and keeps the values of the other fields of the first counting control array when the first field is the second value.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: June 12, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Kuan-Lin Chen, Wu-Chi Kuo
  • Patent number: 9922718
    Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units. The memory units may each have a size less than a total size of the memory. The memory units may include a plurality of cells. The controller may be configured to issue a plurality of program operations to write to one or more of the cells. The controller may be configured to implement a polling status command after each of the program operations to verify programming of each of the cells. A response to each of the polling status commands may be used to report a number of the cells that failed to be programmed.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: March 20, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Yu Cai, Yunxiang Wu, Erich F. Haratsch
  • Patent number: 9910728
    Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: March 6, 2018
    Assignee: INTEL CORPORATION
    Inventors: Debaleena Das, Rajat Agarwal, Brian S. Morris
  • Patent number: 9892068
    Abstract: A memory controller (110) interfaces with one or more memory devices (120-n) having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices (120-n), the memory controller (110) automatically discovers the connectivity configuration of the one or more memory devices (120-n), including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller (110) configures the memory devices (120-n) according to the discovered connectivity and assigns unique addresses to jointly selected devices.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: February 13, 2018
    Assignee: Rambus Inc.
    Inventor: John Eric Linstadt
  • Patent number: 9870478
    Abstract: A method for protecting data on a first storage device from unauthorized access is provided. The method includes copying a data map, such as a file allocation table, from the first storage device, on which the data to be protected resides, to a second storage device. A security key is established for the data map. The data map is then deleted from the first storage device, to render unusable the data thereon. The data map is restored to the first storage device upon successful input of the security key.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventor: Masao Takayama
  • Patent number: 9864684
    Abstract: Performing efficient cache invalidation is disclosed, including: receiving an invalidation request to invalidate one or more invalidated cache entries at a cache storage: determining whether an invalidation pattern included in the invalidation request matches an invalidation pattern associated with an existing invalidation entry of an invalidation data structure; in the event that the invalidation pattern included in the invalidation request matches the invalidation pattern associated with the existing invalidation entry of the invalidation data structure, updating the existing invalidation entry with an invalidation timestamp included in the invalidation request, and in the event that the invalidation pattern included in the invalidation request does not match invalidation patterns associated with existing invalidation entries of the invalidation data structure, generating a new invalidation entry in the invalidation data structure with the invalidation pattern and the invalidation timestamp included in the
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: January 9, 2018
    Assignee: Google Inc.
    Inventors: Vijayakumar Murugesan, Vedant Bhangale
  • Patent number: 9754124
    Abstract: A method for protecting data on a first storage device from unauthorized access is provided. The method includes copying a data map, such as a file allocation table, from the first storage device, on which the data to be protected resides, to a second storage device. A security key is established for the data map. The data map is then deleted from the first storage device, to render unusable the data thereon. The data map is restored to the first storage device upon successful input of the security key.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventor: Masao Takayama
  • Patent number: 9727039
    Abstract: A facility management device manages communication data that is transmitted and received between remote controllers and an outdoor unit and/or indoor units. A temporary-memory controller stores communication data that was received by a communicator, and transmission-waveform data that was acquired by a transmission-waveform data acquirer for a specified amount of time in a temporary memory. An abnormality determiner determines whether or not there is abnormality in the communication data that is stored in the temporary memory. When it is determined that there is abnormality in the communication data stored in the temporary memory, a data copier stores all of the data that is stored in the temporary memory in an abnormal-data memory.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: August 8, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeru Kuroiwa, Taichi Ishizaka, Shigeki Suzuki, Takahiro Ito, Noriyuki Komiya
  • Patent number: 9703705
    Abstract: Performing cache invalidation is disclosed, including: receiving an invalidation request to invalidate one or more invalidated cache entries at a cache storage: determining whether an invalidation pattern included in the invalidation request matches an invalidation pattern associated with an existing invalidation entry of an invalidation data structure; in the event that the invalidation pattern included in the invalidation request matches the invalidation pattern associated with the existing invalidation entry of the invalidation data structure, updating the existing invalidation entry with an invalidation timestamp included in the invalidation request, and in the event that the invalidation pattern included in the invalidation request does not match invalidation patterns associated with existing invalidation entries of the invalidation data structure, generating a new invalidation entry in the invalidation data structure with the invalidation pattern and the invalidation timestamp included in the invalidati
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 11, 2017
    Assignee: Google Inc.
    Inventors: Vijayakumar Murugesan, Vedant Bhangale
  • Patent number: 9665572
    Abstract: A method for providing optimized data representation of relations for in-memory database query processing is disclosed. The method seeks to optimize the use of the available memory by encoding relations on which the in-memory database query processing is performed and by employing auxiliary structures to maintain performance. Relations are encoded based on data patterns in one or more attribute-columns of the relation and the encoding that is selected is suited to a particular type of data in the column. Members of a set of auxiliary structures are selected based on the benefit the structure can provide and the cost of the structure in terms of the amount of memory used. Encoding of the relations is performed in real-time while query processing occurs, using locks to eliminate conflicts between the query processing and encoding.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 30, 2017
    Assignee: Oracle International Corporation
    Inventors: Sam Idicula, Kevin Moore, Brian Gold, Nipun Agarwal, Eric Sedlar
  • Patent number: 9582191
    Abstract: Methods of operating electronic systems having a memory include reading indications of memory block quality from a plurality of memory blocks of the memory in which a memory defect has been detected, wherein a value of the indication of memory block quality stored in a respective memory block of the plurality of memory blocks indicates a type of memory defect detected in the respective memory block, and, in response to the values of the indications of memory block quality, deeming a first portion of memory blocks of the plurality of memory blocks as usable, allocating a second portion of memory blocks of the plurality of memory blocks for storing only data of a particular type, and indicating a third portion of memory blocks of the plurality of memory blocks as defective.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: February 28, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 9489306
    Abstract: Performing cache invalidation is disclosed, including: receiving an invalidation request to invalidate one or more invalidated cache entries of a cache storage, wherein the cache storage is configured to store cache entries; storing the invalidation request to invalidate the one or more invalidated cache entries in an invalidation data structure; prior to removing the one or more invalidated cache entries from the cache storage, receiving a data retrieval request for a requested cache entry from the cache storage; and using the invalidation data structure to determine whether the requested cache entry has been invalidated.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: November 8, 2016
    Assignee: Apigee Corporation
    Inventors: Vijayakumar Murugesan, Vedant Bhangale
  • Patent number: 9483339
    Abstract: Changes in the distribution of memory cells across memory states allow calculation of Bit Error Rate (BER). Comparison of test data stored in memory and a known good copy of the test data provides test data BER from which user data BER may be obtained. Data may be handled differently according to its BER.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 1, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Ariel Navon, Eran Sharon
  • Patent number: 9384124
    Abstract: According to one embodiment, a data storage device includes a first controller, a second controller, and a third controller. The first controller performs a control operation of writing data of a first data unit to a storage area in a flash memory and reading the data of the first data unit from the storage area. The second controller carries out migration processing of measuring a data amount of valid data stored in storage areas of a second data unit that is a data erase processing unit.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taichiro Yamanaka, Yoko Masuo, Hironobu Miyamoto
  • Patent number: 9336075
    Abstract: There is provided a monitoring apparatus (1) including: an acquisition unit (10) that acquires failure information indicating that a failure has occurred in any of a plurality of monitoring targets; a notification job determination unit (20) that determines whether or not a predetermined user has to be notified of the failure which is specified by the failure information; and a display unit (40) that displays failure notification information indicating occurrence of the failure when the acquisition unit (10) acquires the failure information, and displays notification job information indicating that there is a job to notify the failure to a predetermined user when the notification job determination unit (20) determines that notification has to be issued.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: May 10, 2016
    Assignee: NEC Corporation
    Inventor: Teruya Ikegami
  • Patent number: 9305663
    Abstract: Examples are disclosed for assessing pass/fail status of non-volatile memory. In some examples, information may be received to indicate a block having memory pages associated with non-volatile memory cells. The information may indicate at least some of the memory pages have bit errors in excess of an error correction code (ECC) ability to correct. For these examples, the block may be selected for read testing. Read testing may include programming the memory pages with a known pattern and waiting a period of time. Following the period of time each memory page may be read and if a resulting pattern read matches the known pattern programmed to each memory page, the memory page passes. The block may be taken offline if the number of passing memory pages is below a pass threshold number. Other examples are described and claimed.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 5, 2016
    Assignee: NetApp, Inc.
    Inventors: Joshua Silberman, George Totolos, Richard Strong
  • Patent number: 9230687
    Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: January 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
  • Patent number: 9170302
    Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: October 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Ki Up Kim
  • Patent number: 9165684
    Abstract: A fault bits scrambling memory and method thereof relate to a memory including at least one memory bank. The memory bank includes a memory module, a scrambling-logic unit, a self-testing unit and a scrambling code generating unit. The memory module includes a plurality of pages. Each page has a plurality of memory cells, and each memory cell has a physical address. The scrambling logic unit receives a scrambling code and the physical address to generate a mapping address by logical calculation, and outputs the mapping address to the memory module. The self-testing unit detects the faulty memory cells of each page. The scrambling code generating unit is applied to generate the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 20, 2015
    Assignee: National Taiwan University of Science and Technology
    Inventors: Shyue-Kung Lu, Hao-Cheng Jheng