Abstract: A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.

Abstract: A memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. The memory system accesses blocks of data, each block including an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row-parity bits for each of the R rows, (2) an inner-checkbit column containing X=R?S inner checkbits and S spare bits, and (3) C-2 data-bit columns containing data bits. Each column is stored in a different memory component. When the memory system determines that a memory component has failed, the memory system examines the pattern of errors associated with the failed component to determine if the failure affects a partial component associated with S or fewer bits. If so, the memory system corrects and remaps data bits from the failed partial component to the S spare data bits in the inner-checkbit column.

Abstract: Various embodiments comprise a method, the method comprising determining whether each of a plurality of memory blocks in a memory device is defective, wherein the plurality of memory blocks are organized into memory block groups, and one of the memory block groups comprises a base memory block group; forming a grouping of non-defective memory blocks; forming a remapped grouping of memory blocks that includes a non-defective memory block from the base memory block group and at least one non-defective memory block in another memory block group that includes a defective memory block; and storing a mapping of the remapped grouping in at least one of the memory device and a processor coupled to the memory device.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a media defect detector circuit. The media defect detector circuit is operable to compare a data input derived from a medium against at least a first defect level to yield a first level output, and a second defect level to yield a second level output; and provide a combination of the first level output and the second level output as a defect quality output. A value of the defect quality output corresponds to a likelihood of a defect of the medium.

Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.

Abstract: A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is transmitted to a memory device over an address bus coincident with transmitting a no-operation instruction over a command bus.

Abstract: A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.

Abstract: A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.

Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.

Abstract: A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.

Abstract: A method of operating a disk drive comprises scanning each Logical Block Address (LBA) of the disk drive to detect a read error or reading the LBA from a media defect list. The LBA may then be converted to a corresponding physical location on the media and a scan of the corresponding physical location and of nearby physical locations that are within a proximity threshold of the corresponding physical locations may be performed to find media defects. Based thereon, it may then be determined whether a media scratch is present and at least one or more data sectors associated with the media scratch may be relocated to a spare location on the media if the media scratch is determined to be present. If the media scratch is determined not to be present, only the data sector associated with the corresponding physical location may be relocated to the spare location.

Abstract: An error correction apparatus, a method thereof, and a memory device including the apparatus are provided. The error correction apparatus may include: a determination unit configured to determine whether a number of errors in a read word being read and extracted from a multi-level cell (MLC) exists in an error correcting capability range; a read voltage control unit configured to either increase or decrease a read voltage applied to the MLC when the number of errors in the read word is outside the error correcting capability range; and a codeword determination unit configured to analyze a bit error based on the increase or decrease of the read voltage, and to select a codeword corresponding to the analyzed bit error based on a selected read error pattern. Through this, it may be possible to efficiently correct a read error that occurs when the data of the memory device is maintained for a long time.

Abstract: A method for testing electronic devices that are correspondingly connected to test units includes generating control signals for the electronic devices that are connected to one or more test units selected from the test units. A control unit adds ID codes corresponding to the selected test units to the control signals, and wirelessly transmits the control signals with the ID codes to all of the test units. Each of the test units compares the ID codes added to the control signals with its own stored ID code. When the ID code added to a control signal is in accordance with the ID code stored in one of the test units, the test unit controls the electronic device connected thereto to be turned on and off according to the control signal.

Abstract: A first module calculates a failure occurrence risk index of each data storage area address. A second module calculates a power saving index of each data storage area address. A third module calculates an access speed index per unit data volume necessary to access each data storage area address. A fourth module generates a distribution table that represents the failure occurrence risk index, the power saving index, and the access speed index for each candidate address, with respect to data to be distributed. A fifth module selects a candidate address in the distribution table such that the power saving index and the access speed index meet restricting conditions and the failure occurrence risk index is minimized, and distributes the data to the candidate address.

Abstract: In a memory testing method for testing a memory module of a computing device, an operating voltage of the memory module is adjusted to a first voltage or a second voltage. A predetermined data set is written into the memory module after the operating voltage of the memory module is adjusted, and the written data set is read out from the memory module, to accomplish a data writing and reading process of the memory module. A register value that presents how many memory errors have occurred during the data writing and reading process is acquired from an ECC register of the memory module, to determine whether the memory module is stable during the adjusting of the operating voltage according to the register value.

Abstract: A semiconductor device includes a first management area storing a plurality of inspection results, the plurality of inspection results being obtained by executing inspections for each of a plurality of storage areas which store a plurality of data; and a second management area storing the plurality of inspection results. The first and second management areas are independent from each other.

Abstract: A data protection method for damaged memory cells is provided. A power-on self-test (POST) is executed, and an initial backup memory is reserved in a memory. An operating system (OS) is executed, and data is loaded from a kernel region of the OS in the memory into a mirror region, so that when a processor accesses the data in the kernel region, it also accesses the data in the mirror region. An uncorrectable error (UE) is detected to determine a damaged page, and a backup page is selected from the initial backup memory or dynamically obtained from the OS to back up data in the damaged page. A mapping address of the damaged page and backup page are recorded into a page mapping table in a memory controller. Accordingly, when the OS accesses the damaged page, the memory controller accesses the backup page instead according to the page mapping table.

Abstract: A method of recording a temporary defect list on a write-once recording medium, a method of reproducing the temporary defect list, an apparatus for recording and/or reproducing the temporary defect list, and the write-once recording medium. The method of recording a temporary defect list for defect management on a write-once recording medium includes recording the temporary defect list, which is created while data is recorded on the write-once recording medium, in at least one cluster of the write-once recording medium, and verifying if a defect is generated in the at least one cluster. Then, the method includes re-recording data originally recorded in a defective cluster in another cluster, and recording pointer information, which indicates a location of the at least one cluster where the temporary defect list is recorded, on the write-once recording medium.

Abstract: A computer system having a plurality of devices including a data storage part which includes a plurality of cells to store data, and a controller to inspect whether there is a defective cell in the data storage part if a condition to execute a cell inspection function is met, and sets the defective cell to be assigned to one of the devices if a defective cell is found.

Abstract: A bad block identification method for a memory is provided. The memory includes at least one memory block for storing data. A data decoding function is performed on the data, and it is determined whether the data decoding function was performed successfully. If the data decoding function was not performed successfully, at least one predetermined location in the memory block is checked. It is determined whether the predetermined location is marked by predetermined information. If the predetermined location is not marked by the predetermined information, the memory block is identified as a bad block.

Abstract: Embodiments described herein are directed to a virtual repair of digital media using a virtual repair service. Digital media stored on a digital media device is read using a media player. A request is received by a virtual repair unit from the media player to perform a virtual repair of a segment of unreadable digital content of the digital media. The virtual repair unit retrieves a readable copy of the digital content corresponding to the segment of unreadable digital content identified in the request from a media repository using the virtual repair unit. The virtual repair unit transmits the readable copy of the digital content to the media player for insertion into a buffer of the media player.

Abstract: A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.

Abstract: A computer system comprises a memory configured to store software instructions; a set of registers; and a processing unit configured to temporarily store passed parameters in the set of registers during execution of the software instructions, the processing unit is further configured to skip save and restore operations when executing a logging function to log the passed parameters.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can decode error correction codes (ECC).

Abstract: Described are embodiments of an invention for blocking write access to memory modules of a solid state drive. The solid state drive includes a controller access module or a memory access module that controls write access to the solid state drive and the memory modules of the solid state drive. Upon determining that a memory module has failed, the failed memory module or the entire solid state memory device is configured to be read only to prevent an errant write of data over critical data. Further, a failed memory module, or solid state device memory having a failed memory module, may be replaced upon failure.

Abstract: An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle.

Abstract: A system including a first plurality of memory cells to store data, and a memory controller to read the first plurality of memory cells and to identify one or more of the first plurality of memory cells in response to the one or more of the first plurality of memory cells being defective. A second plurality of memory cells stores information regarding locations of the one or more of the first plurality of memory cells. The second plurality of memory cells stores the information at a lower density than the first plurality of memory cells. The information read from the second plurality of memory cells has a lower probability of error than the data read from the first plurality of memory cells.

Abstract: At least one standard size data block of a storage device is scanned for a logically bad pattern. If the logically pad pattern is detected, a block address that is associated with the standard size data block is added to a bad block table. If the logically pad pattern is not detected, it may be determined if the block address associated with the standard size data block is in the bad block table. If the logically pad pattern is not detected and if the block address associated with the standard size data block is in the bad block table, the block address may be removed from the bad block table. The logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.

Abstract: A method for consolidating data logged in log files in a network of servers, each server running at least one application that logs data into files on the server, the method comprising: providing a consolidating message queue for receiving the log data and file name; intercepting log data being written into a log file by a file system and sending that log data and the file name of the log file to a consolidating message queue; receiving the log data and file name in a consolidating message queue; and saving the log data in the consolidating message queue from all the servers to a consolidated file or data structure associated with the file name.

Abstract: According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.

Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Abstract: An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state storage element as bad blocks. A log update module writes at least a location of each bad block identified by the bad block identifier module into each of two or more redundant bad block logs. A bad block mapping module accesses at least one bad block log during a start-up operation to create in memory a bad block map. The bad block map includes a mapping between the bad block locations in the bad block log and a corresponding location of a replacement block for each bad block location. Data is stored in each replacement block instead of the corresponding bad block. The bad block mapping module creates the bad block map using one of a replacement block location and a bad block mapping algorithm.

Abstract: Mechanisms are provided in which firmware verifies he entire system's memory scrub coverage through some additional memory controller (MC) registers/attentions and builds up a processor runtime diagnostic (PRD) scrub coverage table during every scrub cycle. Firmware may go through the scrub coverage table rank-by-rank on a periodic basis to determine whether any ranks had not been covered by hardware scrubbing. Firmware may initiate a targeted scrub and diagnostic for all of the ranks that did not have adequate scrub coverage. If for some reason the system still has some memory ranks that have not been covered by the initial hardware scrub and the targeted scrub, then the firmware may perform some course of action for fault isolation.

Abstract: A method of testing a flash memory is applied to retrieve the flash memory available by picking up a defective flash memory. The flash memory includes at least a block, a page, and a cell. The method comprises inputting a test command into the flash memory to execute at least one of write, read, or compare of the flash memory. After the test command is executed, the states of the block, page, and cell in the flash memory may be obtained. The states are marked in a flash memory distribution list to allow a controller to access at least one of the normal block, page, and cell from the list. Thus, in the method, the normal block, page, and cell may be obtained.

Abstract: A memory cartridge is described that includes a non-volatile memory. The cartridge also includes logic to concentrate memory operations on particular areas of the non-volatile memory to cause the areas of concentration to wear out at an accelerated rate relative to non areas of concentration, and logic to track wear on the non-volatile memory resulting from one or both of erases and writes.

Abstract: Program disturb error logging and correction for a flash memory including a computer implemented method for storing data. The method includes receiving a write request that includes data and a write address of a target page in a memory. A previously programmed page at a specified offset from the target page is read from the memory. Contents of the previously programmed page are compared to an expected value of the previously programmed page. Error data is stored in an error log in response to contents of the previously programmed page being different than the expected value of the previously programmed page, the error data describing an error in the previously programmed page and the error data used by a next read operation to the previously programmed page to correct the error in the previously programmed page. The received data is written to the target page in the memory.

Abstract: According to one embodiment, a failure analyzing device includes a classifying unit that classifies a failure type in a fail bit map corresponding to each layer, a storage unit that stores a rule to combine failed cells of different layers, and a determining unit that groups a classification result matched with the rule among classification results based on the classifying unit. The rule includes a base point failure, an association failure becoming a combination object of the base point failure, a combination condition defining a relationship between the base point failure and the association failure, and a combination failure name. The determining unit extracts the base point failure from the classification result of one layer, extracts the association failure matched with the combination condition from the classification results of the other layers, groups the extracted base point failure and association failure, and provides the combination failure name.

Abstract: An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.

Abstract: A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.

Abstract: A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.

Abstract: An interleaving method (2) and an interleaver (9) for frequency interleaving data symbols. The data symbols are for allocation to carriers in a set of NFFT carriers of a module for multiplexing and modulation by orthogonal functions in a multicarrier transmitter device (3). A block of Npm successive data symbols is interleaved in application of an interleaving law that varies over time for a given transmission mode of the transmitter device, where Npm is less than or equal to NFFT.

Abstract: A solid-state mass storage device and method of anticipating a failure of the mass storage device resulting from a memory device of the mass storage device reaching a write endurance limit. A procedure is then initiated to back up data to a second mass storage device prior to failure. The method includes assigning at least a first memory block of the memory device as a wear indicator, using other memory blocks of the memory device as data blocks for data storage, performing program/erase (P/E) cycles and wear leveling on the data blocks, subjecting the wear indicator to more P/E cycles than the data blocks, performing integrity checks and monitoring the bit error rate of the wear indicator, and taking corrective action if the bit error rate increases, including the initiation of the backup procedure and generating a request to replace the device.

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract: Methods of memory management are described which can accommodate non-maskable failures in pages of physical memory. In an embodiment, when an impending non-maskable failure in a page of memory is identified, a pristine page of physical memory is used to replace the page containing the impending failure and memory mappings are updated to remap virtual pages from the failed page to the pristine page. When a new page of virtual memory is then allocated by a process, the failed page may be reused if the process identifies that it can accommodate failures and the process is provided with location information for impending failures. In another embodiment, a process may expose information on failure-tolerant regions of virtual address space such that a physical page of memory containing failures only in failure-tolerant regions may be used to store the data instead of using a pristine page.

Abstract: A real time clock for outputting data indicating a time of day includes: an event detection circuit for detecting that an event detection signal has been inputted from outside; a timing circuit for generating the time-of-day data according to a signal outputted from an oscillator circuit; a memory; and a control circuit for, if the event detection circuit detects input of the event detection signal, recording event data in the memory, the event data including additional data indicating an operating state of the real time clock and the time-of-day data generated by the timing circuit.

Abstract: Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.

Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.

Abstract: Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.

Abstract: A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.