Abstract: A data storage system configured to perform prioritized memory scanning for memory errors is disclosed. In one embodiment, the data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data. Improved performance of the data storage system is thereby attained.

Abstract: A memory repair mechanism for the memories clustered across the multiple power domains and can be switched on and off independent of each other, thereby enabling low power operation. Enhancements in the shared Fuse Wrapper Architecture enable sharing of a plurality of parallel links connecting the memory blocks of each power domains to the Shared Fuse Wrapper architecture.

Abstract: A memory module including a first memory, a second memory, a test module, and a control module. The first memory is configured to store pages of data to be tested for errors. The second memory is configured to store addresses for the pages of data and store copies of the pages of data. The test module is configured to perform testing on the pages of data stored in the first memory. The control module is configured to, prior to the testing being performed by the test module on the pages of data stored in the first memory, cause the second memory to store the addresses and the copies of the pages of data stored in the first memory and, subsequent to the testing being performed by the test module, store the copies of the pages of data to the first memory based on the addresses stored in the second memory.

Abstract: An integrated circuit includes memory units and at least one memory test module, each module includes one associated memory unit, a set of test registers therefor, and a test engine configured to perform a test operation on that associated memory unit. A transaction interface of the memory test module receives a transaction specifying a register access operation and providing a first address portion having encodings allowing individual memory units as well as groups of memory units to be identified, and a second address portion identifying one of the test registers within the set to be an accessed register. Decode circuitry, within each memory test module and responsive to the transaction, is configured to selectively perform the register access operation if it is determined that the memory test module includes a set of test registers associated with a memory unit.

Abstract: Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be substituted for the failed cell. If two error correcting pointers in the array point to the same cell, a precedence rule dictates the array entry with the higher index (the entry created later) takes precedence. To count the number of error correcting pointers in use, a null pointer address can be employed to indicate that a pointer is inactive, an activation bit can be added, and/or a counter, that represents the number of error correcting pointers that are active. Mechanisms are provided for wear-leveling within the error correction structure, or for pairing this scheme with single-error correcting bits for instances where transient failures may occur. The architecture also employs pointers to correct errors in volatile and non-volatile memories.

Abstract: A data processor having a plurality of data processing cores configured to disable cores found defective by a self-test.

Abstract: A nonvolatile memory device includes a first storage unit configured to store a plurality of first fault address information provided in a first test operation, a second storage unit configured to store a plurality of second fault address information provided in a second test operation which is performed later than the first test operation; a redundancy operation unit configured to, in performing a redundancy operation, determine the number of operation circuits corresponding to the first fault address information and the number of operation circuits corresponding to the second fault address information among a plurality of redundancy operation circuits based on address number information; and an address providing unit configured to read the plurality of first fault address information and the plurality of second fault address information, and sequentially provide the read information to the redundancy operation unit, wherein the address providing unit is further configured to detect the number of the first f

Abstract: A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold pro-gramming values for the generic programmable address scrambler.

Abstract: A testing method is described for performing a fast bit-error rate (BER) measurement on resistance-based RAM cells, such MTJ cells, at the wafer or chip level. Embodiments use one or more specially designed test memory cells fabricated with direct electrical connections between the two electrodes of the cell and external contact pads (or points) on the surface of the wafer (or chip). In the test setup the memory cell is connected an impedance mismatched transmission line through a probe for un-buffered, fast switching of the cell between the high and low resistance states without the need for CMOS logic to select and drive the cell. The unbalanced transmission line is used generate signal reflections from the cell that are a function of the resistance state. The reflected signal is used to detect whether the test cell has switched as expected.

Abstract: Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.

Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.

Abstract: On demand tracing of application code execution includes: during the execution of the application code, writing trace statements to a circular trace buffer (at a selected and potentially variable detail level); determining whether a pre-defined trigger event has occurred; in response to determining that the trigger event has occurred, outputting one or more trace statements in the circular trace buffer according to pre-defined trace parameters; determining whether a trigger end event has occurred; and in response to determining that the trigger end event has occurred, terminating the outputting of the trace statements. The trigger event and the trigger end event may be defined by names of application code variables, values for the variables, and operators to be used. The trigger end event may further be defined by a time duration for which trace statements are to be outputted, or a number of trace statements to be outputted.

Abstract: An arithmetic processing apparatus includes a cache memory to store data in cache lines, an error detecting unit to detect an error occurring in one of the cache lines, a way comparing unit to compare way identification information of a cache line to be accessed with error-way identification information, a word comparing unit to compare a word address of the cache line to be accessed with an error word address, a column comparing unit to compare a column address of the cache line to be accessed with an error column address, and a control unit to disable all cache lines sharing a failed word line in response to results of comparisons made by the way comparing unit, the word comparing unit, and the column comparing unit when the error detecting unit detects a second error occurring in any one of the cache lines after the occurrence of the first error.

Abstract: A method for correcting faults in semiconductor memory components provides an application system having a multichip module (1) which has a semiconductor memory component (2) containing a volatile memory and a diverting circuit (7). When the application system is being booted up, addresses of faulty memory cells in the semiconductor memory component (2) are loaded into the multichip module (1), with the result that the diverting circuit (7) diverts access to a memory cell in the replacement data memory if a faulty memory cell in the semiconductor memory component (2) is accessed.

Abstract: Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.

Abstract: A method of controlling a nonvolatile semiconductor memory includes checking, at a first interval period, an error count of data stored in a first group, the first group including a plurality of blocks/units, and when a first block/unit in the first group satisfies a first condition, assigning the first block/unit to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, the second interval period being shorter than the first interval period, and when a second block/unit in the second group satisfies a second condition, moving data stored in the second block/unit to an erased block/unit in which stored data is erased among the plurality of blocks/units.

Abstract: A method of enhancing an error correction performance in a data storage system, and a storage device using the method, determines a deterioration status of a physical area of a memory device to which data is to be stored and compresses data and stores the compressed data and an error correction code (ECC) with respect to the compressed data in an area of which the deterioration status is equal to or greater than a threshold value that is initially set and stores uncompressed data and an ECC with respect to the uncompressed data in an area of which the deterioration status is less than the threshold value.

Abstract: The claimed subject matter relates to architectures and/or mechanisms that can facilitate issuing, embedding and verification of an optical DNA (o-DNA) signature. A first mechanism is provided for obtaining a set of manufacturing errors inherent in an optical media instance. These errors can be encoded into the o-DNA that can be cryptographically signed with a private key, then embedded into the source optical media instance. A second mechanism is provided that can decrypt the o-DNA with a public key and compare the authenticated errors to the observed errors to ascertain whether the optical media instance is authentic as opposed to a forgery or counterfeit.

Abstract: A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

Abstract: A system includes a first device, a first storage element, a comparator and a second device. The first device is configured to test memory cells in an array of memory cells to detect defective memory cells. The defective memory cells include a first memory cell and a second memory cell. The first storage element is configured to store a first address of the first memory cell. The comparator is configured to compare a second address of the second memory cell to the first address.

Abstract: Disclosed are a flash memory device and flash memory programming method that equalizes a wear-level. The flash memory device includes a memory cell array, an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘1’s and ‘0’s in the data page, a programming unit to store the generated programming page in the memory cell array; and a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page, and thereby can equalize a wear-level of a memory cell.

Abstract: Provided is a test module that tests a device under test, comprising a pattern generating section that generates a test pattern supplied to the device under test and an expected value pattern corresponding to the test pattern, based on a pattern program; an output pattern acquiring section that acquires an output pattern output by the device under test in response to the test pattern; a comparing section that compares the output pattern output and the expected value pattern; a fail counter that counts the number of times the comparing section indicates a mismatch between the output pattern and the expected value pattern; and a control section that controls operation of the fail counter according to control instructions in the pattern program.

Abstract: A component identification system and method, including an identifier associated with a replacement component, a memory to store one or more identifiers for each previously used component corresponding to the replacement component, and a processor to compare the identifier of the replacement component with the one or more stored identifiers of each previously used component. The replacement component is acceptable where the identifier of the replacement component differs from the one or more stored identifiers of each previously used component, and the replacement component is unacceptable where the identifier of the replacement component corresponds to one or more stored identifiers of each previously used component. Prior to accepting the replacement component, one or more predetermined validation operations can be performed on the identifier of the replacement component, with the identifier being formed in a serial number or code type scheme.

Abstract: A memory system comprising a first memory, a control module, a test module, and a second memory. The first memory is configured to store pages of data to be tested. The control module is configured to store identifiers of the pages of data. The test module is configured to test the pages of data in the first memory. The second memory is configured to, while the pages of data stored in the first memory are being tested, store the identifiers of the pages of data and store the pages of data. The control module is further configured to, after the test module completes testing of the pages of data in the first memory, move the pages of data from the second memory to the first memory based on the identifiers of the pages of data.

Abstract: A system including a memory controller configured to identify a first memory cell of a first plurality of memory cells as defective and to store information about the first memory cell in a second memory cell of a second plurality of memory cells. The second plurality of memory cells is configured to store data at a lower density than the first plurality of memory cells. In response to (i) reading data from the first plurality of memory cells and (ii) the first memory cell of the first plurality of memory cells having been identified as defective, the memory controller is configured to read the information about the first memory cell stored in the second memory cell and to determine a location of the first memory cell in the first plurality of memory cells.

Abstract: In a system including a processor and memory coupled to the processor, a method of device failure analysis includes the steps of: upon each error detected within a test series performed on a device, the processor storing within a table in the memory an address at which the error occurred in the device and storing a bit position of each failed bit corresponding to that address; for each unique address at which at least one error occurred, determining how many different bit positions corresponding to the address failed during the test series; and based on results of the test series, determining whether the device failed the test series.

Abstract: A block management method for managing physical blocks of a rewritable non-volatile memory module, and a memory controller and a memory storage device using the same are provided. The method includes maintaining an error information table for recording one or more error correctable physical blocks among the physical blocks and an error bit number corresponding to the one or more error correctable physical blocks. The method further includes selecting a physical block for writing data according to the one or more error correctable physical blocks and the error bit number thereof recorded in the error information table. Accordingly, the data stability of the memory storage device can be improved.

Abstract: Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data.

Abstract: An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.

Abstract: A control apparatus controlling testing of a memory under test that includes one or more row repair memory blocks and column repair memory blocks. The control apparatus comprises a counting section that sequentially receives test results respectively indicating pass/fail of a plurality of test blocks of the memory under test, and sequentially counts, for each first-type memory block, which is a row-oriented memory block or a column-oriented memory block, a fail memory block number among second-type memory blocks; a selecting section that selects memory blocks first-type memory blocks for which the fail memory block number exceeds a reference value, such that the number of selected memory blocks is no greater than the number of first-type repair memory blocks of the memory under test; and a test control section that masks test blocks among the memory blocks selected by the selecting section and causes further testing of the memory under test.

Abstract: Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.

Abstract: Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.

Abstract: A method to enable defect margining of a disk drive may comprise executing a data access command on a target sector on the disk drive. Upon encountering a data access error at the target sector, an address of the target sector may be added to an error list. The address of the target sector in the error list may then be converted to a physical location on the disk drive. A thermal asperity scan may be performed at and around the physical location and, upon detecting a thermal asperity, and at least sectors around the detected thermal asperity may be margined, and the data stored within the margined sectors may be relocated. Instead of sectors, entire tracks may be margined and the data stored therein relocated to a spare or reserve location, one track at a time.

Abstract: A semiconductor memory apparatus having stacked first and second chips includes a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode, a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode, and a final data determination unit configured to generate a final test signal in response to the first and second chip test signals in the test mode.

Abstract: A method for repairing an integrated circuit comprises: fabricating a first circuit, the first circuit including a plurality of regular units and a plurality of redundant units, each of the regular units being identified by an address; performing a first test on the first circuit to determine if a defective regular unit is present; activating, if the defective regular unit is present, at least a first redundant unit to replace the defective regular unit, the first redundant unit being identified by an address of the defective regular unit; performing, if the at least first redundant unit is present, a second test on the first circuit to determine if the first redundant unit is defective; and activating at least a second redundant unit to replace the defective first redundant unit, the second redundant unit being identified by the address of the defective regular unit.

Abstract: A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

Abstract: A test apparatus including a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.

Abstract: A data writing method for a re-writable non-volatile memory module and a memory controller and a memory storage apparatus using the same are provided, wherein the re-writable non-volatile memory module has a plurality of physical writing units, and each of the physical writing units has a plurality of physical writing segments. The data writing method includes identifying at least one non-used segment among the physical writing segments of each of the physical writing units and writing a plurality of segment data streams into the physical writing units, wherein the non-used segments of the physical writing units are not used for writing the segment data. Accordingly, the data writing method can effectively use normal physical writing segments in the physical writing units.

Abstract: A method for dodging bad page and bad block caused by suddenly power off is disclosed. This method is to avoid a new data from host program to potential hurt block or page caused by power off during NAND flash erasing or programming.

Abstract: A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.

Abstract: A method and apparatus for accelerating a load point scanning process. In one embodiment, the method and apparatus comprise creating, at an initial scan, a detection area map identifying files referenced by detection areas. Upon a subsequent scan, determining whether the detection area has changed with respect to the detection area map. If the detection area map has changed, re-evaluating the detection area and repopulating the detection area map entry. In another embodiment, the method and apparatus avoid rescanning files as allowed using information in a file attribute cache.

Abstract: A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.

Abstract: A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix can also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which charge-disturb errors are provoked by executing a selected operation until a detectable error occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.

Abstract: Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. The NVM may be managed based on results of a test performed on the NVM. The test may indicate, for example, physical memory locations that may be susceptible to errors, such as certain pages in the blocks of the NVM. Tests on multiple NVMs of the same type may be compiled to create a profile of error tendencies for that type of NVM. In some embodiments, data may be stored in the NVM based on individual test results for the NVM or based on a profile of the NVM type. For example, memory locations susceptible to error may be retired or data stored in those memory locations may be protected by a stronger error correcting code.

Abstract: Systems and methods are disclosed for performing run-time tests on a non-volatile memory (“NVM”), such as flash memory. The run-time tests may be tests that are performed on the NVM while the NVM can be operated by an end user (as opposed to during a manufacturing phase). In some embodiments, a controller for the NVM may detect an error event that may be indicative of a systemic failure of a die of the NVM. The controller may then select one or more blocks in the die to test, which may be dies that are currently not being used to store user data. The controller may post process the results of the test to determine whether there is a systemic failure, such as a column failure, and may treat the systemic failure if there is one.

Abstract: Provided is a method for the collection and storage of information related to the operation of a chip module. The disclosed technology provides a chip data collection and storage controller. In one embodiment, a chip module is provided with a stand-alone memory that records information relevant to potential debugging operations. The stand-alone memory is on the same chip module as the chip die but is not part of the chip die. A data bus is provided between the chip module and the memory. In addition, the memory has I/O access so that information can be accessed in the event that the chip module cannot be accessed. Stored information includes, but is not limited to, environmental conditions, performance information, errors, time usage, run time, number of power on cycles, the highest temperature experience by the chip, wafer and x, y data, manufacturing info, FIR errors, and PRSO, SRAM PSRO values.

Abstract: Techniques involving failure management of storage devices are described. One representative technique includes encoding data to enable it to be stored in a storage block that includes at least one storage failure. The data is encoded such that it traverses the storage failures when stored in the storage block. When it is determined that a storage access request has requested the data stored in a storage block having such failures, the data is decoded to restore it to its original form.

Abstract: Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

Abstract: A storing apparatus, equipped with a control unit configured to control the writing of data into a memory and to communicate a notice to an external device with a communication unit if the remaining amount of substitute blocks becomes equal to or less than a threshold value specified by stored threshold value information, includes the control unit configured to change the threshold value information, used for the notice communicated by the control unit, by the use of threshold value information received from the external device with the communication unit.

Abstract: An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory unit includes a plurality of memory banks, which are capable of being independently controlled so that data can be written or read in/from the memory banks, each having memory cells arranged in an N×M matrix structure. The memory write/read control unit generates control signals to write/read data in/from the memory unit. The memory access address generation unit generates a memory access address used to write/read data in/from the memory unit in response to the memory write/read control signals. The second permutation and output selection unit rearranges the positions of data bits output from the memory unit and outputs the position-rearranged data bits.