Boundary Scan Patents (Class 714/727)
  • Patent number: 11222884
    Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Po-Hsiang Huang, Ka Fai Chang
  • Patent number: 11209483
    Abstract: Boundary scan test data and a command to initiate a boundary scan test are received via a universal asynchronous receiver-transmitter (UART). Based on receiving the command, a boundary scan test mode is initiated at a memory sub-system controller. A boundary scan test vector based on the boundary scan test data is synchronously streamed to a boundary scan chain. Test result data output by the scan chain is provided to a UART host via the UART.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michael Richard Spica
  • Patent number: 11204385
    Abstract: One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gautam Sanjay Kale, Nagalinga Swamy B. Aremallapur, Sundarrajan Rangachari
  • Patent number: 11199582
    Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO of the JTAG controller.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: December 14, 2021
    Assignee: XILINX, INC.
    Inventors: Roger D. Flateau, Jr., Srinu Sunkara
  • Patent number: 11156662
    Abstract: A software-defined linear feedback shift register (SLFSR) implements a low-power test compression for launch-on-capture (LOC). Each bit of an extra register controls a stage of the SLFSR. A control vector is shifted into the extra register to indicate whether a primitive polynomial contains the stage of the non-zero bit. Therefore, SLFSR can configure any primitive polynomials with different degrees by loading different control vectors without any hardware overhead. A low-power test compression method and design for testability (DFT) architecture provide LOC transition fault testing by using seed encoding scheme, low-power test application procedure and a software-defined linear-feedback shift-register (SLFSR) architecture. The seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 26, 2021
    Inventor: Dong Xiang
  • Patent number: 11153152
    Abstract: Systems, methods and computer-readable storage media are provided for detecting and simulating issues in a network.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 19, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Waseem A Siddiqi, Rajesh S. Pazhyannur, Kedar Krishnanand Gaonkar, Aruna Nukala
  • Patent number: 11138083
    Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Patrik Eder, Rolf H. Kuehnis, Enrico D. Carrieri
  • Patent number: 11137447
    Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11120187
    Abstract: According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including: a first scan chain and a second scan chain; a clock generator; and a test control circuit. The first scan chain includes: a first flip-flop having a first scan data input terminal and a first output terminal; and a first multiplexer. The first multiplexer is configured to electrically couple the first scan data input terminal to the first output terminal based on a first signal received from the test control circuit to form a first closed loop. The second scan chain includes a second flip-flop having a second scan data input terminal and a third output terminal that is not coupled to the second scan data input terminal.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: September 14, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tetsu Hasegawa
  • Patent number: 11113184
    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: September 7, 2021
    Assignee: Breker Verification Systems
    Inventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
  • Patent number: 11073555
    Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 27, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Yen Chen, Jeong-Fa Sheu, Chia-Jui Yang, Po-Lin Chen
  • Patent number: 11061073
    Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 13, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Yen Chen, Jeong-Fa Sheu, Chia-Jui Yang, Po-Lin Chen
  • Patent number: 11054470
    Abstract: A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Amit Agarwal, Steven Hsu, Anupama Ambardar Thaploo, Simeon Realov, Ram Krishnamurthy
  • Patent number: 11057027
    Abstract: The present invention provides a circuit having a plurality of modes, wherein the circuit includes a first circuit, a second circuit, a first multiplexer, a second multiplexer and a specific flip-flop. In the operations of the circuit, the first circuit is configured to generate a first signal, the second circuit is configured to generate a second signal, the first multiplexer is configured to output one of the first signal and the second signal according to a mode selection signal, the second multiplexer is configured to output one of a first clock signal and a second clock signal according to the mode selection signal, and the specific flip-flop is configured to sample the first signal or the second signal outputted by the first multiplexer by using the first clock signal or the second clock signal outputted by the second multiplexer to generate an output signal.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: July 6, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventor: Szu-Yang Chang
  • Patent number: 11056452
    Abstract: An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Md Altaf Hossain
  • Patent number: 11047909
    Abstract: Systems, methods, and circuitries are disclosed to test an inter-domain device that is positioned in a signal path between a first output wrapper device in a first module and a first input wrapper device in a second module. In one example, a testing system includes an output scan chain that includes the first output wrapper device and an input scan chain that includes the first input wrapper device. A controller is configured to: provide an output scan enable signal to the output scan chain to cause test data to be stored in the first output wrapper device; capture, with the first input wrapper device, inter-domain device data output; provide an input scan enable signal to the input scan chain to cause the inter-domain device data to be output by an output scan chain serial output; and determine whether the inter-domain device data indicates that the inter-domain device is defective.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: June 29, 2021
    Assignee: MaxLinear, Inc.
    Inventors: Himanshu Kukreja, Shakil Ahmad
  • Patent number: 11041907
    Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: June 22, 2021
    Assignee: ADVANTEST CORPORATION
    Inventors: Ben Rogel-Favila, Mei-Mei Su, John Frediani, Shunji Tachibana
  • Patent number: 11005458
    Abstract: A semiconductor integrated circuit comprises a scan flipflop comprising a scan input and a data input; and scan control circuitry. The scan control circuitry is configured to control the scan flipflop to capture a value inputted to the scan input in a capture mode.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: May 11, 2021
    Assignee: Synaptics Incorporated
    Inventor: Takahisa Nakako
  • Patent number: 10976366
    Abstract: A scan controller provides a translation between a two terminal external interface and a four signal line internal scan interface to a digital core of the integrated circuit. The two terminal external interface has an input terminal and an input/output terminal. The input terminal receives a clock signal and the input/output terminal serially receives a scan enable signal and a scan in data bit. A state machine controls the scan controller. The scan in data bit, the scan enable signal, and a scan clock signal are supplied in parallel to the internal scan interface. The digital logic provides a scan out data bit and the scan controller supplies the scan out data bit over the input/output terminal in synchronism with the clock signal.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: April 13, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Patrick J. de Bakker, Michael R. May
  • Patent number: 10969432
    Abstract: A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Beom Seok Shin, Jinsoo Park
  • Patent number: 10921848
    Abstract: An integrated circuit includes multiple blocks of circuitry (4, 6, 8) communicating signals via an interface 10 controlled by a clock signal. A clock mesh (20, 22) is used on at least one side of the interface driven by one or more clock drivers (24, 26) that drive the clock mesh with the clock signal communicated with a further block of circuitry. A plurality of interface storage circuits (flip-flops) (12, 14, 16, 18) are coupled to the clock mesh and receive the clock signal from the clock mesh to control storage therein. The interface storage circuits (54) may be of a form controlled by multiple clock signals, CP0, CP1. A signal value D may be captured into the storage circuit upon a rising edge of a first clock signal CP0 and launched from the storage circuit upon the rising edge of a second clock signal CP1.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: February 16, 2021
    Assignee: ARM Limited
    Inventor: Ramnath Bommu Subbiah Swamy
  • Patent number: 10921372
    Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: February 16, 2021
    Assignee: Seagate Technology LLC
    Inventors: Rajesh Maruti Bhagwat, Nitin Satishchandra Kabra, Jay Shah
  • Patent number: 10839863
    Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 17, 2020
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, John W. Poulton
  • Patent number: 10782345
    Abstract: Devices and techniques are disclosed herein for debugging a device implemented on a die using non-test pins. An instruction to enable a debugging mode of operation is received with a memory device implemented at least in part on a die. In response to receiving the instruction, functionality of a first non-test pin of the die is modified to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die. A debugging clock signal is established using a signal received at a second non-test pin of the die. Information including the debugging data is exchanged between the die and the debugging component using the first and second non-test pins of the die.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Nadav Grosz
  • Patent number: 10775434
    Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Michael Mishaeli, Larisa Novakovsky, Edward Brazil, Alexander Gendler
  • Patent number: 10739402
    Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mudasir Shafat Kawoosa, Rajesh Mittal
  • Patent number: 10692583
    Abstract: Provided are a multi-channel package capable of reducing a test cost while performing a test at a high speed, and a test apparatus and a test method of testing the multi-channel package. The multi-channel package includes: a package substrate; and at least two semiconductor chips mounted on the package substrate and having different channels, wherein each of the at least two semiconductor chips includes a built-in-self-test (BIST) circuit and operates in one of a self-test mode, a tester mode, and a target mode during a test, and in the tester mode or the target mode, the at least two semiconductor chips are configured to be inter-channel cross-tested through an external signal path of the package substrate.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-seob Shin
  • Patent number: 10678674
    Abstract: A novel system and method for remotely debugging a network device is disclosed. A debug system is used to transmit debug commands over a network to the network device. The network device interprets the debug commands. The processing unit on the network device includes a special debugging mode where it is able to perform special debug operations. This special debugging mode operates at a priority that is lower than that of the network interface so that the network device can still receive network packets while being debugged. The network device also has the ability to generate responses to the debug commands in some embodiments. The concept of wireless debugging can also be applied to multi-core processors as well.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 9, 2020
    Assignee: Silicon Laboratories, Inc.
    Inventor: Lauri Mikael Hintsala
  • Patent number: 10642709
    Abstract: A method for refining multithread software executed on a processor chip of a computer system. The envisaged processor chip has at least one processor core and a memory cache coupled to the processor core and configured to cache at least some data read from memory. The method includes, in logic distinct from the processor core and coupled to the memory cache, observing a sequence of operations of the memory cache and encoding a sequenced data stream that traces the sequence of operations observed.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: May 5, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Susan Carrie, Vijay Balakrishnan
  • Patent number: 10585141
    Abstract: A pin connection testing system for connector, and a method thereof are disclosed. In the pin connection testing system, a JTAG instruction is used to control a PLD, to drive the demultiplexer to transmit each to-be-tested signal, which is from the connector, to a first line or a second line; and, when the to-be-tested signal is transmitted to the first line, the to-be-tested signal is converted from analog to digital and encoded, and then transmitted to I/O pins of the PLD for reading; and, when the JTAG command is transmitted to the second line, the PLD reads the statuses of the I/O pins electrically connected to the second line; and then the PLD generates a test result according to the to-be-tested signals and the read I/O pins. Therefore, the technical effect of improving convenience in testing the connection status of the connector can be achieved.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 10, 2020
    Assignees: Inventec (Pudong) Technology Corporation, Inventec Corporation
    Inventor: Ping Song
  • Patent number: 10578672
    Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: March 3, 2020
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: David Jacquet, Didier Fuin
  • Patent number: 10515039
    Abstract: A vehicle USB hub system that includes a USB hub, a controller and memory unit is provided. The vehicle USB hub system collects data link quality metrics for messaging to and within a vehicle. The USB hub has a CRC error detector for detecting CRC errors in messaging received via its ports. Information regarding detected CRC errors is stored in the memory unit. The controller generates a CRC error log using the information stored in the memory unit upon receiving an indication that an error log should be sent. The controller then sends the CRC error log to a device via the USB hub port indicated.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 24, 2019
    Assignee: Molex, LLC
    Inventors: Joseph D. Stenger, Robert Sosack
  • Patent number: 10459029
    Abstract: An on-chip clock (OCC) circuit of an integrated circuit includes a clock generator, an OCC controller, and an OCC observation circuit. The clock generator is configured to generate a plurality of clock signals. The OCC controller is configured to receive the clock signals and generate an OCC output for use by the scan chains of logic blocks. The OCC observation circuit is configured to generate a status output on a status output port based on the OCC output during an at-speed capture phase and a scan enable signal. Patterns of the status output with respect to the scan enable signal include a valid pattern indicating that the OCC output includes a valid number of at-speed capture pulses, a first invalid pattern indicating a first error in the OCC output, and a second invalid pattern indicating a second error in the OCC output that is different from the first error.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: October 29, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Paras Gangwal, Komal Shah, Surbhi Bansal, Sachin Bastimane
  • Patent number: 10451668
    Abstract: A system for performing an automated test is disclosed. The system comprises a user computer operable to load a test program from a user to a control server, wherein the test program comprises a plurality of test flows. The system further comprises a tester deploying a plurality of primitives. Further, the control server is communicatively coupled to the user computer and to the tester, wherein the control server is operable to download the test program to a primitive from the plurality of primitives, and wherein the control server is further operable to execute a first test flow from the plurality of test flows on a first DUT within the primitive and concurrently execute a second test flow from the plurality of test flows on a second DUT within the primitive.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 22, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Rotem Nahum, Rebecca Toy, Boilam Phan, Jungtsung Liu, Leon Chen
  • Patent number: 10401426
    Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 3, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10347354
    Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventor: David J. Zimmerman
  • Patent number: 10330729
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 25, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10325048
    Abstract: An integrated circuit test method provides an interactive shell environment having analysis modules organized as a directory such that for a given session a user can access any of the analysis modules. This invention describes a virtual directory structure for navigating through the entire test data starting from design, test configuration, ATPG patterns, failure information and callout information. This structure also allows the creation of a scripting environment for the user to select a specific configuration and process the information. User can achieve all of this in a single session as opposed to working on every test configuration in an independent session.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 18, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sameer Chakravarthy Chillarige, Sonam Kathpalia, Mehakpreet Kaur, James S. Allen, Krishna Vijaya Chakravadhanula
  • Patent number: 10267852
    Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10261128
    Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Pramod Kumar, Vinay Kumar
  • Patent number: 10255150
    Abstract: Provided are a multichip debugging method and a multichip system adopting the same. The multichip system includes: a first chip including a first debugging port and first identification (ID) information, a second chip including a second debugging port and second ID information, and a test access port (TAP) electrically connected to the first debugging port and the second debugging port and configured to connect to a test apparatus via the TAP.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-min Kim, Chan-ho Yoon, Jung-pil Lee, Hyung-joon Park, Jae-ho Sim
  • Patent number: 10254341
    Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 9, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10210130
    Abstract: Circuits and methods for efficient interconnect layout of multiple circuit elements, including integrated circuits (ICs), within a circuit module, while enabling only a single control/status (C/S) connection per module. In a first embodiment, the C/S interfaces of multiple ICs are configured in parallel within a multi-IC module, and coupled through a single module serial bus to a system C/S serial bus. In a second embodiment, the C/S interface of a primary IC is coupled through a single module serial bus to a system C/S serial bus, while a secondary IC is internally serially coupled to a “pass through” interface of the primary IC. In a third embodiment, a dynamic address translation circuit translates device and register address information provided by a master device into corresponding internal addresses, and re-directs command messages from a system C/S serial bus to internal slave devices.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 19, 2019
    Assignee: pSemi Corporation
    Inventors: David Alan Podsiadlo, Yuji Shintomi
  • Patent number: 10210118
    Abstract: Circuits and methods for efficient interconnect layout of multiple circuit elements, including integrated circuits (ICs), within a circuit module, while enabling only a single control/status (C/S) connection per module. In a first embodiment, the C/S interfaces of multiple ICs are configured in parallel within a multi-IC module, and coupled through a single module serial bus to a system C/S serial bus. In a second embodiment, the C/S interface of a primary IC is coupled through a single module serial bus to a system C/S serial bus, while a secondary IC is internally serially coupled to a “pass through” interface of the primary IC. In a third embodiment, a dynamic address translation circuit translates device and register address information provided by a master device into corresponding internal addresses, and re-directs command messages from a system C/S serial bus to internal slave devices.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 19, 2019
    Assignee: pSemi Corporation
    Inventors: David Alan Podsiadlo, Edward Nicholas Comfoltey
  • Patent number: 10197626
    Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: February 5, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10185606
    Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: January 22, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Peter Yan, Alan Gatherer, Alex Elisa Chandra, Lee Dobson Mcfearin, Mark Brown, Debashis Bhattacharya, Fang Yu, Xingfeng Chen, Yan Bei, Ke Ning, Chushun Huang, Tong Sun, Xiaotao Chen
  • Patent number: 10126363
    Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Wen-Yi Lin, Girishankar Gurumurthy
  • Patent number: 10126364
    Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: November 13, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10120022
    Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: November 6, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10114075
    Abstract: System and method for performing scan test on multiple IC devices by site-multiplexing. Multiple test sites of an ATE are coupled to multiple DUTs through a multiplexer. A scan test includes a scan-in/out phase and consecutive launch/capture cycles. Each site performs scan in/out in parallel on the corresponding DUT. In each launch/capture cycle, a respective site drives/captures data from a DUT while the remaining sites are inactive. The multiplexer allows the active site to borrow test channels assigned to other test sites such that all the test data of a DUT can be driven/captured in the launch capture cycle despite the test channel limitation of the active test site. As the tester channels receive interleaved data of the multiple sites, each strobe edge of a receive channel is assigned to a particular test site and used to quickly identify a failure site without post-processing test data.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: October 30, 2018
    Assignee: Advantest Corporation
    Inventor: Matthias Werner