Abstract: A user terminal, a debugging device, and a data backup method are provided. The user terminal includes a storage component, an I/O controller, a main controller, a first CC controller, a first MUX, a second MUX, a third MUX, and a first interface. The first CC controller is connected to each of the first interface and a first signal selection input end of the first MUX; a first signal input end of the first MUX is connected to the I/O controller, a second signal input end of the first MUX is connected to the main controller, and a first signal output end of the first MUX is connected to the first interface; the main controller is connected to each of a second signal selection input end of the second MUX and a third signal selection input end of the third MUX.

Abstract: A basic logic element includes: a calculation unit configured to perform calculation processing; a self-diagnosis unit configured to self-diagnose whether or not there is an abnormality in a result of the calculation output from the basic logic element; a management unit configured to determine whether or not to retain authority to output the result of the calculation based on a result of the diagnosis performed by the self-diagnosis unit and output a result of the determination as an authority signal; and an output control unit configured to control whether or not to output the result of the calculation performed by the calculation unit based on whether or not the authority to output data is retained by the management unit.

Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.

Abstract: A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

Abstract: Apparatuses, systems, and methods for signal encryption in high bandwidth memory are described. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.

Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.

Abstract: A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

Abstract: In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

Abstract: An industrial monitoring system comprises monitoring devices that are enabled for debugging by a component comprising a first microcontroller unit and a second microcontroller unit. The monitoring device receives a debugging command based on a subscription, on a publish-subscribe communications channel, to events indicative of requests to perform debugging operation. The second microcontroller unit causes the first microcontroller unit to perform the command. Results of performing the command are returned by publishing an event to the publish-subscribe communications channel.

Abstract: A memory component comprises a memory unit including an array of memory cells, a controller of the memory unit, and a JTAG test interface including a plurality of contact pads adapted to connect the memory component with a host device and/or a test machine, wherein the test interface further comprises a plurality of test registers, which are configured to store the operating instructions for performing the test of the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. A related System-On-Chip device and a related method are further disclosed.

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Abstract: The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains. The operational mode information comprising information of the full-toggle scan chains may be determined based on reduced toggle ranges first and the hold-toggle pattern may then be determined using a relaxation method. Alternatively, the hold-toggle pattern and the full-toggle scan chains may be determined incrementally together.

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

Abstract: A system-on-chip (SoC) is disclosed. The SoC includes a set of input channels, a first partition including a set of output wrapper chains, a set of output channels, a second partition including a set of input wrapper chains, and an inter-partition circuit coupled between the first and second partitions. During an external test mode, the set of input channels receives input test data. The set of output wrapper chains receives and stores intermediate data that is generated based on the input test data. The inter-partition circuit receives the intermediate data from the set of output wrapper chains and generates test response data based on the intermediate data. The set of input wrapper chains receives the test response data, and provides the test response data to be captured as output test data at the set of output channels to test the inter-partition circuit.

Abstract: Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

Abstract: A semiconductor device, a test method, and a system including the same are disclosed, which may relate to a technology for testing open and short states of a pad of a semiconductor device.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: A test system includes a transmitter, capacitor, and receiver. The transmitter includes: an output circuit coupled to the receiver via the capacitor; a transmitting circuit transmitting a predetermined signal to a pad of the output circuit during a first test; a signal generator outputting a first signal and second signal to the pad during a first process and second process of a second test; and a comparator comparing the pad's signal with a reference signal in the first process and second process to determine whether the second test passes. The receiver includes: an input circuit coupled to the transmitter via the capacitor; a switch coupled between the input circuit and a receiving circuit to be conducting in the first test and second process and nonconducting in the first process; and the receiving circuit determining whether the first test passes according to the predetermined signal and assisting the capacitor in discharging.

Abstract: A display device includes a panel unit including a display unit, a first circuit board connected to the display unit, and a first connecting member connected to the first circuit board, an input unit including a connection member configured to attach to the first connecting member, and to provide an image signal to the panel unit, a master configured to output a transmitting signal for diagnosing an electrical connection between the first connecting member and the connection member, a transmitting line connected to the master, an inspecting line configured to connect to the transmitting line through the connection member, and a slave configured to connect to the master through the inspecting line, to receive the transmitting signal as a receiving signal, and to enable determination of on-time duty and off-time duty of the receiving signal to determine whether a connection error between the panel unit and the input unit exists.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: An augmented simulation model can be created of an integrated circuit (IC) design by inserting a switch in a simulation model of the IC design between an output of a scan cell and an input of a combinational logic cloud. A simulation enable signal can be used to control the switch. Next, an IC design simulation environment can be generated based on the augmented simulation model. The IC design can be verified by using the IC design simulation environment. The simulation enable signal can be activated when the combinational logic cloud is desired to be simulated by the IC design simulation environment.

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

Abstract: Boundary scan test data and a command to initiate a boundary scan test are received via a universal asynchronous receiver-transmitter (UART). Based on receiving the command, a boundary scan test mode is initiated at a memory sub-system controller. A boundary scan test vector based on the boundary scan test data is synchronously streamed to a boundary scan chain. Test result data output by the scan chain is provided to a UART host via the UART.

Abstract: One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.

Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO of the JTAG controller.

Abstract: A software-defined linear feedback shift register (SLFSR) implements a low-power test compression for launch-on-capture (LOC). Each bit of an extra register controls a stage of the SLFSR. A control vector is shifted into the extra register to indicate whether a primitive polynomial contains the stage of the non-zero bit. Therefore, SLFSR can configure any primitive polynomials with different degrees by loading different control vectors without any hardware overhead. A low-power test compression method and design for testability (DFT) architecture provide LOC transition fault testing by using seed encoding scheme, low-power test application procedure and a software-defined linear-feedback shift-register (SLFSR) architecture. The seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set.

Abstract: Systems, methods and computer-readable storage media are provided for detecting and simulating issues in a network.

Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including: a first scan chain and a second scan chain; a clock generator; and a test control circuit. The first scan chain includes: a first flip-flop having a first scan data input terminal and a first output terminal; and a first multiplexer. The first multiplexer is configured to electrically couple the first scan data input terminal to the first output terminal based on a first signal received from the test control circuit to form a first closed loop. The second scan chain includes a second flip-flop having a second scan data input terminal and a third output terminal that is not coupled to the second scan data input terminal.

Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.

Abstract: The present invention provides a circuit having a plurality of modes, wherein the circuit includes a first circuit, a second circuit, a first multiplexer, a second multiplexer and a specific flip-flop. In the operations of the circuit, the first circuit is configured to generate a first signal, the second circuit is configured to generate a second signal, the first multiplexer is configured to output one of the first signal and the second signal according to a mode selection signal, the second multiplexer is configured to output one of a first clock signal and a second clock signal according to the mode selection signal, and the specific flip-flop is configured to sample the first signal or the second signal outputted by the first multiplexer by using the first clock signal or the second clock signal outputted by the second multiplexer to generate an output signal.

Abstract: An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.

Abstract: A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

Abstract: Systems, methods, and circuitries are disclosed to test an inter-domain device that is positioned in a signal path between a first output wrapper device in a first module and a first input wrapper device in a second module. In one example, a testing system includes an output scan chain that includes the first output wrapper device and an input scan chain that includes the first input wrapper device. A controller is configured to: provide an output scan enable signal to the output scan chain to cause test data to be stored in the first output wrapper device; capture, with the first input wrapper device, inter-domain device data output; provide an input scan enable signal to the input scan chain to cause the inter-domain device data to be output by an output scan chain serial output; and determine whether the inter-domain device data indicates that the inter-domain device is defective.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: A semiconductor integrated circuit comprises a scan flipflop comprising a scan input and a data input; and scan control circuitry. The scan control circuitry is configured to control the scan flipflop to capture a value inputted to the scan input in a capture mode.

Abstract: A scan controller provides a translation between a two terminal external interface and a four signal line internal scan interface to a digital core of the integrated circuit. The two terminal external interface has an input terminal and an input/output terminal. The input terminal receives a clock signal and the input/output terminal serially receives a scan enable signal and a scan in data bit. A state machine controls the scan controller. The scan in data bit, the scan enable signal, and a scan clock signal are supplied in parallel to the internal scan interface. The digital logic provides a scan out data bit and the scan controller supplies the scan out data bit over the input/output terminal in synchronism with the clock signal.

Abstract: A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.

Abstract: An integrated circuit includes multiple blocks of circuitry (4, 6, 8) communicating signals via an interface 10 controlled by a clock signal. A clock mesh (20, 22) is used on at least one side of the interface driven by one or more clock drivers (24, 26) that drive the clock mesh with the clock signal communicated with a further block of circuitry. A plurality of interface storage circuits (flip-flops) (12, 14, 16, 18) are coupled to the clock mesh and receive the clock signal from the clock mesh to control storage therein. The interface storage circuits (54) may be of a form controlled by multiple clock signals, CP0, CP1. A signal value D may be captured into the storage circuit upon a rising edge of a first clock signal CP0 and launched from the storage circuit upon the rising edge of a second clock signal CP1.

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

Abstract: Devices and techniques are disclosed herein for debugging a device implemented on a die using non-test pins. An instruction to enable a debugging mode of operation is received with a memory device implemented at least in part on a die. In response to receiving the instruction, functionality of a first non-test pin of the die is modified to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die. A debugging clock signal is established using a signal received at a second non-test pin of the die. Information including the debugging data is exchanged between the die and the debugging component using the first and second non-test pins of the die.

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Abstract: Provided are a multi-channel package capable of reducing a test cost while performing a test at a high speed, and a test apparatus and a test method of testing the multi-channel package. The multi-channel package includes: a package substrate; and at least two semiconductor chips mounted on the package substrate and having different channels, wherein each of the at least two semiconductor chips includes a built-in-self-test (BIST) circuit and operates in one of a self-test mode, a tester mode, and a target mode during a test, and in the tester mode or the target mode, the at least two semiconductor chips are configured to be inter-channel cross-tested through an external signal path of the package substrate.

Abstract: A novel system and method for remotely debugging a network device is disclosed. A debug system is used to transmit debug commands over a network to the network device. The network device interprets the debug commands. The processing unit on the network device includes a special debugging mode where it is able to perform special debug operations. This special debugging mode operates at a priority that is lower than that of the network interface so that the network device can still receive network packets while being debugged. The network device also has the ability to generate responses to the debug commands in some embodiments. The concept of wireless debugging can also be applied to multi-core processors as well.

Abstract: A method for refining multithread software executed on a processor chip of a computer system. The envisaged processor chip has at least one processor core and a memory cache coupled to the processor core and configured to cache at least some data read from memory. The method includes, in logic distinct from the processor core and coupled to the memory cache, observing a sequence of operations of the memory cache and encoding a sequenced data stream that traces the sequence of operations observed.