Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.

Abstract: An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, testing each of the plurality of devices, and providing test results to the ATE. The method comprises mounting a plurality of devices to be tested on the test load board, using the daughter card to communicate with the test board and the ATE, and using the daughter card for testing each of the plurality of DUTs, providing test results to the ATE. Also provided is a system to perform automated tests of integrated chips, comprising an ATE scan test unit, an off-load tester resource coupled to the ATE scan test unit, a processor executing commands to control the ATE unit and the off-load tester resource.

Abstract: The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

Abstract: Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with first data; executing a first iteration of the system to process the first data; partially reconfiguring the PLD, during execution of the first iteration, to initialize shadow memory elements in the PLD with second data, the shadow memory elements respectively shadowing the memory elements in the system; transferring the second data from the shadow memory elements to the memory elements; and executing a second iteration of the system to process the second data.

Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: Systems, apparatuses, and methods for system and application debugging are described herein. A tested platform may include a debug event monitor in a boundary scan interface that detects a debug event in a process and determines a characteristic associated with the debug event. The debug event monitor may trigger an application debug event or a boundary scan debug event based at least in part on the determined characteristic. Other embodiments may be described and claimed.

Abstract: A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration information is received from a signal line at each of the controllers, wherein the plurality of controllers are connected in parallel to the signal line and the configuration information is stored within each controller that matches a selection criteria following the selection event when the selection event initiates a selection sequence.

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Abstract: A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase.

Abstract: Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used to support programming, testing, and user mode operations. Programming operations may be performed on a programmable logic device integrated circuit by receiving configuration data with the differential communications circuitry and storing the received configuration data in nonvolatile memory. The nonvolatile memory may be located in an external integrated circuit such as a configuration device or may be part of the programmable logic device integrated circuit. The stored configuration data may be loaded into configuration memory in the programmable logic device to program the device to perform a desired custom logic function. The differential communications circuitry may be used to handle boundary scan tests and programmable scan chain tests. During user mode operations the differential communications circuitry carries user data traffic.

Abstract: A boundary scan circuit comprising a freeze circuit and a transparency circuit provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving power. There are two transparency circuit configurations, one that connects to an input pad cell and one that connects to an output pad cell. The circuitry in the transparency circuit is controlled in such a manner as to establish at the output of transparency circuit a known logic state to control leakage current resulting from the circuitry of the various pad cell configurations, which further conserves power during sleep mode.

Abstract: An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.

Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.

Abstract: Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a received data input. The plurality of data blocks may each include registers configured to store data, each of the plurality of data blocks being configured to write over at least some of the data stored in their respective registers in response to receiving a write-over instruction. The reset node may be configured to reset the registers based on receiving either a first reset input or a second reset input. The integrated circuit may be configured to enter a test mode, enter a scan mode, and exit the test mode.

Abstract: An integrated circuit includes an embedded processor. An embedded in-circuit emulator is located within the embedded processor. The embedded in-circuit emulator performs a test on the integrated circuit. The embedded in-circuit emulator generates a testing result based on the test on the integrated circuit. Trace logic to generate trace data based on the testing result, the trace data being in a parallel format. A serializer is located on the integrated circuit. The serializer converts the parallel format of the trace data into a serial format. The serializer serially outputs the trace data in the serial format from the integrated circuit.

Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Abstract: An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.

Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

Abstract: An apparatus (such as a printer) including a combination engine controller circuit board having a integrated circuit (IC) chip configured to process (format) incoming data as well as to control the operations of the apparatus is disclosed. The IC chip is adapted to receive and process data as well as to control the operations of the apparatus. For this reason, the IC chip is referred to as a combined controller IC.

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

Abstract: System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols.

Abstract: An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different among the target systems, outputting a bit from its bit pattern on the control signal. The process further comprises each target system comparing the resulting state of the control signal to that target system's output bit. If the target system's output bit differs from the resulting control signal state, the target system ceases participating in the ID process or, if the target system's output bit matches the resulting control signal state, the target system continues to participate in the ID process.

Abstract: Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell.

Abstract: An integrated circuit includes logic circuits including the first and second logic circuits, and a scan chain configured to test the logic circuits. The scan chain includes the first scan chain portion for testing the first logic circuit based on an input test pattern and output the first output test pattern, a switching unit for selecting and outputting one of the input test pattern and the first output test pattern as a selected test pattern, and the second scan chain portion for testing the second logic circuit based on the selected test pattern from the switching unit and output the second output test pattern. The switching unit selects one of the input test pattern and the first output test pattern based on at least one of a logic depth, a number of gates, a number of gate inputs and a number of gate outputs of the logic circuits.

Abstract: A method and apparatus allows controlling a plurality of test operations in an electronic device, and in particular a volatile or non-volatile memory device in which a test mode has already been established, without the need for additional device connections. One such operation may be switching device operation from test mode to functional mode, the normal operating mode of the device. Other test operations include support of continuity testing by external circuitry, support of externally accessing device identification with which the device has been previously programmed, support of built in self-test, support of self-repair and support of other operations determined as needs arise.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method implements one of a selectable plurality of control levels in the command window based on the number of the at least one zero-bit scans.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.

Abstract: A scan control method for a circuit device connected with a first bus and having a test access port controller, including setting information indicating a register to be scanned in the circuit device, a number of scan shifts and a scan start via a second bus different from the first bus, and generating based on the information set, by using a sequencer, a signal replacing a test mode signal and a test reset signal transferred via the first bus during testing of the circuit device, and supplying the signal to the test access port controller.

Abstract: Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.

Abstract: A method and system to facilitate a scalable scan system in the design of a system-on-chip. In one embodiment of the invention, the system-on-chip includes a controller and one or more clock gating units. The clock gating unit is added to each unique clock domain of each function or logic block in the system-on-chip. By having a controller that connects to each clock gating unit and the scan input and output signals in each logic block of the SOC, this allows a scalable scan system in the design of the SOC and allows frequent block level design changes in the SOC without extensive changes to the scan logic in one embodiment of the invention. In addition, the scalable scan system also allows at-speed scan write-through testing of a memory array that can improve the scan test coverage of the system-on-chip.

Abstract: Serial data communication methods and apparatus using a single line are provided. The data communication methods may include: setting a rising edge of a serial pulse signal so that a cycle of the serial pulse signal begins therefrom; setting a falling edge of the serial pulse signal within the cycle of the serial pulse signal according to a data value recorded within the cycle of the serial pulse signal; and transmitting a packet formed by combining at least one cycle of the serial pulse signal in series via a single line.

Abstract: A debugging module for connecting an IC to a JTAG debugger device includes a JTAG interface, an earphone circuit, a USB interface, a switching unit, and a reset circuit. The earphone circuit is electrically connected to the JTAG interface via the switching unit. The USB interface and the reset circuit are electrically connected to the JTAG interface. When a JTAG debugger device is connected to the earphone circuit and the USB interface, the earphone circuit and the USB interface, respectively, can establish a connection between the JTAG debugger device and the JTAG interface.

Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

Abstract: The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.