Abstract: A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase.

Abstract: A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.

Abstract: Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used to support programming, testing, and user mode operations. Programming operations may be performed on a programmable logic device integrated circuit by receiving configuration data with the differential communications circuitry and storing the received configuration data in nonvolatile memory. The nonvolatile memory may be located in an external integrated circuit such as a configuration device or may be part of the programmable logic device integrated circuit. The stored configuration data may be loaded into configuration memory in the programmable logic device to program the device to perform a desired custom logic function. The differential communications circuitry may be used to handle boundary scan tests and programmable scan chain tests. During user mode operations the differential communications circuitry carries user data traffic.

Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.

Abstract: A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all flip-flops in the core. The partial residual test mode spans across a subset of the cores and allows to bound the number of cores that a full residual test mode may span across. The interaction of the cores among one another at the top-level is analyzed and the minimum number of flip-flops in a core that must participate in a intermediate test mode is selected. Algorithms are devised to analyze the interactions among the cores and build data structures which are used for identifying intermediate test modes. Using a reconfigurable scan segment architecture, intermediate test modes are implemented that are designed to work with all known test compression solutions.

Abstract: An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR.

Abstract: The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test signal through the shared pins. Pins necessary for the microelectronic device are therefore reduced.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.

Abstract: A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a plurality of clock signals. As a result of receiving a signal, the circuit logic uses the plurality of clock signals to obtain the first and second data and to provide the first and second data to target logic coupled to the circuit logic. The system resets the circuit logic between providing the first data and providing the second data.

Abstract: Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described. An integrated circuit has circuitry that compacts test response data from scan chains in the integrated circuit under test. In many cases groups of the scan chains are coupled to output registers, such that a same group of scan chains is coupled to sequential elements of different output registers; and the same group is a subset of the scan chains including two or more scan chains. Various computer-implemented methods divide scan chains among at least groups and partitions. The groups disallow sharing a common scan chain from the scan chains, within a particular partition. At least one common scan chain is shared between the groups of different partitions.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Abstract: A semiconductor device test system has an interface for use with a semiconductor device test method, and a semiconductor device test method. In a first mode of an interface, in reaction to test signals corresponding to a test standard, for example, a JTAG test standard, and received by the interface from a test device, the interface outputs signals corresponding to the test standard to a semiconductor device to be tested. In a second mode of the interface, in reaction to test signals corresponding to the test standard and received by the interface from a test device, the interface outputs signals that do not correspond to the test standard to a semiconductor device to be tested.

Abstract: This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: A testing circuit has scan chain segments (62,64,60) defined between parallel inputs (wpi[0] . . . wpi[N?1]) and respective parallel outputs (wpo[0] . . . wpo[N?1]). The scan chain segments comprise a bank (62) of cells of a shift register circuit, a core scan chain portion (62), a first bypass path around the core scan chain portion (62) and a second bypass path around the bank (60) of cells of the shift register circuit. This architecture enables loading of data in parallel into the core scan chain, or into the shift register (WBR). In addition, each scan chain segment also has a series latching element (80), and this provides additional testing capability. In particular, the shifting of data between the latching elements (80) can be used to test the bypass paths while the internal or external mode testing is being carried out. This testing can thus be part of a single ATPG procedure.

Abstract: Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a first plurality of control inputs, a second boundary scan circuit with a second plurality of control inputs, and a plurality of boundary scan control signals connected to the first plurality of control inputs on the first boundary scan circuit and to the second plurality of control inputs on the second boundary scan circuit. At least two of the plurality of boundary scan control signals are connected between the first boundary scan circuit and the second boundary scan circuit in a crossover fashion.

Abstract: [PROBLEMS] To provide a semiconductor integrated circuit by which what has been referred to as two-pattern test is made possible without greatly increasing an occupying area. [MEANS FOR SOLVING PROBLEMS] The semiconductor integrated circuit is provided with a plurality of flip-flop circuits and selectors corresponding to each flip-flop circuit. Each flip-flop circuit is provided with a master latch and a slave latch connected to the master latch. The selector is electrically connected with the master latch of the flip-flop circuit to which the selector corresponds, and is also connected with the master latch of the flip-flop circuit other than the one to which the selector corresponds.

Abstract: A method of and an arrangement for testing connections on a printed circuit board between boundary-scan compliant circuit terminals of one or more boundary-scan compliant devices mounted at the printed circuit board and comprising a boundary-scan register of boundary-scan cells of the boundary-scan compliant circuit terminals. Under control of an electronic processing unit, boundary-scan properties of the or each boundary-scan compliant device are retrieved, a list comprising boundary-scan compliant circuit terminals is displayed, and a selection of at least a first and second boundary-scan compliant circuit terminal is received. Based on this selection, a boundary-scan cell of a first boundary-scan compliant circuit terminal of a boundary-scan compliant device is operated as a driver and a boundary-scan cell of a second boundary-scan compliant circuit terminal of a boundary-scan compliant device is operated as a sensor. The driver is controlled through data provided to the boundary-scan register.

Abstract: A scan test circuit in the present invention includes a control FF for inputting a control signal, and a scan path chain configured of scan storage elements to operate in a shift operation mode when an output of the control FF is a first status value, and in a normal operation mode when the output is a second status value. When the control signal is switched from the first status value to the second status value, the control FF outputs the second status value to multiple scan storage elements synchronously with a first clock pulse, after the switching, of a clock provided to multiple scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control FF outputs the first status value to multiple scan storage elements at a timing of the control signal switching.

Abstract: A shift register circuit is provided for storing instruction data for the testing of an integrated circuit core. The shift register circuit comprises a plurality of stages, each stage comprising a serial input (si) and a serial output (so) and a parallel output (wir_output) comprising one terminal of a parallel output of the shift register circuit. A first shift register storage element (32) is for storing a signal received from the serial input (si) and providing it to the serial output (so) in a scan chain mode of operation. A second parallel register storage element (38) is for storing a signal from the first shift register storage element (32) and providing it to the parallel output (wir_output) in an update mode of operation. The stage further comprises a feedback path (40) for providing an inverted version of the parallel output (wir_output) to the first shift register storage element (32) in a test mode of operation.

Abstract: A method and apparatus for testing an integrated circuit core or circuitry external to an integrated circuit core using a testing circuit passes a test vector from a parallel input of the testing circuit along a shift register circuit. The shift register circuit is configured to bypass one or more cores not being tested and to provide the test vector to a core scan chain of the core being tested. The bypassed cores are configured such that the associated shift register circuit portion is driven to a hold mode in which storage elements of the shift register circuit portion have their outputs coupled to their inputs. This method provides holding of the shift register stages when a core is bypassed and in a test mode, and this means the shift register stages are less prone to errors resulting from changes in clock signals applied to the shift register stages.

Abstract: The circuit and method providing dynamic scan chain partitioning delivers peak power reduction by dynamically partitioning scan chains into multiple groups, wherein transitions are equally distributed among these multiple groups. For each test pattern, a particular partitioning that leads to the even partitioning of the transitions is computed by analyzing the transition distribution of the pattern. The scan chain partitioning is formulated using an Integer Linear Programming (ILP) and an efficient greedy heuristic. The computed information is loaded into the reconfigurable scan chain partitioning hardware during the capture window. The partitioning hardware is composed of controllable clock gating logic, which is reconfigured on a per pattern basis, wherein the reconfiguration is effected by only utilizing the existing scan channels. The reconfigurability delivers a solution that is test set independent.

Abstract: A TAP Linking Module (TLM) couples plural TAPs, via select and enable signals, to an externally accessible IEEE 1149.1 interface. The select signals are outputs from the TAPs to the TLM, and the enable signals are output from the TLM to the TAPs. Each select signal is output in response to a special instruction scanned into a TAP's instruction register, which causes the TLM to be selected as the data register scan path between the TDI and TDO pins. A conventional data register scan operation shifts data through the TLM. Following the scan operation, the TLM outputs one enable signal to the TAPS and outputs select signals to a multiplexer to establish a TAP link configuration.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell.

Abstract: A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.

Abstract: An electronic circuit having a boundary scan test circuit receives, though one pin, an embedded clock encoded test signal having an encoded bit stream having occurrences of a first header followed by at least one encoded boundary scan mode bit and an encoded second header followed by at least one boundary scan test input bit. The bit stream and the clock are extracted and occurrences of the first header and second header are detected. Based on the detected occurrences the boundary scan mode bits and boundary scan input bits are identified and distributed to the electronic circuit, along with the extracted clock, and boundary scan test is performed.

Abstract: An input and/or output pad is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad comprises a pad cell comprising a pad block connected to an input buffer and/or an output buffer and arranged to be connected to one of the core input and/or output pins. The pad also comprises a pad logic module comprising a first and/or a second boundary scan cell, connected to the pad block through the input buffer and/or output buffer and arranged to feed input signals to and/or deliver output signals from the pad block, and control means connected to the first and/or second boundary scan cell(s) and adapted to receive control signals for controlling access to the first and/or second boundary scan cell(s) and feeding the first boundary scan cell with the input signals and/or outputting the output signals delivered by the first boundary scan cell.

Abstract: A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m?2) and less than the total number of m bits as an instruction that carries out a processing for a control object and interprets each bit string having an m-bit length as an instruction that carries out no processing for the control object. The m-bit length is obtained by adding a predetermined single bit string to each bit string included in the group 1 consisting of at least two or more bit strings having an n-bit length, respectively. The secondary TAP controller extracts a single bit string denoting an instruction that has an n-bit length and carries out no processing for the control object from each bit string interpreted by the primary TAP controller as an instruction that carries out a processing for the control object, then interprets the single bit string.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation/debug circuitry, and IEEE P1532 in-system programming circuitry. Internal scan test ports serve as a serial communication port for primarily accessing internal scan circuitry within ICs and cores. Today, the TAP and internal scan test ports are typically viewed as being separate test interfaces, each utilizing different IC pins and/or core terminals.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A computer is programmed to prepare a computer program for simulating operation of an integrated circuit (IC) chip, in order to test scan circuitry therein. The computer is programmed to trace a path through combinational logic in a design of the IC chip, starting from an output port of a first scan cell and ending in an input port of a second scan cell. If the first and second scan cells receive a common scan enable signal, then the computer generates at least a portion of the computer program, i.e. software to perform simulation of propagating a signal through the path conditionally, for example when the common scan enable signal is inactive and alternatively to skip performing simulation when the common scan enable signal is active. The computer stores the portion of the computer program in memory, for use with other such portions of the computer program.

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. The test vector is input from the memory to the embedded core to mimic scan chain input to the embedded core. A test result is obtained from the embedded core responsive in part to the test vector input.

Abstract: A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.

Abstract: A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.

Abstract: A system on chip (SOC) may include function blocks, and a scan chain in each of the function blocks, the scan chains being adapted to conduct scan test operations in sync with a respective one of a plurality of clock signals having a different phase relative to each other, wherein during an isolation mode, the scan chains test combination circuits of the function blocks, and during an interface mode, the scan chains of adjacent ones of the function blocks test combination circuits between the adjacent ones of the function blocks.

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: A boundary scan test circuit is capable of sequentially performing a boundary scan test with respect to semiconductor integrated circuits bonded to both surfaces of a memory board. In order to reduce a boundary scan test time, the boundary scan test circuit includes a mirror function unit which transmits data signals of a first group pin or data signals of a second group pin corresponding to the first group pin according to a mirror function enable signal, and a boundary scan test unit which receives the data signals of the mirror function unit to perform a boundary scan test.

Abstract: A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.