Abstract: A method and apparatus for tuning the activity factor of a scan capture phase is described. In one example an activity factor is determined for a die to be tested. The die may be isolated or part of a wafer. A structural scan test is modified to run with an activity factor based on the determined activity factor. The modified structural scan test is run and the die is characterized based on the test.

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal.

Abstract: An asynchronous debug interface is disclosed that allows TAG agents, JTAG-based debuggers, firmware, and software to debug, access, and override any functional registers, interrupt registers, power/clock gating enables, etc., of core logic being tested. The asynchronous debug interface works at a wide range of clock frequencies and allows read and write transactions to take place on a side channel, as well as within the on chip processor fabric without switching into a debug or test mode. The asynchronous debug interface works with two-wire and four-wire JTAG controller configurations, and is compliant with IEEE standards, such as 1149.1, 1149.7, etc., and provides an efficient and seamless way to debug complex system-on-chip states and system-on-chip products.

Abstract: Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a scan test port. The process maintains the state machine in an IDLE 1 state while receiving a scan test port capture signal and transitions the state machine to an IDLE 2 state when receiving a scan test port shift signal. The process then transitions the state machine to a SEQUENCE 1 state, then to a SEQUENCE 2 state, and then to a SEQUENCE 3 state when receiving sequential scan test port capture signals. The state machine then transitions to an UNLOCK TAP state and then back to the IDLE 1 state when receiving sequential scan test port shift signals on the test mode select/capture select lead.

Abstract: Embodiments of integrated circuits include a first input interconnect, a second input interconnect, an output interconnect, a shift register, a select register, a test access port (TAP) controller, and select register decode circuitry. The TAP controller is coupled to the first input interconnect and the select register, and the TAP controller is configured to shift a select value provided on the first input interconnect into the select register. The select register decode circuitry is configured to control, based on the select value, which of a plurality of test data output signals are provided to the output interconnect, where the plurality of test data output signals includes a first test data output signal and a second test data output signal. The first test data output signal is provided by the shift register, and the second test data output signal is received from a second integrated circuit on the second input interconnect.

Abstract: Exemplary embodiments of the present disclosure include apparatus, methods, and computer-accessible medium for a toggle-masking procedure configured to mask, e.g., most or all the unknown x's and minimizing the over-masked known bits for clustered distribution of unknown bits. According to certain exemplary embodiments, it is possible to obtain previous masking information regarding the scan chain(s) associated with a previous cycle, and mask the scan chain(s) for a present cycle based on the previous masking information.

Abstract: Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit design are determined and combined to derive a forward-tracing cone. Fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design are determined and combined to derive a backward-tracing cone. By determining intersection of the forward-tracing cone and the backward-tracing cone, a chain diagnosis sub-circuit for the test failure file is generated. Using the process, a plurality of chain diagnosis sub-circuits may be generated for a plurality of test failure files. Scan chain fault diagnosis may then be performed on the plurality of chain diagnosis sub-circuits with a plurality of computers.

Abstract: A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry further comprises transition launch mode selection circuitry configured to provide independent selection between multiple transition launch modes for each of a plurality of clock domains of the integrated circuit. The multiple transition launch modes may include, for example, at least a launch-on-shift mode and a launch-on-capture mode. These transition launch modes provide different manners of launching a given signal transition via at least one of the scan cells in a corresponding one of the clock domains. The transition launch mode selection circuitry may be configured to generate from a common shift enable signal multiple independently controllable shift enable signals for respective ones of the clock domains of the integrated circuit.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: An integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals provided, one for each of the first data storage sections, and a clock output terminal adapted to output a transfer clock; and a second semiconductor device having data input terminals which receive the transfer data, a clock input terminal adapted to receive the transfer clock, second data storage sections associated with the data input terminals respectively to store input data, and selection sections associated with the second data storage sections respectively to select either the transfer data or data shifted and output to the associated second data storage section in a first series circuit which is formed by connecting the second data storage sections in series, the selection sections supplying the selected data to the associated second data storage section.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains each having a plurality of scan cells. The scan test circuitry further comprises control circuitry comprising first switching elements configured to control selective application of respective scan input signals to respective scan inputs of respective ones of the plurality of scan chains and second switching elements configured to control selective application of a shift enable signal to respective shift enable inputs of the respective ones of the plurality of scan chains. By appropriate control of the switching elements using test data register bits or other scan chain specific control signals, one or more debug modes can be supported by the scan test circuitry of the integrated circuit.

Abstract: A system and a method for programming chips on circuit board through boundary scan technology are provided. Each chip and a Joint Test Action Group (JTAG) interface on a target circuit board are connected in series according to a boundary scan technology to form a boundary scan chain. A read and write device selects a corresponding chip according to programming data, pushes the programming data to the selected chip through the JTAG interface by using the boundary scan technology to perform programming, thereby achieving the technical effects of simplifying the programming of different chips on circuit board and enhancing the efficiency of programming chips.

Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.

Abstract: A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip.

Abstract: An integrated circuit comprises scan test circuitry, additional circuitry subject to testing utilizing the scan test circuitry, and control circuitry associated with the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells, and the associated control circuitry is coupled to at least a given one of a primary input of the integrated circuit and a primary output of the integrated circuit. The scan test circuitry is configurable by the control circuitry so as to permit testing of both an input functional path associated with the given one of the primary input and the primary output and an output functional path associated with the given one of the primary input and the primary output.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: A semiconductor device include a first wrapper including a first scan flip-flop, first control flip-flops and a first pad, the first scan flip-flop receiving a first value and second values and storing the second value for determining a function of the first pad; a second wrapper including a second scan flip-flop, second control flip-flops and a second pad, the second scan flip-flop receiving the first value from the first wrapper and storing the first value for determining a function of the second pad; and an input/output controller configured to provide a shift input signal having the first and second values to the first wrapper.

Abstract: In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.

Abstract: Exemplary apparatus, methods, and computer-accessible medium can be provided for transforming a circuit. For example, it is possible to select, from the circuit, at least one scan cell which includes a first multiplexer coupled to a first flip-flop. A second flip-flop and a second multiplexer can be inserted in the circuit. The first multiplexer can be coupled as an input to the second flip-flop, and the second multiplexer can be coupled to the output of the first flip-flop and the second flip-flop.

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: A test architecture for 3D ICs is provided in which Through-Silicon-Vias and die logic can be tested pre-bonding dies in the stack for the 3D ICs. Post-bond scan test architecture is reconfigured to be accessed during pre-bond testing through using stratigically placed MUXs and TSVs. By connecting post-bond architecture including scan flops and boundary registers to gated scan flops used in TSV testing, an internal chain of scan flops such as typically used in post-bond testing can be selectively connected to gated scan flops connected to one end of each TSV for pre-bond testing of the internal logic through the TSVs.

Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Abstract: A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in the failure log to identify a faulty scan cell. In one embodiment a single fault in a scan chain is identified. In another embodiment, a last fault and a first fault in a scan chain are identified.

Abstract: A semiconductor device includes a decoder, a first register unit, and a second register unit. The decoder generates first and second register control signals in response to an external test code signal. The first register unit is coupled to the decoder. The first register unit receives the first register control signal from the decoder. The first register unit outputs in series a plurality of test signals in response to the first register control signal. The second register unit is coupled to the first register unit. The second register unit receives the first and second register control signals from the decoder. The second register unit receives in series the plurality of test signals from the first register unit in response to the first register control signal. The second register unit outputs in parallel the plurality of test signals in response to the second register control signal.

Abstract: A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.

Abstract: The invention provides a boundary scan test interface circuit. The boundary scan test interface circuit includes N test input pads, a test interfacing module and M test output pads, wherein N and M are positive integers, and M is smaller than N. The test interfacing module is coupled to the test input pads. The test interfacing module having a plurality of logical gates, and each of input pins of each of the logical gates coupled to each of the test input pads. The test output pads are coupled to output pins of the logical gates in the test interfacing module.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: The disclosure describes a novel method and apparatus for allowing a controller to access a bus router using a communication occurring in response to one edge of a clock to select one or more devices for access using a communication occurring on the opposite edge of the clock. Additional embodiments are also provided and described in the disclosure.

Abstract: An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent violation of the select signal constraint in conjunction with scan testing. The multiplexer may be, for example, a one-hot multiplexer for which the select signal constraint indicates that only one of the select signal inputs should receive a logic high select signal at a particular time.

Abstract: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Abstract: Circuits and methods are provided for debugging an integrated circuit. An integrated circuit includes core circuitry, scan test circuitry, scan control circuitry, and debug control circuitry. The scan test circuitry includes scan chains with scan cells interspersed throughout the core circuitry. The scan control circuitry controls the scan test circuitry to scan test the core circuitry. The debug control circuitry utilizes the scan test circuitry and controls the scan control circuitry to debug failure conditions of the integrated circuit during normal use. The scan control circuitry applies a debug clock signal to a clock port of each scan cell of a given scan chain to store data values that are generated by the core circuitry into the scan cells. The scan control circuitry controls the scan test circuitry to scan shift out the stored data values generated by the core circuitry during the debug process.

Abstract: A 1149.1 TAP performs at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. In a second embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal. In a third embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states. In a fourth embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. The improvements are achieved without requiring any additional IC pins beyond the 4 required TAP pins. Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.

Abstract: An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.