Random Pattern Generation (includes Pseudorandom Pattern) Patents (Class 714/728)
  • Patent number: 11199583
    Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: December 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11193975
    Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 7, 2021
    Assignee: Intel Corportion
    Inventors: Christopher J. Nelson, Shelby G. Rollins, Hiren V. Tilala, Matthew Hendricks, Sundar V. Pathy, Timothy J. Callahan, Jared Pager, James Neeb, Bradly Inman, Stephen Sturges
  • Patent number: 11092650
    Abstract: A built-in self-test (BIST) method includes providing expanded test patterns to a logic circuit under test, generating a first signature based on a response of the logic circuit to the expanded test patterns, generating a second signature based on the first signature, wherein the second signature is a compressed version of the first signature, selecting one of the first signature or the second signature in response to a control signal, comparing the selected one of the first signature or the second signature to an expected signature, and, based on the comparison of the selected one of the first signature or the second signature to the expected signature, determining that the logic circuit passes or fails BIST.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Neil John Simpson, Alan David Hales
  • Patent number: 11057201
    Abstract: A random number sequence generation apparatus includes: a semiconductor laser device repeatedly generating a pulsed laser beam having a disordered phase; an interferometer including a first transmission line and a second transmission line, a first port connected to an input terminal side and to which the pulsed laser beam is input, a second port connected to an output terminal side and outputs the pulsed laser beam, and a third port connected to the input terminal side; a Faraday mirror connected to the second port and reflecting the pulsed laser beam; a photodiode connected to the third port and outputs an electrical signal in accordance with interference light of the pulsed laser beam that is reflected by the Faraday mirror and passes through one of the transmission lines; and an AD converter configured to generate a random number sequence on the basis of the electrical signal and a threshold.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 6, 2021
    Assignee: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventors: Akihisa Tomita, Kensuke Nakata
  • Patent number: 11038446
    Abstract: A motor driving circuit includes a plurality of pins, a Hall sensor, a Hall signal processing portion and a driving processing circuit. The test-starting pin for receiving the test-starting signal and the test signal output pin for outputting the test signal are shared with at least one pin of the plurality of pins. The Hall sensor senses the change in the magnetic field of the motor to generate a Hall signal. The Hall signal processing unit amplifies the generated Hall signal, and the driving processing circuit drives the motor based on an output signal of the Hall signal processing unit and a control signal input from one of the plurality of pins. In a test mode, the output signal is output from the test signal output pin as a test signal. In a normal mode, at least one pin is used for normal operation.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 15, 2021
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Kun-Min Chen, Shen-Min Lo
  • Patent number: 11010523
    Abstract: One, two, or three test pattern generation and encoding processes are performed for a circuit design to generate compressed test patterns for one or two input channel numbers. The one, two, or three test pattern generation and encoding processes are configured to minimize active input channels for each of the compressed test patterns. A test pattern count for each of a plurality of input channel numbers is determined based on the compressed test patterns for the one or two input channel numbers, a number of active input channels for each of the compressed test patterns, and an assumption of similar input data volumes for different numbers of input channels. The test pattern count information can be employed to determine an optimal number of input channels for a test decompressor.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 18, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Yu Huang, Janusz Rajski, Mark A. Kassab, Wu-Tung Cheng
  • Patent number: 10998075
    Abstract: A non-limiting example includes data storage circuitry. The data storage circuitry includes a built-in self-test (BIST) engine. The data storage circuitry includes a memory array including memory cells. The memory array is configured to store data based on a read-write vector associated with an address vector that includes memory addresses and according to a bit-write vector that defines bit-write enablement for the memory addresses. The memory array is configured to output a stored data vector. The data storage circuitry includes a selector configured to receive the bit-write vector, and to output a selected vector based on an initialization vector and a comparison vector based at least in part on the bit-write vector. The data storage circuitry includes a comparator configured to receive the stored data vector and the selected vector, and to output an error based on discrepancies between the stored data vector and the selected vector.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Huott, Daniel Rodko, Pradip Patel, Matthew Steven Hyde
  • Patent number: 10978170
    Abstract: A memory device including: a loopback circuit for performing a loopback operation, wherein the loopback operation includes receiving, via a loopback channel, test signals provided from a test device and feeding back the test signals to the test device via the loopback channel; and an information management circuit for outputting information of the memory device to the loopback channel.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-ho Lee, Sung-joo Park, Young Yun, Yong-jin Kim, Jae-jun Lee
  • Patent number: 10908213
    Abstract: A proposed linear time compactor (LTC) with a means of significantly reducing the X-masking effect for designs with X's and supports high levels of test data compression where: 1) The LTC consists of two parts that are unloaded into a tester through an output serializer. 2) The first part is unloaded per t shift cycles while the second part is unloaded once per test pattern. 3) One part of the LTC divides scan chains into groups such that X-masking effect between groups of scan chains is impossible. 4) One part of LTC divides shift cycles into groups such that X-masking effect between groups of shift cycles is impossible. Consequently, the X-masking effect in the proposed LTC is significantly reduced.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 2, 2021
    Assignee: Synopsys, Inc.
    Inventors: Emil Gizdarski, Peter Wohl, John A. Waicukauski
  • Patent number: 10896120
    Abstract: Methods and systems for an automated micro-scheduler testing framework that allows tests to be automatically scheduled or rescheduled based on information such as results of previously-executed tests or other external information are provided. In large-scale development environments, where individual changes to a code repository cannot be specifically fully tested due to scalability and resource issues, micro-scheduler servers may be configured and designed to automatically identify target tests and request that the target tests be executed by a continuous integration system to automatically identify and resolve breakages introduced into a codebase managed by the continuous build system in a large-scale environment.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 19, 2021
    Assignee: Google LLC
    Inventors: Sanjeev Dhanda, Eric Nickell
  • Patent number: 10866280
    Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 15, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prakash Narayanan, Nikita Naresh
  • Patent number: 10804934
    Abstract: A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: October 13, 2020
    Assignee: Saturn Licensing LLC
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 10746694
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a detection layer, a substrate, and a transistor having a transistor gate electrode, a transistor source, and a transistor drain. A capacitor gate electrode overlies the substrate, where the capacitor gate electrode and the transistor gate electrode are electrically connected with each other and with the detection layer. A capacitor well is defined within the substrate, and a gate insulator is positioned between the capacitor well and the capacitor gate electrode. A capacitor includes the capacitor gate electrode, the gate insulator, and the capacitor well.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 18, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Bin Liu, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Patent number: 10678667
    Abstract: Described herein are embodiments related to holdup self-tests in memory sub-systems for power loss operations. A processing device receives a request to perform a holdup self-test to detect a defect in a holdup circuit that powers the processing device and a memory component in the event of power loss. The processing device identifies a memory location of memory that is available and, responsive to detection of a loss of power, performs a continuous sequence of write operations to the memory location using holdup energy until all of the holdup energy is expended. After reboot, the processing device determines a number of the write operations that were successfully completed in the memory location before all of the holdup energy was expended. The processing device determines whether the number satisfies a defect criterion. Responsive to the responsive to the number satisfying the defect criterion, the processing device reports the defect associated with the holdup circuit.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Douglas Majerus, Brent Byron
  • Patent number: 10613832
    Abstract: A random number generation system and a random number generation method thereof are provided. The random number generation system includes a random number generator, a random number selection circuit, and a random number logic circuit. The random number generator receives the random number request signal to provide a first random number sequence with n bits, where n is a positive integer. The random number selection circuit receives the random number request signal to provide a bit selection signal with n bits, wherein the bit selection signal is a time varying signal and is determined by the received random number request signal. The random number logic circuit receives the random number request signal, the first random number sequence and the bit selection signal, and in response to the random number request signal to adjust the first random number sequence using the bit selection signal to provide the second random number sequence.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 7, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Wen-Chiao Ho, Pil-Sang Ryoo
  • Patent number: 10422832
    Abstract: A sequential circuit includes a data input terminal, a data path, and a redundant feedback loop. The data input terminal receives input data. The data path is connected to the data input terminal and transmits the input data to a data output terminal based on a first clock signal and a second clock signal. The redundant feedback loop is connected to the first data path and stores first data based on at least one of the first or second clock signals when the first data is equal to second data. The first data corresponds to the input data. The second clock signal is a delayed signal of the first clock signal. The second data is delayed data of the first data.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Taiki Uemura
  • Patent number: 10184980
    Abstract: A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Naman Maheshwari, Wilson Pradeep, Prakash Narayanan
  • Patent number: 10107860
    Abstract: According to an embodiment of the present invention, a computer-implemented method for testing a microelectronic chip is described. The method may include dividing, via a processor running a scanning engine, a plurality of sections of the microelectronic chip. Each of the plurality of sections includes at least two latch sets in at least one scan chain. The method may further include determining, via the processor, based on the dividing, whether each of the plurality of sections fail a data test. The determining comprises interleaving the plurality of sections by scanning, via the processor, an alternating latch set from each scan chain in a first section, and scanning an alternating latch set from each scan chain in a second section.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Todd L. Cohen, Mary P. Kusko, Hari K. Rajeev, Timothy C. Taylor
  • Patent number: 10101389
    Abstract: A method for verifying a power-management system including a controller and a plurality of power devices, wherein the controller receives a plurality of input signals to generate a plurality of control signals to control the power devices, includes: determining each of the power devices operating in a corresponding mode when the power-management operates under a power configuration; determining a target combination of the control signals when each of the power devices operates in the corresponding mode; patternlessly verifying a behavior of the controller with an input combination of the input signals for the power-management system operating under the power configuration to generate a calculated result of the control signals; comparing the calculated result to the target combination; and determining that the input combination is valid when the calculated result is equal to the target combination.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 16, 2018
    Assignee: MEDIATEK INC.
    Inventor: Jian-Wei Lin
  • Patent number: 10042698
    Abstract: In an approach to cleanup of unpredictable test results, one or more computer processors generate a data area associated with a first test instruction in a test stream. The one or more computer processors determine whether the generated data area overlaps with an unpredictable data area. In response to determining the generated data area overlaps with an unpredictable data area, the one or more computer processors determine a second test instruction associated with the overlapped unpredictable data area, where the second test instruction precedes the first test instruction in the test stream. The one or more computer processors select a location in the test stream between the first test instruction and the second test instruction. The one or more computer processors insert one or more pre-requisite instructions in the selected location, where the one or more pre-requisite instructions load the overlapped unpredictable data area with pre-defined data.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventor: Louis P. Gomes
  • Patent number: 10018672
    Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Satya Rama S. Bhamidipati, Mary P. Kusko, Cedric Lichtenau
  • Patent number: 10018671
    Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Satya Rama S. Bhamidipati, Mary P. Kusko, Cedric Lichtenau
  • Patent number: 9448284
    Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: September 20, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sreenath Narayanan Potty, Rajesh Mittal, Mudasir Shafat Kawoosa, Vivek Singhal
  • Patent number: 9443611
    Abstract: According to an embodiment, a semiconductor integrated circuit includes a memory, a bypass circuit, a first selection unit, a compression unit, and a comparison unit. The bypass circuit bypasses the test signal to output a bypass signal. When the memory is tested using a BIST circuit, the first selection unit selects a memory signal output from the memory in response to the test signal. When the BIST circuit is tested, the first selection unit selects the bypass signal. If the memory is tested, the compression unit holds a signal output from the first selection unit and if the BIST circuit is tested, the compression unit compresses and holds the signal output from the first selection unit. The comparison unit compares the signal held in the compression unit with an expectation value signal of the memory signal which is generated in the BIST circuit.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: September 13, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chikako Tokunaga, Kenichi Anzou
  • Patent number: 9224503
    Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Gorman, Michael R. Ouellette, Patrick E. Perry
  • Patent number: 9003248
    Abstract: Aspects of the invention relate to using fault-driven techniques to generate scan chain configurations for test-per-clock. A plurality of test cubes that detect a plurality of faults are first generated. Scan chains for loading specified bits of the test cubes are then assigned to a stimuli group. From the plurality of test cubes, a test cube that detects a large number of faults that do not propagate exclusively to scan chains in the stimuli group is selected. One or more scan chains that are not in the stimuli group and are needed for observing the large number of faults are assigned to a compacting group. The number of scan chains either in the compacting group or in both of the compacting group and the stimuli group may be limited to a predetermined number.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 7, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Patent number: 8996941
    Abstract: Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and a background portion are then determined for each test cube in the plurality of test cubes. The background portion corresponds to the background scan cells. Test cubes in the plurality of test cubes that have compatible main portions are merged into test cube groups. Each test cube group in the test cube groups comprises a main test cube and background test cubes. A main test cube, supplied by a tester or a decompressor, may be shifted into the scan chains. A background test cube may be shifted into background chains and be inserted into the main test cube in the scan chains based on control signals.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 31, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Janusz Rajski
  • Patent number: 8943377
    Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael W. Harper, Mack W. Riley
  • Patent number: 8914689
    Abstract: A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 16, 2014
    Assignees: Cadence Design Systems, Inc., IMEC
    Inventors: Erik Jan Marinissen, Sergej Deutsch
  • Patent number: 8887015
    Abstract: An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Iwata, Jun Matsushima
  • Patent number: 8843797
    Abstract: A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the LFSR and one or more save and restore registers; initializing a MISR and running test loops. Upon reaching a predetermined number of test loops, moving a signature of the MISR to a shadow register; then, performing a signature stability test by loading the initial seed to the LFSR; executing the predetermined number of BIST test loops, and comparing a resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register, wherein unloading is performed by way of serial MISR unloads and single bit XORs.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Franco Motika, Raymond J. Kurtulik, John D. Parker
  • Patent number: 8843802
    Abstract: The present invention relates to coding method and coding device that allow Rate-Compatible LDPC (low-density parity-check) codes to have favorable BER performance both with a low code rate and with a high code rate. In coding of LDPC codes that have plural code rates and whose all parity check matrices are composed of plural cyclic matrices, a coder 121 performs the coding in such a way that 1<w0 and w1<w0 are satisfied when the maximum column weight of the cyclic matrices in the check matrix of a certain code whose code rate is not the minimum value among the LDPC codes is defined as w0 and the maximum column weight of the cyclic matrices in the check matrix of a code having a code rate lower than that of the certain code is defined as w1.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 23, 2014
    Assignee: Sony Corporation
    Inventor: Makoto Noda
  • Patent number: 8762803
    Abstract: A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random pattern generators (PRPGs) is provided, each PRPG comprising one or more linear feedback shift registers (LFSRs). Each respective PRPG includes an XOR feedback input selectively receiving a feedback from another PRPG and predefined inputs of the respective PRPG. A respective XOR spreading function is coupled to a plurality of outputs of each PRPG with predefined XOR spreading functions applying test pseudo random pattern inputs to LBIST channels for LBIST diagnostics.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Publication number: 20140157067
    Abstract: A device under test has a connection interface, a controller, and a functional block. The connection interface is used to receive a test pattern transmitted at a first clock rate and output a functional test result. The controller is used to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate. The functional block is used to perform a designated function upon the sampled test pattern and accordingly generate the functional test result.
    Type: Application
    Filed: November 25, 2013
    Publication date: June 5, 2014
    Applicant: Silicon Motion Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20140143623
    Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicant: Syntest Technologies, Inc.
    Inventors: Nur A. TOUBA, Laung-Terng WANG, Shianling WU
  • Patent number: 8726113
    Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: May 13, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Jerzy Tyszer
  • Patent number: 8707114
    Abstract: A semiconductor device includes a decoder, a first register unit, and a second register unit. The decoder generates first and second register control signals in response to an external test code signal. The first register unit is coupled to the decoder. The first register unit receives the first register control signal from the decoder. The first register unit outputs in series a plurality of test signals in response to the first register control signal. The second register unit is coupled to the first register unit. The second register unit receives the first and second register control signals from the decoder. The second register unit receives in series the plurality of test signals from the first register unit in response to the first register control signal. The second register unit outputs in parallel the plurality of test signals in response to the second register control signal.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: April 22, 2014
    Inventor: Hiromasa Noda
  • Patent number: 8694951
    Abstract: An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: April 8, 2014
    Assignee: LSI Corporation
    Inventors: Narendra B. Devta Prasanna, Saket K. Goyal, Vankat Rajesh Atluri
  • Patent number: 8689066
    Abstract: A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Grady, Mark C. Johnson, Bradley D. Pepper, Dean G. Percy, Joseph C. Pranys
  • Patent number: 8689067
    Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: April 1, 2014
    Assignee: Marvell International Ltd.
    Inventor: Darren Bertanzetti
  • Patent number: 8683280
    Abstract: Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: March 25, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie
  • Patent number: 8627163
    Abstract: Improved apparatus, systems and methods, such as those for testing an error correction code (ECC) encoder/decoder for solid-state memory devices, are provided. In one or more embodiments, the improved systems and methods deliberately inject errors into memory storage areas of memory devices to test the operation of the ECC encoder/decoder.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Adrian Drexler, Brandi Jones
  • Publication number: 20130268818
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Application
    Filed: May 15, 2013
    Publication date: October 10, 2013
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
  • Patent number: 8549369
    Abstract: A semiconductor-based test device includes a plurality of testing clusters and a pseudorandom global stimulus source coupled to the testing clusters. Each testing cluster includes a plurality of data registers and logic elements configured to perform random logic functions for generating test data for the plurality of data registers. The pseudorandom global stimulus source generates a pseudorandom binary stimulus for the logic elements. At least some of the plurality of testing clusters are coupled together to support inter-cluster fan-out and fan-in of data register output.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: October 1, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Christian Haufe
  • Patent number: 8543887
    Abstract: The present invention relates to coding method and coding device that allow Rate-Compatible LDPC (low-density parity-check) codes to have favorable BER performance both with a low code rate and with a high code rate. In coding of LDPC codes that have plural code rates and whose all parity check matrices are composed of plural cyclic matrices, a coder 121 performs the coding in such a way that 1<w0 and w1<w0 are satisfied when the maximum column weight of the cyclic matrices in the check matrix of a certain code whose code rate is not the minimum value among the LDPC codes is defined as w0 and the maximum column weight of the cyclic matrices in the check matrix of a code having a code rate lower than that of the certain code is defined as w1.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: September 24, 2013
    Assignee: Sony Corporation
    Inventor: Makoto Noda
  • Patent number: 8543876
    Abstract: A design for test (DFT) circuitry which delivers serial data serially is disclosed. The DFT circuit has a transceiver to receive serial data and then deserialize the serial data into deserialize data. The DFT circuit also has a control logic block which receives the deserialize data and stimulates at least one test element with the test data. The test element will generate an output response from the stimulus. The DFT circuit also has an output response block which receives the output from the test element and analyses the output response. Utilizing this DFT circuitry, a high speed data delivery method can be used for testing a device-under-test (DUT). Such method could reduce test time and the test cost associated with test process.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 24, 2013
    Assignee: Altera Corporation
    Inventor: Adam J. Wright
  • Patent number: 8543877
    Abstract: Utilize a pattern generator to write a predetermined logic voltage to each memory cell of a memory chip. Read a predetermined logic voltage stored in the memory cell. Compare the predetermined logic voltage stored in the memory cell with the predetermined logic voltage to determine if the memory cell is a good memory cell or not and store a determination result corresponding to the memory cell in a data latch of the memory chip. And determine if the memory chip is a good memory chip or not according to determination results of all memory cells of the memory chip stored in the data latch of the memory chip.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 24, 2013
    Assignee: Etron Technology, Inc.
    Inventors: Wei-Ju Chen, Shi-Huei Liu, Lien-Sheng Yang
  • Patent number: 8468433
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for optimizing the size of memory devices used for error correction code storage. An apparatus (such as a memory module) may include a number of memory devices to store data and a memory device to store error correction (ECC) bits. In some embodiments, the memory devices to store data may have a density of N and the memory device to store ECC bits has a density of ½ N.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: June 18, 2013
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, Joe H. Salmon
  • Patent number: 8464115
    Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 11, 2013
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux
  • Patent number: 8443246
    Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: May 14, 2013
    Assignee: Marvell International Ltd.
    Inventor: Darren Bertanzetti