Abstract: In a failure section estimating apparatus for a sequential circuit, when it is determined that the failure section is positioned in the current stage combination circuit, an input vector estimating section estimates input vectors each of which sets to a failure state, at least a predetermined output section as a failure output section of an output boundary of a current stage combination circuit of the sequential circuit. A failure output propagation path determining section determines a failure output propagation region in the current stage combination circuit for each of the estimated input vectors to be applied to an input boundary of the current stage combination circuit. The failure output propagation region represents connection paths between the failure output section and input sections of the input boundary to which the failure output section is indirectly connected.

Abstract: A method and apparatus for using weighted random patterns in a partial scan test. A computer generates deterministic patterns on the partial scan design. Deterministic patterns that have the same number of capture clocks between adjacent scan loads are grouped together into pattern groups. A computer then determines a set of weights corresponding to each of the pattern groups. A tester then uses these weights as a filter to weighted random test patterns and applies these filtered weighted random test patterns along with the appropriate number of capture clock pulses to a device under test.