Abstract: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Abstract: In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built-in self-test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.

Abstract: A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal that is also utilized to cause the scan cells to form a serial shift register during scan testing. The clock gating circuitry may be used to determine whether a clock delay defect that causes a scan error during scan testing will also cause a functional error during functional operation, thereby improving yield in integrated circuit manufacturing.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: A scalable scan-based architecture with reduced test time, test power and test pin-count in scan based testing of ICs. In an embodiment, a test vector is scanned serially into a functional memory element at a first frequency, which then de-multiplexes the bits in the test vector to multiple sub-chains at a lower frequency. Due to the use of lower frequency to scan-in, the power dissipation is reduced. Due to the use of the higher frequency to scan-in the test vector as well as multiple sub-chains, the test time is reduced. Due to the use of the functional memory elements for scanning in the test vector at higher frequency, any number of chains can potentially be supported.

Abstract: A system and method for scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device is provided. One or more scan partitions in the embedded logic circuit are identified. Each scan partition includes one or more scan chains of scan registers. One or more interacting registers connecting scan registers of a first scan partition and scan registers of a second scan partition are identified and combined to form an interacting scan chain. The embedded logic circuit is tested by selectively activating the scan chains of the first and second scan partitions and the interacting scan chain.

Abstract: An apparatus and method for protecting the contents of a secure register from scan accessibility is disclosed. The secure register may include a number of scannable elements within a scan chain. During a normal scan test mode, the scannable elements of the secure register may be accessibly, as data may be shifted to, from, or through these elements. During certain other modes (e.g., a scan dump or memory dump), a bypass circuit may be invoked to effectively separate the scan elements associated with the secure register from the remainder of the scan chain. During operation in one of these modes, no data may be shifted to, from, or through the scan elements of the secure register. Accordingly, the bypass path may protect secure data stored in the secure register from unauthorized access.

Abstract: A test architecture adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values. The test architecture can include control logic for selecting between a linear mode and a cyclical mode. In the linear mode, only top level scan inputs are mapped to the scan chains. In the cyclical mode, outputs of the plurality of cyclical cache chains and top level scan inputs are mapped to the scan chains.

Abstract: The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources.

Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: An integrated circuit 2 provided with multiple functional units 6, 8, 10, 12, 14, and 16 for performing data processing operations as part of advancing execution of a data processing task by the integrated circuit 2. Activity detection circuitry 26 determines which of these functional circuits is inactive at the given time. If a functional is inactive, then scan control circuitry 28 may perform a scan test operation thereon using an associated serial scan chain 34, 36, 38, 40, 42, 44.

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Abstract: A method and system for reducing switching activity of a spreader network during a scan-load operation is disclosed. According to one embodiment, a spreader network receives a plurality of scan input signals from a tester. A linear feedback shift register of the spread network is updated using the plurality of scan input signals. Each bit of the linear feedback shift register is shifted at each shift cycle for a plurality of shift cycles. The linear feedback shift register outputs a nonlinear gating signal using a first set of outputs and a data value feeding one or more scan chains of the spreader network using a second set of outputs. The pipeline clock of a pipeline element of the scan chains is gated using the nonlinear gating signal, and the data value is fed to the scan chains based on the pipeline clock. The scan chains are fed with updated values at the pipeline stage.

Abstract: In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Abstract: In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.

Abstract: An integrated circuit architecture including architecture for a scan based test, where the integrated circuit includes N scan chain sets including one or more scan chains and an input register bank. The input register bank includes an input for serially receiving an N-bit input vector synchronous with a first clock signal, and N-outputs configured to substantially simultaneously provide the N-bits of the received input vector as N separate output bits. The N separate output bits are used to provide test bits for simultaneously shifting into the respective inputs of the scan chain set synchronous with a second clock signal.

Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.

Abstract: An IC having a scan chain and a testing method for a chip, comprising a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is connected to the I/O interfaces of the second interface group.

Abstract: Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

Abstract: A data processing apparatus comprises a circuit block to be tested, and a plurality of scan chains, each scan chain providing a mechanism for providing input test data to, and receiving output test data from, at least a portion of the circuit block during a test mode of operation. Configurable decompression circuitry is provided for supporting a plurality of decompression schemes associated with more than one test generation tool, and configuration circuitry is responsive to a configuration stimulus to configure the configurable decompression circuitry to implement a selected decompression scheme. Thereafter, on receipt of compressed input test data, the configurable decompression circuitry applies the selected decompression scheme to the compressed input test data to produce the input test data to be provided to the plurality of scan chains.

Abstract: Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

Abstract: On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Abstract: A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: An extraction unit of fault assumption and a finish-point FF is provided, the fault assumption is selected from fault assumption information, and a logic trace is executed from the fault assumption toward an output side. A test result of a finish-point FF obtained as a result of the trace from the fault assumption is determined. The maximum value and the minimum value of the propagation route up to the finish-point FF are determined, and a delay margin is determined from the values. A delay range is determined by using the delay margin and the test result, and a fault candidate and a delay range of the delay fault are specified by the process of the determination of the fault candidate and the delay range.

Abstract: A shift register circuit for providing plural scan signals and plural emission signals includes a plurality of shift register stages. Each shift register stage includes a scan signal generation module and an emission signal generation module. The scan signal generation module is utilized for generating a first scan signal and a second scan signal according to a first clock and a second clock having a phase opposite to the first clock. The first and second scan signals have pulses opposite to each other. The pulse width of the first scan signal is substantially twice that of the first clock. The emission signal generation module is utilized for generating an emission signal according to a third clock and a fourth clock having a phase opposite to the third clock. The pulse width of the emission signal is substantially identical to that of the third clock.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises scan cells configured to form scan chains. At least a given one of the scan cells is a multiple scan input scan cell having at least first and second scan inputs. In a first scan shift mode of operation, the given scan cell is configured with a first plurality of other scan cells into a scan chain of a first type using the first scan input. In a second scan shift mode of operation, the given scan cell is configured with a second plurality of other scan cells different than the first plurality of other scan cells into a scan chain of a second type using the second scan input.

Abstract: In a scanning-capable latch circuit, main latch circuits respectively corresponding to data inputs D1 to D4 are connected in series and, except the last-stage main latch circuit, the scanning output from each main latch circuit becomes the scanning input for the subsequent main latch circuit; while the scanning output from the last-stage main latch circuit becomes the scanning input for a slave latch circuit. Hence, in the scanning-capable latch circuit used in an information processing apparatus, the circuit area can be reduced and scanning can be performed with a small-scale circuit.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a method includes, after a layout phase of generating a design of a circuit, receiving timing information related to the design of the circuit. The method also includes selectively identifying at least one gate of a combinational logic portion of the design of the circuit to be modified to respond to a test enable signal, the at least one gate identified at least partially based on the timing information. The method also includes modifying the at least one gate. The at least one modified gate is fixed at a constant level during a test mode and is dynamically changeable during a functional mode of operation of the circuit.

Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract: Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.

Abstract: A semiconductor integrated circuit according to an aspect of the invention includes scan flip-flops and a scan control unit. The scan flip-flop outputs backup data that is held as an internal state under control of the scan control unit, and the scan flip-flop holds backup data output from the scan flip-flop in the scan flip-flop under control of the scan control unit.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.