Abstract: This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip.

Abstract: An integrated circuit device according to an embodiment of this invention includes: a memory having: a first port to which a first clock signal is input, and a second port to which a second clock signal is input; and a built-in self test circuit having: a first signal generating circuit to which the first clock signal is input, a second signal generating circuit to which the second clock signal is input, a clock selecting circuit to which the first and second clock signals are input and which selects and outputs one of the input clock signals, and a controlling circuit which outputs a clock requesting signal requesting one of the first and second clock signals to the clock selecting circuit, operates in accordance with the clock signal selected and output by the clock selecting circuit, and outputs a controlling signal for controlling one of the first and second signal generating circuits.

Abstract: A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic.

Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing.

Abstract: A semiconductor integrated circuit device includes a plurality of flip-flops configured to form a scan chain in a scan path test to operate as a shift register. The first flip-flop of the plurality of flip-flops latches a first input signal in synchronization with a clock signal, outputs a first output signal and fixes the first output signal based on the first selection control signal. A second flip-flop of the plurality of flip-flops latches a second input signal in synchronization with the clock signal, outputs a second output signal, and fixes the second output signal based on a second selection control signal. The semiconductor integrated circuit device further includes a control circuit configured to generate the first and second selection control signals such that a period during which the first flip-flop fixes the first output signal is different from a period during which the second flip-flop fixes the second output signal.

Abstract: A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: The test design cost of a circuit capable of accessing an external memory is reduced. There is included a built-in self-test circuit for use in testing an external memory separately from a memory controller for performing memory control in response to an access request to the external memory capable of being coupled to a memory interface, and a TAP controller is used to control the built-in self-test circuit and referring to a test result. There is adopted a multiplexer for switchably selecting the memory controller or the built-in self-test circuit as a circuit for coupling to the memory interface in accordance with control information externally inputted through the TAP controller. The built-in self-test circuit programmably generates and outputs a pattern for a memory test in accordance with an instruction inputted through the TAP controller, and compares data read from the external memory with an expected value.

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: An integrated circuit 2 includes a plurality of serial data transmitters 18 and a plurality of serial data receivers 20. On-chip test signal paths 22 with associated on-chip test circuits 24, 26, 28 are provided so as to permit on-chip serial data communication to be performed with test characteristics imposed by the on-chip test circuits 24, 26, 28 thereby providing on-chip stress testing of the data transmitter 18 and the serial data receiver 20.

Abstract: An interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse coded signal applied to said pin to a sequence of logic low and logic high values, and a state machine responsive to said sequence of logic values to switch the electronic system between different modes of operation.

Abstract: System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed.

Abstract: Example embodiments of the present invention include a memory device testable without using data and a dataless test method. The memory device includes a plurality of registers to store test patterns, the registers being coupled to input/output DQ pads. The test patterns are stored in the registers when a mode register of the memory device is set. The memory device transfers the test patterns to a DQ pad responsive to a write test signal, and transfers the test patterns from the DQ pad to a data input buffer responsive to a read test signal. The memory device writes the test patterns transferred to the data input buffer to memory cells. The memory device reads data stored in the memory cells responsive to the write test signal and transfers the memory cell data from the DQ pad to a comparator responsive to the read test signal. The memory device compares the test patterns to the memory cell data transferred to the comparator and generates an indicator signal to indicate the comparison result.

Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.

Abstract: A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring data to the test debug system while the test access port remains in a predefined state. The predefined state comprises a state in which no scans occur.

Abstract: A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.

Abstract: A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.

Abstract: A system for repairing embedded memories on an integrated circuit includes an external Built-In Self-repair Register (BISR) associated with every reparable memory. Each BISR is serially configured in a daisy chain with a fuse box controller. The controller determines the daisy chain length upon power up. The controller may perform a corresponding number of shift operations to move repair data between BISRs and a fuse box. Memories can have a parallel or serial repair interface. The BISRs may have a repair analysis facility into which fuse data may be dumped and uploaded to the fuse box or downloaded to repair the memory. Pre-designed circuit blocks provide daisy chain inputs and access ports to effect the system or to bypass the circuit block.

Abstract: An integrated circuit (IC) having a memory built-in self-test (MBIST) controller. The IC includes an MBIST controller and a plurality of memory arrays. One or more the memory arrays has a different physical organization with respect to other ones of the memory arrays. The MBIST controller is configured to generate a logical address of a memory under test. The MBIST controller is further configured to permute the bits to produce a physical address. The user programmed permutation enables a simple address incrementer to create an address sequence that traverses the physical organization of the memory in accordance with the type of desired test.

Abstract: A semiconductor integrated circuit includes: a first circuit having a plurality of scan chains; a second circuit connected with input/output signals of the first circuit; and a third circuit connected with the second circuit through the first circuit. The plurality of scan chains comprises a first scan chain that contains flip-flops whose input/output signals are connected with the second circuit, and a second scan chain that does not contain any flip-flop whose input/output signal is connected with the second circuit. The flip-flops operate as a shift register at a scan path test, and when the third circuit exchanges signals with the second circuit through the flip-flops of the first scan chain, the second scan chain of the first circuit operates as a shift register.

Abstract: A system on a circuit board includes a plurality of devices designed to access an electronic system on the circuit board, and a programmable logic device (PLD) connected to the plurality of devices. Each of the plurality of devices complies with a test port architecture. The PLD interfaces the plurality of devices with a test port. The PLD is capable of configuring different connectivity among the plurality of devices based on the program implemented and the assertion of input control signals. A method and apparatus configures a plurality of devices on a circuit board into a desired configuration using the PLD. The configuration includes (a) receiving a control signal at the PLD, (b) configuring at least one of the plurality of devices into a chain based on the control signal, and (c) coupling the configured chain to the test port via the PLD.

Abstract: An integrated device comprises a functional circuit, a test circuit for testing the functional circuit and for providing an error data item and a register element for storing the error data item and for outputting the error data item at an error data output of the integrated device responsive to an output signal. The register element is connected to a data input of the integrated device in order to accept a data item, which is applied to the data input, responsive to the output signal.

Abstract: A test device that makes a test of a circuit device including a plurality of modules being substitutable in terms of function for one another, and in which a function change can be made for assignment to each of the modules based on an incoming control signal. The test device includes: a control section that generates the control signal, without changing a function to be assigned to a whole of the modules, to make the function change for assignment to each of the modules at least in a group of the modules; and a determination section that detects whether the circuit device operates differently when the function change is made for assignment to the modules, and based on a detection result, determines whether or not at least the group of the modules includes a defective module.

Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: A semiconductor integrated circuit includes an MISR (Multiple-Input Signature Register) for generating and storing compressed code based upon code from a ROM, and for reading out and outputting the compressed data that has been stored. The MISR has a clock change-over unit for changing over a clock in such a manner that the MISR is caused to operate at a high-speed clock when the compressed data is generated and stored, and at a low-speed clock when the stored compressed data is read out and output.

Abstract: A semiconductor integrated circuit is configured to test a high-speed memory at the actual operation speed of the memory, even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data.

Abstract: In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal 104 from a ground terminal 30 or a power source terminal 31 connected to the semiconductor integrated circuit 11, a switch 105 for selectively switching the outputting of the ground/power-source signal 104 inputted via the input/input-output pad 103, and an expected value generation circuit 13 for generating a test expected value signal 21 based on a switch output signal 122 outputted from the switch 105.

Abstract: A semiconductor testing circuit of the present invention includes a signal line which is connected to a terminal not to be tested and a plurality of terminals to be tested of a semiconductor device; switch circuits for controlling electrical connection/disconnection between the signal line and the terminals to be tested; and a resistor connected to one end of the signal line. With this configuration, in a test on the AC characteristics of an input signal, a test signal generated by an LSI tester can be inputted to the terminals to be tested through the terminal not to be tested and the signal line by turning on the switch circuits.

Abstract: A semiconductor integrated circuit contains a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit.

Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.

Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

Abstract: In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn, each MISR may includes bit cells, each having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first and second cells. Other embodiments are described and claimed.

Abstract: A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit 104 synchronously with checking clock signal A2. When the skew margin of clock signal CKA_IN and data signal DA_IN are checked, the checking signal TCKA of flip-flop circuit 105 is input instead of clock signal CKA_IN, and the checking signal TDA of flip-flop circuit 104 is input instead of clock signal DA_IN. The timing relationship between clock signal CKB7 and checking timing signal A1 and the timing relationship between clock signal CKB7 and checking timing signal A2 are controlled independently by timing control circuit 109.

Abstract: A method and apparatus allows externally selecting a functional operation mode or one of a plurality of test operation modes of an electronic device, and in particular a volatile or non-volatile memory device, without the need for additional device connections. One variation of the method and apparatus allows unlimited switching between modes. Another variation of the method and apparatus limits test operation mode selection except at the time of powering up of the device. In either variation, mode selection is based on internally detected stimulus externally applied to the device that would not be present during normal functional operation of the device. Operation of the present invention is essentially transparent in applications where test operations are not utilized, making a device incorporating the present invention compatible with previous versions of the device where the present invention and test operation modes, such as IEEE P1581 and BIST, were not included.

Abstract: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.

Abstract: An on-chip self test circuit implemented on the same chip as a test semiconductor device includes: a test load block for receiving a test target signal; and a self test block for receiving a test target signal passing through the test load block and a test target signal inputted to an output driver together, and determining whether a change of the test target signal is within an allowable range.

Abstract: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

Abstract: A data processing device includes a first memory for use during normal operation of the device and a second memory for use during testing. The second memory stores a set of test patterns for testing of a functional module. When the data processing device is in a normal (i.e. non-test) mode of operation, data is retrieved from a first memory based on a received memory address. The retrieved data is applied to the functional module of the data processing device to perform a designated function. When the data processing device is in a test mode of operation, received memory addresses are provided to the second memory for retrieval of a test pattern associated with the address. The test pattern is applied to the functional module to generate an output pattern. The result of a test is determined by comparing the output pattern to an expected pattern.

Abstract: A semiconductor memory device is capable of performing a normal operation, while detecting an internal voltage without a special bonding method during a test mode. The semiconductor memory device comprises a switching unit and an internal reference voltage generating unit. The switching unit transfers one of an internal and an external reference voltages according to whether a test mode is being performed, wherein the external reference voltage is input from outside of the semiconductor memory device. The internal reference voltage generating unit generates the internal reference voltage having the same level of the external reference voltage to thereby supply the internal reference inside the semiconductor memory device during the test mode.

Abstract: A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.

Abstract: Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on the memory. The microcode instructions generate subroutine calls to the subroutine microcode sequencer. The subroutine instructions generate memory operation codes, address codes, and data codes for testing the memory device. BIST addresses are generated in response to the memory operation codes and the address codes. BIST data are generated in response to the memory operation codes and the data codes. Conventional memory commands are created by generating command signals, address signals, and data signals for the memory in response to the memory operation codes, the BIST data, and the BIST addresses. Test results output data may be stored in a data checker in the form of information stored in data registers or checksum registers.

Abstract: A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract: A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets. A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.

Abstract: A semiconductor apparatus comprising: a plurality of memory circuits each including a memory and an input/output selector, the memory having a plurality of memory cells and a plurality of input/output circuits respectively corresponding to the memory cells; and an incorporated self-test circuit that executes a quality test for the memory, wherein the input/output selector selects one of the input/output circuits and successively outputs data signals to the incorporated self-test circuit, the data signals read by the one of the input/output circuits from the corresponding memory cells.

Abstract: A semiconductor device includes circuits to be tested, an input terminal for receiving a tester clock signal from outside, a built-in self-test (BIST) circuit for logically testing the circuit at every cycle of a tester clock signal, and an output terminal for outputting a test result signal representing a result of testing performed in the BIST circuit. Before generating a test result signal, the BIST circuit generates a marker signal, whose phase is identical to the phase of the test result signal, instead of the test result signal.

Abstract: A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even if the system reset signal on an input pin of the electronic device is logically disconnected from the internal reset connection to the core logic, as often occurs in boundary-scan and related testing.