Structural (in-circuit Test) Patents (Class 714/734)
  • Patent number: 10460644
    Abstract: The present disclosure relates to a driving system of display panels. The driving system includes a main board and a display panel. The main board is configured with a driving chip, and the driving chip electrically connects to the display panel via a flexible circuit board to drive the display panel to display. With such configuration, the driving system is configured with the main board and the driving chip, and the driving chip is arranged on the main board, instead of the flexible circuit board. With such configuration, the space of the display area occupied by the components is reduced so as to realize the narrow border design for a top border and a bottom border of the display panel. In this way, the screen ratio of the display panel is increased.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Xingling Guo, Xiaoping Tan, Man Li
  • Patent number: 10365708
    Abstract: Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Simon N. Peffers, Sean M. Gulley, Thomas L. Dmukauskas, Aaron Gorius, Vinodh Gopal
  • Patent number: 10288682
    Abstract: An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: May 14, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 10219248
    Abstract: A method for communicating test results from a wireless device under test (DUT) using non-link testing resources. Test data resulting from testing one or more operations of the DUT are combined with other data to form one or more data packets for transmission to a tester. The test data occupies, e.g., via encoding, a portion of the one or more data packets designated for data identifying the DUT or a tester.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: February 26, 2019
    Assignee: LightPoint Corporation
    Inventors: Ruizu Wang, Christian Volf Olgaard, Qinghui Luo
  • Patent number: 10164480
    Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Jer Wang, Ching-Nen Peng, Chewn-Pu Jou, Feng Wei Kuo, Hao Chen, Hung-Chih Lin, Huan-Neng Chen, Kuang-Kai Yen, Ming-Chieh Liu, Tsung-Hsiung Lee
  • Patent number: 10027665
    Abstract: A method for querying a knowledgebase of malicious hosts numbered from 1 through N. The method includes providing a network of computers, which has a plurality of unknown malicious host machines. In a specific embodiment, the malicious host machines are disposed throughout the network of computers, which includes a worldwide network of computers, e.g., Internet. The method includes querying a knowledge base including a plurality of known malicious hosts, which are numbered from 1 through N, where N is an integer greater than 1. In a preferred embodiment, the knowledge base is coupled to the network of computers. The method includes receiving first information associated with an unknown host from the network; identifying an unknown host and querying the knowledge base to determine if the unknown host is one of the known malicious hosts in the knowledge base. The method also includes outputting second information associated with the unknown host based upon the querying process.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: July 17, 2018
    Assignee: ThreatMetrix PTY LTD.
    Inventors: Scott Thomas, David G. Jones
  • Patent number: 9983262
    Abstract: A device includes one or more random number generator (RNG) cores (e.g., true random number generator cores) and a built-in self-test controller (BIST) configured to perform various fault tests on each RNG core. The tests include a stuck-at-1 fault test, a stuck-at-0 fault test, and a transition delay fault test. For those RNG cores that have multiple ring oscillators, each individual ring oscillator is fault tested by the BIST controller. For those RNG cores that have a multi-tap inverter chain configuration, the individual taps may be tested by the BIST controller. The RNG core also may comprise a bi-stable cell which can be tested by the BIST controller as well.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 29, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Dan Trock, Ron Diamant
  • Patent number: 9600384
    Abstract: Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process. The AIC includes a plurality of communication protocols. During the software development process, the AIC configures at least one of the communication protocols to not enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a high-level programming language model is used for the peripherals.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: March 21, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Qamrul Hasan, William Chu, Lijun Pan, Hongjun Xue
  • Patent number: 9293224
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus to test a semiconductor device comprises a controller configured to perform one or more tests on the semiconductor device, a reduce low pin count (RLPC) circuit configured to write data to the semiconductor device or read data from the semiconductor device at a double data rate (DDR) with respect to a single data rate (SDR), and pad logic to couple to the semiconductor device, the pad logic configured to provide a trimmable data access time from clock (tAC) signal to select different access times of a single data rate (SDR) or a double data rate (DDR) mode of operation, wherein a loading time or an unloading time of the semiconductor device being tested, or a combination thereof, is reduced when a DDR mode is selected.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Dzung Nguyen, Luyen T. Vu
  • Patent number: 9237165
    Abstract: Technologies are directed to prevention of malicious attacks through cartography of co-processors at a datacenter. According to some examples, configuration data to create a co-processor at a field programmable gate array (FPGA) may be received at a configuration controller. The configuration controller may determine unused arrangements for the co-processor and unused placements at the FPGA corresponding to the unused arrangements. The used arrangements and the unused placements, associated with a type of the co-processor, may be stored in a configuration matrix. One of the unused arrangements and one of the unused placements corresponding to the selected unused arrangement may then be selected by the configuration controller to create the co-processor.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 12, 2016
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventors: Kevin S. Fine, Ezekiel Kruglick
  • Patent number: 9208320
    Abstract: A software distribution system comprises a computer; a first distribution device; and a second distribution device, wherein the computer includes a first software reception unit configured to receive the software; a second software reception unit configured to receive the test program corresponding to the software; and a software execution unit configured to merge the software described in an executable format and the test program, and execute, the second software reception unit attempts to acquire a test program corresponding to the software at a timing at which the first software reception unit has received the software, and makes repeated attempts at a predetermined interval when the test program cannot be acquired, and the software execution unit merges the software and the test program at a timing at which the second software reception unit has received the test program.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: December 8, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masaru Suzuki, Masaharu Akei
  • Patent number: 9195767
    Abstract: A method and apparatus for third party control of a device have been disclosed. By utilizing a third party to control a device, view and control of a device may be separated.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 24, 2015
    Assignee: Digi International Inc.
    Inventor: Michel C. Burger
  • Patent number: 9134363
    Abstract: A device that supports an operator in checking an operation of an electronic circuit mounted on a board includes the following units. A waveform obtainment unit obtains a measured waveform as a signal waveform of a voltage or current measured by the operator bringing a probe into contact with the board. A similarity calculation unit calculates a similarity between the measured waveform and each of simulated signal waveforms which are signal waveforms of a voltage or current at respective nodes on the electronic circuit and are obtained by simulating the operation of the electronic circuit. A position determination unit determines, based on node information indicating positions of the nodes, a node position on the electronic circuit which corresponds to a simulated signal waveform having a maximum similarity. A notification unit notifies the operator of the node position determined on the electronic circuit.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: September 15, 2015
    Assignee: Panasonic Corporation
    Inventors: Kenji Mizutani, Nobuyuki Otsuka
  • Patent number: 9041431
    Abstract: Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: May 26, 2015
    Assignee: Altera Corporation
    Inventors: Alan Louis Herrmann, David W. Mendel
  • Patent number: 9043665
    Abstract: A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Srinivas Patil, Abhijit Jas, Peter Lisherness
  • Patent number: 9026872
    Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: May 5, 2015
    Assignee: Xilinx, Inc.
    Inventor: Rafael C. Camarota
  • Patent number: 9013204
    Abstract: A test system is provided. A printed circuit board (PCB) includes a plurality of traces and at least one test point. A central processing unit (CPU) socket including a plurality of first pins and a memory module slot including a plurality of second pins are disposed on the PCB. Each of the second pins is coupled to the corresponding first pin of the CPU socket via the corresponding trace. A CPU interposer board is inserted into the CPU socket, and a memory interposer board is inserted into the memory module slot. The traces form a test loop via the CPU interposer board and the memory interposer board. When an automatic test equipment (ATE) provides a test signal to the test loop via the test point, the ATE determines whether the test loop is normal according to a reflectometry result of the test signal.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: April 21, 2015
    Assignee: Wistron Corp.
    Inventors: Kuan-Lin Liu, Kuo-Jung Peng
  • Patent number: 9015542
    Abstract: Apparatus and techniques for performing JTAG testing on production devices and systems through industry standard interfaces. The devices employ processors configured to receive packetized test input data from a tester over a standard communication interface such as a USB or Ethernet port and perform associated testing operations defined by the test input data, such as JTAG-compliant testing. This is facilitated, in part, via use of a bridge and one or more DFx handlers, with the bridge operating as an interface between the DFx handlers and a bus and/or interconnect over which test input and result data is transferred via the standard communication interface. The techniques enable testing such as JTAG testing to be performed on fully-assembled devices and systems without requiring the use of dedicated test or debug ports.
    Type: Grant
    Filed: October 1, 2011
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Keith A. Jones, Daniel R. Pfunder, John H. Zurawski
  • Patent number: 9003253
    Abstract: A method for testing a data packet signal transceiver device under test (DUT) that minimizes time lost due to waiting for respective power levels of data packets transmitted by the DUT to settle at the desired nominal value for transmit signal testing. In accordance with exemplary embodiments, signals transmitted by the DUT during receive signal testing, e.g., as acknowledgement data packets, are transmitted at the nominal value for transmit signal testing, thereby allowing sufficient time for individual data packet signal power levels to settle and remain consistent at the nominal value by the time receive signal testing is completed and transmit signal testing is to begin.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: April 7, 2015
    Assignee: Litepoint Corporation
    Inventors: Christian Volf Olgaard, Ruizu Wang, Guang Shi
  • Publication number: 20150095733
    Abstract: An apparatus comprising a plurality of devices connected in series with one another, each of the devices comprising a test enable pin for receiving a test enable signal that indicates enablement of a test mode, and a test output pin for outputting a test output signal in the test mode, and a controller coupled to the devices and comprising an additional test output pin for outputting a test channel output signal, wherein a failure of at least one of the test output signals and the test channel output signal indicates the existence of one or more potential defects associated with the plurality of devices and the controller.
    Type: Application
    Filed: September 5, 2014
    Publication date: April 2, 2015
    Inventors: Hong Beom Pyeon, Young-Goan Kim
  • Patent number: 8990649
    Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8990650
    Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8990651
    Abstract: Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: March 24, 2015
    Assignee: Tabula, Inc.
    Inventors: Marc Miller, Steven Teig, Brad Hutchings
  • Patent number: 8977921
    Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: March 10, 2015
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Hong Ho, Daniel Smathers
  • Publication number: 20150067429
    Abstract: A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Randall C. Gray, Christopher B. Lesher
  • Publication number: 20150067430
    Abstract: A The semiconductor integrated circuit includes a test input/output port including test pads; an internal input interface configured to generate an internal clock, an internal address, an internal command, internal data and temporary storage data in response to external signals through the test input/output port; and an error detection block configured to determine whether the internal data and the temporary storage data are the same, and output a result through one test pad of the port. The internal input interface includes a data input/output block which generates the internal data and the data input/output block includes a temporary storage part which stores the internal data as the temporary storage data, a data output part which receives the temporary storage data, and a data input part which receives an output of the data output part and outputs it as the internal data.
    Type: Application
    Filed: January 29, 2014
    Publication date: March 5, 2015
    Applicant: SK hynix Inc.
    Inventor: Dong Uk LEE
  • Patent number: 8972811
    Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Sik Kang, Jae-Goo Lee
  • Publication number: 20150058691
    Abstract: A method for testing a data packet signal transceiver device under test (DUT) that minimizes time lost due to waiting for respective power levels of data packets transmitted by the DUT to settle at the desired nominal value for transmit signal testing. In accordance with exemplary embodiments, signals transmitted by the DUT during receive signal testing, e.g., as acknowledgement data packets, are transmitted at the nominal value for transmit signal testing, thereby allowing sufficient time for individual data packet signal power levels to settle and remain consistent at the nominal value by the time receive signal testing is completed and transmit signal testing is to begin.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Applicant: LITEPOINT CORPORATION
    Inventors: Christian Volf OLGAARD, Ruizu WANG, Guang SHI
  • Patent number: 8943457
    Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: Amit Dinesh Sanghani, Punit Kishore
  • Patent number: 8930782
    Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a layout-aware diagnosis method. Based on the suspect information, potential root causes for the plurality of failing dies, and suspect feature weights and total feature weights for each of the potential root causes may then be determined. Next, the probability information of observing a particular suspect that is related to a particular root cause may be extracted. Finally, an expectation-maximization analysis may be conducted for generating the root cause distribution information based on the probability information and the suspect information. Heuristic information may be used to prevent the analysis from over-fitting.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: January 6, 2015
    Assignee: Mentor Graphics Corporation
    Inventor: Robert Brady Benware
  • Patent number: 8918685
    Abstract: This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Gyun Yang, Hyung-Dong Lee, Yong-Kee Kwon, Young-Suk Moon, Hong-Sik Kim
  • Patent number: 8914688
    Abstract: In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: George M. Belansek, Kevin W. Gorman, Kiran K. Narayan, Krishnendu Mondal, Michael R. Ouellette
  • Publication number: 20140365841
    Abstract: A signal processing system includes a module under test, an oscillation signal generator, a translational filter, and a testing module. The module under test has a signal input end. The oscillation signal generator generates an oscillation signal. The translational filter includes a mixer controlled by the oscillation signals. The mixer has a high-frequency side and a low-frequency side. The high-frequency side is coupled to the signal input end of the module under test. The testing module is coupled to the low-frequency side of the mixer. When the signal processing system is in a testing mode, the testing module provides a testing signal to the low-frequency side, so as to generate a high-frequency testing signal at the high-frequency side of the mixer.
    Type: Application
    Filed: May 9, 2014
    Publication date: December 11, 2014
    Applicant: MStar Semiconductor, Inc.
    Inventors: Shih-Chieh Yen, Chih-Ming Hung
  • Patent number: 8910003
    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8904250
    Abstract: Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: December 2, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Francesco Falanga, Victor Tsai
  • Patent number: 8880969
    Abstract: The present invention provides a switching converter with pulse skipping mode. The switching converter comprises a switching circuit having at least one switch, a controller and a feedback circuit. The controller comprises an error amplifying circuit, a logic circuit, a ramp signal generator and a pulse skipping circuit. The error amplifying circuit generates a compensation signal based on comparing the feedback signal with a reference signal. The logic circuit generates a control signal to control the ON and OFF switching of the at least one switch based on the compensation signal. The ramp signal generator generates a ramp signal. The pulse skipping circuit generates a pulse skipping signal based on the compensation signal, the ramp signal and a threshold voltage. The logic circuit skips one or more switching pulses of the control signal in accordance with the pulse skipping signal.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: November 4, 2014
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventor: Xiaoyu Xi
  • Patent number: 8872531
    Abstract: A semiconductor device and a test apparatus including the same, the semiconductor device including a command distributor receiving a serial command that is synchronized with a first clock signal and converting the serial command into a parallel command, a command decoder receiving the parallel command and generating a pattern sequence based on the parallel command, and a signal generator receiving the pattern sequence and generating operating signals synchronized with a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: October 28, 2014
    Assignees: Samsung Electronics Co., Ltd., Postech Academy Industry Foundation
    Inventors: Ki-jae Song, Ung-jin Jang, Jun-young Park, Sung-gu Lee, Hong-seok Yeon
  • Patent number: 8862949
    Abstract: Embodiments relate to reliably storing information in a sensor or other device. In an embodiment, information storage circuitry comprises independent, redundant memory portions and error detection circuitry. The circuit can operate in cooperation with a memory writing procedure that utilizes a validity bit and sequentially writes to one or the other of the redundant memory portions such that at least one of the memory portions has data that is valid and can be recognized as such.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mihai-Alexandru Ionescu, Razvan-Catalin Mialtu, Radu Mihaescu
  • Patent number: 8839056
    Abstract: Systems, methods, and devices related to testing receive equipment. A test signal generator is coupled to both a receiver and an antenna. The receiver is also coupled to the antenna and a test signal verifier. A test signal is synthesized at the generator and is routed to the receiver. Once the verifier verifies that the test signal was received by the receiver, this ensures that the equipment coupled to the receiver, as well as the receiver itself, is in operating condition. Switches or other means of routing the test signal between the different components of the system can also be present.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: September 16, 2014
    Inventor: James Francis Harvey
  • Patent number: 8829940
    Abstract: The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test data output (18); placing a first die on the carrier, the first die having a test access port (100c) comprising a primary test data input (142), a secondary test data input (144) and a test data output (152), the test access port being controlled by a test access port controller (110); communicatively coupling the secondary test data input (144) of the first die to the device-level test data input (12), and the test data output (152) of the first die to the device-level test data output (18); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (144); testing the first die, said testing including providing the secondary test data input (144) of the first die with test instructions through the device-
    Type: Grant
    Filed: September 26, 2009
    Date of Patent: September 9, 2014
    Assignee: NXP, B.V.
    Inventors: Fransciscus Geradus Marie de Jong, Alexander Sebastian Biewenga
  • Patent number: 8832499
    Abstract: Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that define a configuration of the electronic device, circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests, and a shadow memory that includes values corresponding to the flagged hardware registers. The circuitry is further operable to access a value in shadow memory that corresponds to a flagged hardware register, responsive to receiving a request from an external device to access the flagged hardware register.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: September 9, 2014
    Assignee: LSI Corporation
    Inventors: Eugene Saghi, Richard Solomon
  • Patent number: 8825433
    Abstract: A method and system is provided for automatically generating valid at speed structural test (ASST) test groups. The method includes loading a netlist for an integrated circuit into a processor. The method further includes determining a plurality of clock domain crossings between a plurality of clock domains within the integrated circuit. The method further includes generating a first test group. The method further includes adding a first clock domain of the plurality of clock domains to the first test group. The method further includes adding a second clock domain of the plurality of clock domains to the first test group when the second clock domain does not have a clock domain crossing into the first clock domain.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Konda R. Baalaji, Malede W. Berhanu, Vikram Iyengar, Douglas C. Pricer
  • Patent number: 8826086
    Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: September 2, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
  • Patent number: 8826091
    Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: September 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8819511
    Abstract: Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 26, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Angel Socarras
  • Patent number: 8819510
    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: August 26, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8812936
    Abstract: A method includes receiving a request to read data at a data storage device from an external device. In response to determining that the data is in a first memory of the data storage device, a first read operation is initiated to read the data from the first memory and a response is sent to the external device. The response indicates an error correction code (ECC) error. A read latency of the first read operation exceeds a reply time period corresponding to the request. The response is sent prior to completion of the first read operation and within reply time period.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: August 19, 2014
    Assignee: Sandisk Technologies Inc.
    Inventor: Mordechai Blaunstein
  • Patent number: 8813019
    Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: August 19, 2014
    Assignee: NVIDIA Corporation
    Inventors: Avinash Rath, Sanjith Sleeba, Ashish Kumar
  • Publication number: 20140229783
    Abstract: A printed circuit board, an in-circuit test structure and a method for producing the in-circuit test structure thereof are disclosed. The in-circuit test structure comprises a via and a test pad. The via passes through the printed circuit board for communicating with an electrical device to be tested on the printed circuit board. The test pad is formed on an upper surface of the printed circuit board and covering the via, wherein a center of the via deviates from a center of the test pad. In the in-circuit test, the accuracy of the test data can be improved by means of the in-circuit test structure provided by the present invention, and thus the reliability of the test result is ensured. Also, the test efficiency of the in-circuit test is improved.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 14, 2014
    Applicant: NVIDIA Corporation
    Inventors: Jinchai (Ivy) QIN, Bing AI
  • Patent number: 8803716
    Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: August 12, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Ravindranath Ramalingaiah Munnan, Raghu Ravindran, Ravi Shekhar