Device Response Compared To Input Pattern Patents (Class 714/735)
  • Patent number: 10303566
    Abstract: An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 28, 2019
    Assignee: ARM Limited
    Inventors: Emre Özer, Balaji Venu, Xabier Iturbe, Antony John Penton
  • Patent number: 10126979
    Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit (EU) of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes compressing data at the EU. The method further includes encoding the compressed data at the EU. The method further includes generating control data for decoding the encoded data at the EU. The method further includes generating metadata corresponding to the compressed data at the EU. The metadata further includes the control data. The method further includes directing storage of the encoded data and the metadata in the DRAM.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: November 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Jeffrey Chu
  • Patent number: 9448942
    Abstract: A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 20, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William C. Moyer, Jeffrey W. Scott
  • Patent number: 9354978
    Abstract: A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: May 31, 2016
    Assignee: Dell Products L.P.
    Inventor: Bi-Chong Wang
  • Patent number: 9262303
    Abstract: A simulation system enables comparison of a realized physical implementation against the simulation models that produce them, thereby detecting differences between an initial, logical design and the resulting physical embodiment. Errors introduced by an initial design, faulty Intellectual Property blocks, faulty programmable logic device silicon, faulty synthesis algorithms and software, and/or faulty place and route algorithms and software may be detected. As a result, the simulation system reflects both the accuracy of the actual implemented device with the capacity and performance of a purpose built hardware-assisted solution.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: February 16, 2016
    Assignee: ALTERA CORPORATION
    Inventors: Christopher A. Schalick, Roderick B. Sullivan, Jr., Elliot H. Mednick, Matthew D. Kopser
  • Patent number: 9235425
    Abstract: A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: January 12, 2016
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Heiko Kalte
  • Publication number: 20150135030
    Abstract: Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.
    Type: Application
    Filed: August 18, 2014
    Publication date: May 14, 2015
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventors: Wei Zou, Wu-Tung Cheng, Huaxing Tang
  • Publication number: 20150121159
    Abstract: There is provided a semiconductor integrated circuit, including a test circuit, a plurality of signal cells, a power supply cell, and a control circuit. The test circuit performs a predetermined test on a test target circuit. A plurality of signal cells input an input signal into the test circuit and the test target circuit. The power supply cell supplies power to some of the plurality of signal cells in the test. The control circuit controls a value of the input signal from signal cells that include signal cells to which the power is not supplied and that are not used in the test, to be a predetermined value.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 30, 2015
    Inventors: Keita Izumi, Katsumi Takaoka, Toshiyuki Kouchiyama, Syunsuke Hamashima, Kouichirou Ono
  • Patent number: 9021325
    Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 28, 2015
    Assignee: LSI Corporation
    Inventors: Coralyn S. Gauvin, Gabriel L. Romero
  • Patent number: 9003249
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: April 7, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8996936
    Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: March 31, 2015
    Assignee: Sandisk Technologies Inc.
    Inventor: Saravanakumar Sevugapandian
  • Patent number: 8943377
    Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael W. Harper, Mack W. Riley
  • Patent number: 8914694
    Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: December 16, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
  • Patent number: 8896437
    Abstract: A system includes at least one sensor and an equipment health monitoring (EHM) unit. The at least one sensor is configured to measure one or more characteristics of an asset, where the asset includes a piece of equipment. The EHM unit includes at least one sensor interface configured to receive at least one input signal associated with the asset from the sensor(s). The EHM unit also includes at least one processing unit operable to be pre-configured to identify a specified fault in the asset using the input signals and an asset-specific model that includes a combination of standard subsystem models. The EHM unit further includes at least one output interface configured to provide an indicator identifying the fault. The standard subsystem models could include standardized fault models configured to identify faults for standard assets.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: November 25, 2014
    Assignee: Honeywell International Inc.
    Inventor: Rajat Sadana
  • Patent number: 8880967
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8862938
    Abstract: A system includes at least one monitored device collect data detect and detect an error in the data, a central server, and at least one local server communicatively coupled to the monitored device and the central server. The local server is configured to receive the data and an indication of the error detected from the monitored device, determine a solution for use in resolving the error, transmit instructions to perform the solution to the monitored device, and transmit the error and the solution to the central server for storage.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: October 14, 2014
    Assignee: General Electric Company
    Inventor: Manyphay Souvannarath
  • Patent number: 8843794
    Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Christopher J. Nelson, Tak M. Mak, David J. Zimmerman, Pete D. Vogt
  • Patent number: 8832513
    Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert W. Berry, Anand Haridass, Prasanna Jayaraman
  • Patent number: 8826092
    Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert W. Berry, Jr., Anand Haridass, Prasanna Jayaraman
  • Patent number: 8812918
    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: August 19, 2014
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
  • Patent number: 8799713
    Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Swathi Gangasani, Srinivasulu Alampally, Prohor Chowdhury, Srinivasa B S Chakravarthy, Padmini Sampath, Rubin Ajit Parekhji
  • Publication number: 20140195870
    Abstract: A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion under test, a comparator and a comparison result recorder. The circuit portion under test receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. The comparator outputs comparison results according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The system receives at least a portion of test signals and at least a portion of ideal response signals in a dynamically configurable time-interleaved manner via one or more physical channels from a test equipment.
    Type: Application
    Filed: February 16, 2014
    Publication date: July 10, 2014
    Inventor: SSU-PIN MA
  • Patent number: 8775881
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 8756469
    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 17, 2014
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
  • Patent number: 8718123
    Abstract: A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: May 6, 2014
    Assignee: Advantest Corporation
    Inventors: Kazumichi Yoshiba, Hiromi Oshima
  • Patent number: 8713391
    Abstract: A system for testing an integrated circuit, in which the system includes a deserializer, a frame sync module, and a diagnostic module. The deserializer is external to the integrated circuit and is configured to receive messages in a serial data format, wherein the messages include test results associated with the integrated circuit, and deserialize the messages into data frames. The frame sync module is configured to provide control code based on the data frames, wherein the control code includes, in a digital format, status information associated with the messages deserialized into the data frames. The diagnostic module is configured to generate, based on the control code, diagnostic data associated with states of the integrated circuit.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: April 29, 2014
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Ho, Daniel Smathers
  • Publication number: 20140115409
    Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: APPLIED MICRO CIRCUITS CORPORATION
    Inventor: Glen Miller
  • Patent number: 8707113
    Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: April 22, 2014
    Assignee: Agilent Technologies, Inc.
    Inventors: Douglas Manley, Randy A. Coverstone
  • Patent number: 8700963
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: April 15, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8638792
    Abstract: A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: January 28, 2014
    Assignee: Synopsys, Inc.
    Inventor: Robert Erickson
  • Patent number: 8607109
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Publication number: 20130326299
    Abstract: A server stores multiple configuration data. A tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory, to supply a power supply voltage to a DUT, to transmit a signal to the DUT, and to receive a signal from the DUT. An information technology equipment is configured such that, (i) when the test system is set up, the information technology equipment acquires the configuration data from the server according to the user's input, and writes the configuration data to the nonvolatile memory. Furthermore, the information technology equipment is configured such that, (ii) when the DUT is tested, the information technology equipment executes a test program so as to control the tester hardware, and to process data acquired by the tester hardware.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 5, 2013
    Inventor: Hiromi Oshima
  • Publication number: 20130326300
    Abstract: A termination circuit includes a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function; and an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance.
    Type: Application
    Filed: August 7, 2013
    Publication date: December 5, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Toshihide Suzuki, Yoichi Kawano
  • Patent number: 8595576
    Abstract: Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 26, 2013
    Assignee: LSI Corporation
    Inventor: Johnson Yen
  • Patent number: 8595574
    Abstract: Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: November 26, 2013
    Assignee: Mentor Graphics Corporation
    Inventors: Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg
  • Patent number: 8572446
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: October 29, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8572448
    Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: October 29, 2013
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Hong Ho, Daniel Smathers
  • Patent number: 8549136
    Abstract: For the operation of at least one non-safety-critical application process and at least one safety-critical application process, the invention proposes a data processing and transmission system with a data transmission network, at least one non-safety-related network element linked to the non-safety-critical application process and connected to the network, and with at least one safety-related network element linked to the safety-critical application process, as well as with at least one master unit connected to the network, and a server unit connected to the network separately from the master unit, wherein the safety-related server unit controls the at least one safety-critical application process, specifically by processing safety-relevant data necessary for controlling the safety-critical application process and by organizing the transmission of the safety-relevant data over the network by means of at least one of the network elements and/or the master unit.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: October 1, 2013
    Assignee: Phoenix Contact GmbH & Co. KG
    Inventors: Johannes Kalhoff, Rahlves Lutz, Steffen Horn
  • Patent number: 8533169
    Abstract: Writing data in a distributed database having a plurality of nodes is disclosed. Writing includes receiving a write request at a node, wherein the write request is associated with one or more operations to define an atomic transaction and performing the atomic transaction based on the request. The atomic transaction includes writing to a first version of the database in the node and writing to an entity representative of a state of the first version of the database.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: September 10, 2013
    Assignee: Infoblox Inc.
    Inventors: Stuart Bailey, Ivan W. Pulleyn, Srinath Gutti
  • Patent number: 8531322
    Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: September 10, 2013
    Assignee: Mediatek Singapore Pte. Ltd.
    Inventors: Changhua Cao, Xiaochuan Guo, Yen-Horng Chen, Caiyi Wang
  • Publication number: 20130227366
    Abstract: Embodiments of the invention relate to the conversion and execution of functional tests. In one embodiment, a current test step of a manual functional test is executed. The test includes a set of test steps each including at least one action and one target of the action. The test is associated with an application that includes a plurality of objects to be tested. At least two of the objects are determined to be associated with the target of the test step. A user is prompted to provide a selection of one of the at least objects for association with the target of the test step. A new test step is generated. The new test step associates the object selected by the user with the target of the current test step. The new test step is designated for automatic execution in place of the current test step for subsequent executions thereof.
    Type: Application
    Filed: August 20, 2012
    Publication date: August 29, 2013
    Applicant: International Business Machines Corporation
    Inventors: Tessa A. LAU, Jalal U. Mahmud, Pablo Pedemonte
  • Publication number: 20130227367
    Abstract: A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus.
    Type: Application
    Filed: January 16, 2013
    Publication date: August 29, 2013
    Inventors: Allen J. Czamara, Ed Paulsen, Lev Alperovich
  • Patent number: 8522099
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 8515416
    Abstract: In a radio device such as a receiver or transceiver, a test operation can be performed to determine performance. A received signal can be processed to obtain demodulated samples, which can be provided to a logic to perform a logic operation on the samples to generate a logic output. A storage such as a counter or other mechanism is coupled to the logic to store a count of a number of the logic outputs having an error.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Silicon Laboratories Inc
    Inventor: Hendricus De Ruijter
  • Patent number: 8510613
    Abstract: A method includes temporarily storing write-data to be written into non-volatile memory cells, respectively, the memory cells being divided into cell groups, performing a first operation including write-phases performed in series and on an associated cell group and including applying a write-voltage to the memory cells belonging to the associated cell group in response to an associated write-data to be written into the memory cells belonging to the cell groups, and performing a second operation after the first operation is completed, which includes read-phases performed in series and on an associated cell group and including applying a first read-voltage to the memory cell or cells belonging to the associated one of the cell groups to produce first read-data therefrom, and comparing the first read-data with the write-data to be written into the memory cells belonging to the associated cell groups to produce comparison data.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: August 13, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Akiyoshi Seko
  • Patent number: 8479048
    Abstract: In the system management server, an information processing apparatus that is an event-information acquisition target is registered as a monitored apparatus in configuration information; event information that complies with a rule stored in advance is identified from among a plurality of pieces of event information stored in the system management server; a server apparatus for a network service related to the event information is identified; and a message is displayed which indicates that the cause of the event that occurred in a client information processing apparatus which has generated event information is an event related to the network service, which occurred in the server apparatus.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: July 2, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Morimura, Takayuki Nagai, Kiminori Sugauchi, Takaki Kuroda, Yoshihiro Arato
  • Patent number: 8458539
    Abstract: An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, comprises a mask register an arm register. A comparator compares debug data with contents of the mask register and the arm register to determine a comparison result to be stored in one or more bit positions of the vector register. The apparatus further comprises a triggering logic unit to determine whether or not to trigger a fire event based on the vector registers.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Daniel Skaba, Michael Israeli, Itai Samoelov, Julius Mandelblat
  • Patent number: 8453024
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: May 28, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8418013
    Abstract: The invention relates to automated hardware in the loop testing. A method of automated diagnostic testing is described as monitoring, modifying, overwriting, providing and/or providing read-only access to input data given to a tested application and output data provided by a tested application to compare a desired relationship between input data and output data. A preferred system includes a communication network with a preferred method including a controller area network to associate a test controlling system to a tested application. An automated diagnostic testing system comprises a test controlling system operably coupled to a tested application.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: April 9, 2013
    Assignee: Deere & Company
    Inventors: Bryan D. Sulzer, Scott J. Breiner
  • Patent number: 8418007
    Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: April 9, 2013
    Assignee: Mentor Graphics Corporation
    Inventors: Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer