Abstract: A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.

Abstract: A test device and method with built-in self-test logic and a communication device. The test device includes at least one generator and at least one checker which are disposed between a physical layer and a medium access control layer. The at least one generator is configured to generate a protocol pattern to form a data path between the physical layer and the medium access control layer, and generate different pseudo random bit sequence patterns in the data path. The at least one checker is configured to test a data stream in the physical layer and/or the medium access control layer according to the pseudo random bit sequence patterns, thereby locating a fault position.

Abstract: According to some embodiments, a method in a wireless device comprises obtaining a set of information bits for wireless transmission and dividing the set of information bits into one or more subsets of information bits. For each subset, generating extra cyclic redundancy check (CRC) bits using a CRC polynomial capable of generating N CRC bits. The extra CRC bits for each subset comprise less than N CRC bits. The method further comprises: generating a final set of N or less CRC bits for the set of information bits using the CRC polynomial; generating a set of coded bits by encoding the set of information bits for wireless transmission, together with the extra CRC bits and the final set of CRC bits, using a polar encoder; and transmitting the set of coded bits using a wireless transmitter.

Abstract: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a memory cell array including memory blocks, a local parity memory block, and a register block. The memory blocks respectively store pieces of partial local data in response to a plurality of column selection signals, or a first partial global parity in response to a global parity column selection signal. The local parity memory block stores local parities of local data in response to the plurality of column selection signals, or a second partial global parity in response to the global parity column selection signal. The register block generates a global parity including the first partial global parities and the second partial global parity. Each piece of local data includes the partial local data, and the global parity is a parity of the pieces of local data and the local parities.

Abstract: Identification of changes in functional and runtime behavior of a system during maintenance cycles. The traditional methods provide for viewing the problem of change identification de-coupled from system design, thus making the process further human dependent and increasing the time and probability of errors. Embodiment of the present disclosure provide for identification of changes in the functional behavior and the runtime behavior of the system by acquiring, a design comprising of structures and behaviors of the system, generating a design model and a set of implementation codes based upon the design, updating the set of implementation codes with log statements, constructing a design model based upon log files, constructing an operations model based upon the design model and comparing the operations model and a design table, to identify changes in the functional behavior and the runtime behavior of the system using an operations verification component.

Abstract: Disclosed herein are example embodiments of methods, apparatus, and systems for transactors configured for use in a hardware emulation environment and designed to adapt to speed changes dynamically at runtime in addition to providing dynamic port mapping. Among the embodiments disclosed herein is an emulation system comprising one or more configurable hardware components (e.g., configurable logic blocks) configured to implement a mutable port group transactor in communication with a design under test being emulated by the emulation system. The emulation system can further comprise a host computer in communication with the emulator and configured to provide configuration commands to the emulator that alter the mutable port group transactor from a first configuration to a second configuration.

Abstract: An apparatus for core repair includes a failure analysis and recovery (“FAR”) probe that accesses a core of a processor and units of the core over a low-level communication bus while the core is operational after a failure notification. The FAR probe compares operational data of the core versus vital product data (“VPD”) while the core is running tests and a thermal, power, functional (“TPF”) workload to determine if the core is in a degraded state and runs tests to identify a failure after determining that the core is in a degraded state. The FAR probe adjusts parameters of the core in response to identifying a failure of the core and re-evaluates the core to determine if the core is functional. The FAR probe returns the core to service after determining that the core is functional. The FAR probe operates independent of other processor cores while the cores are operational.

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

Abstract: A power supply device includes a voltage adjusting unit, an A/D converter, a determination unit, and a supply unit configured to supply a voltage. The A/D converter includes an A/D conversion circuit, and a selector that connects any one of a plurality of input ports to the A/D conversion circuit. The input ports include load ports, a first diagnostic port, and a second diagnostic port, the supply unit supplies a first voltage value to the first diagnostic port and supplies a second voltage value to the second diagnostic port, and the determination unit determines abnormality of the A/D converter on the basis of conversion results by the A/D conversion circuit when the first diagnostic port and the A/D conversion circuit are connected together and conversion results by the A/D conversion circuit when the second diagnostic port and the A/D conversion circuit are connected together.

Abstract: An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit (EU) of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes compressing data at the EU. The method further includes encoding the compressed data at the EU. The method further includes generating control data for decoding the encoded data at the EU. The method further includes generating metadata corresponding to the compressed data at the EU. The metadata further includes the control data. The method further includes directing storage of the encoded data and the metadata in the DRAM.

Abstract: A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

Abstract: A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.

Abstract: A simulation system enables comparison of a realized physical implementation against the simulation models that produce them, thereby detecting differences between an initial, logical design and the resulting physical embodiment. Errors introduced by an initial design, faulty Intellectual Property blocks, faulty programmable logic device silicon, faulty synthesis algorithms and software, and/or faulty place and route algorithms and software may be detected. As a result, the simulation system reflects both the accuracy of the actual implemented device with the capacity and performance of a purpose built hardware-assisted solution.

Abstract: A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.

Abstract: Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.

Abstract: There is provided a semiconductor integrated circuit, including a test circuit, a plurality of signal cells, a power supply cell, and a control circuit. The test circuit performs a predetermined test on a test target circuit. A plurality of signal cells input an input signal into the test circuit and the test target circuit. The power supply cell supplies power to some of the plurality of signal cells in the test. The control circuit controls a value of the input signal from signal cells that include signal cells to which the power is not supplied and that are not used in the test, to be a predetermined value.

Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: A system includes at least one sensor and an equipment health monitoring (EHM) unit. The at least one sensor is configured to measure one or more characteristics of an asset, where the asset includes a piece of equipment. The EHM unit includes at least one sensor interface configured to receive at least one input signal associated with the asset from the sensor(s). The EHM unit also includes at least one processing unit operable to be pre-configured to identify a specified fault in the asset using the input signals and an asset-specific model that includes a combination of standard subsystem models. The EHM unit further includes at least one output interface configured to provide an indicator identifying the fault. The standard subsystem models could include standardized fault models configured to identify faults for standard assets.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A system includes at least one monitored device collect data detect and detect an error in the data, a central server, and at least one local server communicatively coupled to the monitored device and the central server. The local server is configured to receive the data and an indication of the error detected from the monitored device, determine a solution for use in resolving the error, transmit instructions to perform the solution to the monitored device, and transmit the error and the solution to the central server for storage.

Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.

Abstract: A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion under test, a comparator and a comparison result recorder. The circuit portion under test receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. The comparator outputs comparison results according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The system receives at least a portion of test signals and at least a portion of ideal response signals in a dynamically configurable time-interleaved manner via one or more physical channels from a test equipment.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired.

Abstract: A system for testing an integrated circuit, in which the system includes a deserializer, a frame sync module, and a diagnostic module. The deserializer is external to the integrated circuit and is configured to receive messages in a serial data format, wherein the messages include test results associated with the integrated circuit, and deserialize the messages into data frames. The frame sync module is configured to provide control code based on the data frames, wherein the control code includes, in a digital format, status information associated with the messages deserialized into the data frames. The diagnostic module is configured to generate, based on the control code, diagnostic data associated with states of the integrated circuit.

Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.

Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A server stores multiple configuration data. A tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory, to supply a power supply voltage to a DUT, to transmit a signal to the DUT, and to receive a signal from the DUT. An information technology equipment is configured such that, (i) when the test system is set up, the information technology equipment acquires the configuration data from the server according to the user's input, and writes the configuration data to the nonvolatile memory. Furthermore, the information technology equipment is configured such that, (ii) when the DUT is tested, the information technology equipment executes a test program so as to control the tester hardware, and to process data acquired by the tester hardware.

Abstract: A termination circuit includes a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function; and an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance.

Abstract: Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory.

Abstract: Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.

Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: For the operation of at least one non-safety-critical application process and at least one safety-critical application process, the invention proposes a data processing and transmission system with a data transmission network, at least one non-safety-related network element linked to the non-safety-critical application process and connected to the network, and with at least one safety-related network element linked to the safety-critical application process, as well as with at least one master unit connected to the network, and a server unit connected to the network separately from the master unit, wherein the safety-related server unit controls the at least one safety-critical application process, specifically by processing safety-relevant data necessary for controlling the safety-critical application process and by organizing the transmission of the safety-relevant data over the network by means of at least one of the network elements and/or the master unit.

Abstract: Writing data in a distributed database having a plurality of nodes is disclosed. Writing includes receiving a write request at a node, wherein the write request is associated with one or more operations to define an atomic transaction and performing the atomic transaction based on the request. The atomic transaction includes writing to a first version of the database in the node and writing to an entity representative of a state of the first version of the database.

Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

Abstract: Embodiments of the invention relate to the conversion and execution of functional tests. In one embodiment, a current test step of a manual functional test is executed. The test includes a set of test steps each including at least one action and one target of the action. The test is associated with an application that includes a plurality of objects to be tested. At least two of the objects are determined to be associated with the target of the test step. A user is prompted to provide a selection of one of the at least objects for association with the target of the test step. A new test step is generated. The new test step associates the object selected by the user with the target of the current test step. The new test step is designated for automatic execution in place of the current test step for subsequent executions thereof.