Abstract: A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate test data. If the received bit is “0,” the test data bits are all “0,” and if the received bit is “1,” the test data bits are all “1.” The test data bits are applied to the ECC encoder that is used in normal operation. The ECC encoder is designed so that it generates ECC bits that have the same logic level as the test data bits. The test data bits and ECC bits are then written to a memory array and subsequently read. During the test mode, a logic circuit determines if the read data and check bits are all either “0” or “1” and outputs a corresponding test result bit from the memory device.

Abstract: An embodiment is a circuit including 2n?1 first comparators to generate a first result by comparing data from at least two of 2n memory cells to which test pattern data are written. 2n?1 first switching circuits provide the first result or a disable signal responsive to a first switching signal. And 2n?2 second comparators generate a second result by comparing signals output from some of the 2n?1 first switching circuits. N may be a natural number greater than or equal to three.

Abstract: An apparatus and associated methodology are provided to generate system test libraries for solution testing involving heterogeneous devices from different vendors. A unified user interface employs received information to execute the tests based on provided device and network topology libraries, generating the system library to perform the required end-to-end system testing. The unified user interface and the library generation mechanism provide a layer of abstraction avoiding complexities of the system configuration commands native to disparate devices.

Abstract: An integrated scannable interface for testing memory. The interface includes a selection device for selecting a signal from at least two input signals responsive to an activation signal, a first storage device coupled to the output of the selection device for storing the signal responsive to a first enable signal and generating an output signal for the memory. The first storage device is connected at the input node of the memory, and a second storage device is coupled at its input to the first storage device for storing the output signal responsive to a second enable signal and generating a test signal for testing the memory. The output signal is observed for debugging faults between the integrated scannable interface and the memory and for debugging faults between the first and second storage devices.

Abstract: A method of recreating instructions and data traces in a processor can include the step of fetching an instruction from an executable program in an order corresponding to sequential program counter (PC) values, obtaining a destination register from the fetched instruction and updating the destination register in a data structure with a value from a collected destination register corresponding to the PC value. The steps above can be repeated until all desired PC values and destination values are obtained.

Abstract: A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the user control of the pattern generator to compensate for tool and/or device under test latency timing issues. Inputs may be combined and processed into one contiguous pattern of vectors which are definable by the user.

Abstract: An integrated circuit includes a first bus and at least one array of embedded memories. Each array includes a second bus such as a bidirectional bus coupled to the embedded memories and to the first bus such that test vectors in the form of data words can be written from the first bus to selected embedded memories in the array. Also included is a built-in-self-test (BIST) circuit operable to compare data words on the first bus to data words read back from the selected embedded memories through the bidirectional bus.

Abstract: An apparatus for automatic testing of a PS/2 interface includes a micro controller unit, a PS/2 port, and a plurality of LEDs. The micro controller unit is coupled with both a data pin and a clock pin of the PS/2 interface. The LEDs coupled to the micro controller unit simulate functions of a keyboard. A related method for testing the PS/2 interface is also provided.

Abstract: A method and system for evaluating performance of a device by on-chip determination of BER may include establishing and generating PRBS test packets in a closed communication path internally within a physical layer device (PLD) and a remote PLD. A BER for the PLD may be determined from within the PLD based on a comparison of at least a portion of the generated test packets with at least a portion of the generated test packets transmitted over the closed communication path received by the PLD via the closed communication path from the remote PLD. A transmit path of the PLD may be internally coupled to a receive path of the PLD, and a receive path of the PLD may be internally coupled to a transmit path of the PLD. The PLD may be internally configured to operate in an internal optical loopback mode or an internal electrical loopback mode.

Abstract: A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test multiple transistors. A testing method is disclosed in which a supply voltage is applied to the waveform generator to produce pulses that are applied to the gate of a transistor to be tested. A bias voltage is applied to the source and drain of the transistor to be tested, and the charge pumping current that is generated at the substrate is then measured. The process can be repeated at different bias voltage levels to obtain additional current measurements, indicating the maximum charge pumping current for the transistor that is being tested. The determined maximum charge pumping current can then be used for determining whether there is excessive 1/f noise in the device under test.

Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

Abstract: A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output from each programmable logic component to a fixed logic component, examining the outputs, and determining a validated output from among the outputs. An architecture for mitigating logic upsets includes an input, a plurality of programmable logic components, and a fixed logic component. The input is provided to each of the programmable logic components. Each programmable logic components includes an encryption algorithm and a first majority voting logic, and processes the respective input to determine a respective output. The fixed logic component includes a second majority voting logic. The fixed logic component receives each respective output from the programmable logic components, examines the outputs, and determines a validated output.

Abstract: A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift registers (LFSR). The generated patterns are implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.

Abstract: A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training sequence when the received data are in the training sequence, and shifting the alignment point by reflecting an addition or a removal of a skip symbol on the received data through each of the four lanes when the received data are not in the training sequence. Therefore, the byte skew of the PCI Express bus may be effectively compensated for despite the addition or the removal of the skip symbol.

Abstract: A modulated voltage signal modulated at a predetermined frequency f0 is supplied to an integrated circuit under test to be tested set at an arbitrary stationary point, and an observation signal containing information on power supply current flowing through the integrated circuit under test at the stationary point. Then, a determination signal from which DC component is removed is extracted from the observation signal and supplied to a determination device. The determination device compares the size of spectral component of the determination signal at the predetermined frequency f0 between each measurement point and determines that an error exists in the integrated circuit under test if a difference is a predetermined value or greater.

Abstract: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).

Abstract: A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.

Abstract: Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.

Abstract: The present invention relates to a built-in self test of a flash memory device in a data processing device, particularly a mobile terminal, comprising a flash-memory having a plurality of data blocks, a data block memory for temporarily storing a data block of said data blocks, a CPU and a test memory comprising a stored test program executable by the CPU, wherein the method comprises: a) fetching data from a first data block of said plurality of data blocks of the flash-memory; b) storing the fetched data temporarily in the data block memory; c) fetching a test pattern from the test memory, d) writing said test pattern into the first data block; e) reading back the test pattern that was written into the first data block; f) performing a data block test to see whether the first data block is corrupt or not by comparing the test pattern that was written into the first data block in step d) with the test pattern that was read back in step e) g) reporting the results of the data block test performed in step f);

Abstract: An integrated circuit package includes at least two electronic circuits. A first of the at least two electronic circuits includes a digital input and a digital output and a test mode control line for setting the first integrated circuit chip into a determined test mode. The digital input includes at least two parallel input paths and the digital output includes at least two parallel output paths. The at least two parallel input paths and at least two parallel output paths provide a corresponding number of internal paths by which the first electronic circuit and a second electronic circuit can be tested essentially simultaneously.

Abstract: An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.

Abstract: A test pattern generation circuit has multiple pseudo random number generation circuits and a clock control circuit. The pseudo random number generation circuits are provided corresponding to the respective signal lines in a bus wiring, and have predetermined first initial values, which take the same value. In response to first clock signals, the pseudo random number generation circuits generate pseudo random numbers including the first initial values as starting values. According to the value of a control signal, the clock control circuit determines the output-start timings of the first clock signals to be respectively provided to the multiple pseudo random number generation circuits.

Abstract: To verify an addition-function of a floating-point adder-subtractor in a processor, parameters such as the number of verification patterns of a verification program are set, a floating-point addition instruction to be verified is created, and operands used for this addition are created at random. The floating-point addition instruction thus created is emulated only by a fixed-point instruction and processed only by using the fixed-point execution element, thereby creating an expectation value. The floating-point addition instruction is computed by using the floating-point adder-subtractor to be verified, and the created expectation value is compared with the operation result. If they do not correspond to each other, the set number of operation patterns is checked. If the number has reached a prescribed value, the operation verification is terminated in the normal manner.

Abstract: A semiconductor device includes an output path; an input path; and a test signal generating circuit. The test signal generating circuit generates an input test data signal by changing at least one of an amplitude and a phase of an output test data signal which is generated from a test data in the semiconductor device and transferred on the output path, and supplies the input test data signal onto the input path. The output path and the input path are tested by using the output test data signal and the input test data signal, respectively.

Abstract: A method, system, and machine-readable medium for controlling access to data of a tape data storage medium are disclosed. In accordance with one embodiment, a method is provided which comprises conveying data access control metadata from a tape cartridge comprising a tape data storage medium to a host, receiving decrypted metadata from the host, comparing a checksum value determined utilizing the decrypted metadata with checksum data stored within the tape cartridge; and processing a request to access the tape data storage medium received from the host based upon a comparison of the checksum value and checksum data. In the described method embodiment, the data access control metadata comprises encrypted metadata corresponding to a data storage parameter, where data is stored within the tape data storage medium utilizing the data storage parameter and the decrypted metadata is generated by the host utilizing the encrypted metadata.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract: Disclosed is a system and method for testing electronic devices which uses a random pattern for testing electronic devices. In one embodiment there is communicated to a device under test (DUT) a test sequence causing the DUT to exercise certain parameters in a controlled pattern of operation. The test sequence is randomly created. In one embodiment this random creation is controlled by a random looping algorithm which controls both the order of and the magnitude of each parameter. Included, if desired, is the ability to selectively retransmit previously communicated test sequences.

Abstract: An apparatus which is tested includes a master logic unit and a slave logic unit. The testing method includes accessing a virtual slave logic unit by a test pattern which includes an address for accessing and an expected value of a waiting time, returning a response value from the virtual slave logic unit which is accessed by the address after lapse of the waiting time, and comparing the expected value and the response value.

Abstract: A test circuit for testing a command signal at a package level in a semiconductor device includes: a logic level determining unit for determining logic levels of a plurality of command flag signals in response to a plurality of internal command signals in a test mode; a storage unit for storing the plurality of command flag signals in response to a store control signal and outputting the plurality of command flag signals in series in response to an output control signal; and an output unit for driving an output signal of the storage unit to a data pad.

Abstract: A device (10) for validating a circuit (1) comprising at least one microprocessor (3) and a specialized unit (2) provided with registers includes a base (11) for receiving the circuit, a memory (4, 5) simulating an external memory with which the circuit is intended to cooperate and a computer (20) controlling the validation. The memory (4, 5) contains software for processing data received by the circuit and instructions for executing a validation sequence, making it possible to form a data flow representing a flow received by the circuit in normal operation, to compare data contained in registers of the circuit with theoretical values and to supply a signature representing a result of these comparisons.

Abstract: A semiconductor integrated circuit device includes a programmable circuit in which information is programmed, an information holding circuit which electrically holds information programmed in the programmable circuit, a compression circuit which compresses information held in the information holding circuit, an information output circuit which outputs expected value information, and a detection circuit which checks whether information held in the information holding circuit is destroyed or not. The detecting circuit compares expected value information of the information output circuit with compression information of the information compression circuit to check destruction of information held in the information holding circuit.

Abstract: An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.

Abstract: A shift amount measuring apparatus for measuring a phase shift amount of a signal under measurement which is input thereto includes a PLL circuit that generates a strobe signal which is synchronized with a reference signal, a CDR circuit that inputs, into the PLL circuit, a control signal which has a level determined in accordance with a difference in phase between the signal under measurement and the strobe signal, so as to achieve a predetermined difference in phase between the signal under measurement and the strobe signal, and a measuring circuit that, before and after the signal under measurement is phase-shifted, measures a value of the control signal when the predetermined difference in phase is achieved between the signal under measurement and the strobe signal, and calculates the phase shift amount of the signal under measurement based on a difference between the measured levels of the control signal.

Abstract: Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a transmitter uses the transmitter clock signals to transmit a write data strobe signal corresponding to the first and second digital signals to memory devices being tested. The transmitter is enabled by an enable signal generated by a third phase interpolator. By varying the timing of the enable signal, the third phase interpolator can vary the duration of preambles and postambles of respective write data strobe signals.

Abstract: A testing technique and apparatus are described for apply a test to a System Under Test (SUT) in one or more configurations of the SUT. The test can generate and store multiple output results that capture the behavior of the SUT in performing the test. Policy analysis logic applies a policy to the output results to generate an output verdict that reaches some conclusion regarding the outcome of the test. That is, the applied policy maps a subset of stored output results (and possibly input parameters) into the output verdict based on specified rules. A tester can apply different policies to investigate different aspects of the SUT's behavior.

Abstract: 64/66b encoding (IEEE 802.3ae Standard for 10 Gigabit Ethernet) is based on a self-synchronous scrambler which inherently duplicates errors occurring in the transmission line. An error carryover indicator ECI vector is used to correct duplicated errors crossing the codeword boundary and entering into the next codeword. The ECI vector is updated for each codeword C(i) to provide the position of the erroneous bit(s) carried over to the next codeword C(i+1). The codeword C(i+1) is corrected by XOR-ing it with the ECI vector.

Abstract: A semiconductor device having a plurality of circuits with the same configuration, wherein since expected values in the number corresponding to the number of circuits are not required, operation tests are effectively performed in a short time. The semiconductor device has first, second and third digital filters with the same configuration. To test these digital filters, comparison circuits comparing an output value and an expected value are individually provided per one digital filter. The digital filters and the comparison circuits are daisy-chained such that the output values of the first and second digital filters are input as the expected values of the comparison circuits corresponding to the second and third digital filters, respectively. When the same test signal is input to each digital filter from a built-in self test (BIST) controller, abnormal circuits can be detected based on comparison results of the comparison circuits.

Abstract: Test patterns for testing electrical circuits are generated by a MUX having its output operatively coupled to a Scan-In shift register and inputs receiving seed pattern signals, response signal from a response shift register, positive and negative signals from the Scan-In register. A control logic circuit provides control signals that enable the MUX to select appropriate input signals. The circuit arrangement enables relatively few seed patterns to generate relatively large number of test patterns. The seed patterns are a sub-set of a test pattern set preferably generated by software such as the Automatic Test Pattern Generator (ATPG). A method to generate the seed patterns is, also, provided.

Abstract: A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation. Since the disabled entries are not allocated to store memory data, the data stored in the entries at the time the cache is programmed to disable the entries may remain in the cache. In one specific implementation, the cache also provides for direct access to entries in response to direct access transactions.

Abstract: Apparatus and Method for Testing Circuit Units To Be Tested. According to one aspect, a test apparatus for testing circuit units to be tested, includes a nominal data production unit for production of a nominal data stream, a comparison device for comparison of an actual data stream which is emitted from the circuit unit to be tested as a function of the nominal data stream that is supplied with the nominal data stream; and a compression device for compression of an intermediate result signal which is emitted from the comparison device as a function of the comparison into a test result signal, with the intermediate result signal (108) which is emitted from the comparison device being temporarily stored in a buffer storage device with the intermediate result signal which is temporarily stored in a buffer storage device being read by means of a read unit.

Abstract: A semiconductor integrated circuit includes a pin section, internal circuits, an interface section, an expectation value generation circuit, a comparison circuit and a waveform generation circuit. In a first test mode, the expectation value generation circuit generates expectation values of operation signals to be generated by the interface section when first test signals having the same waveform are input via respective pins of the pin section, and the comparison circuit compares operation signals that are actually produced by the interface section with the respective expectation values and produces comparison results. In a second test mode, the waveform generation circuit supplies second test signals to the interface section, and the interface section outputs test output signals having the same waveform to the external system via respective pins of the pin section.

Abstract: A test apparatus implements a method for testing electronic devices that exhibit non-deterministic behavior. The test apparatus includes a high-speed buffer queue for storing data packets. The data packets arrive at one end of the queue and, as they exit at the other end, are compared against expect data packets stored in memory. If the data packet exiting the buffer queue corresponds to response signals generated by the device under test during a non-deterministic (e.g., idle) state, the expect data packet is not retrieved from memory and the comparison is not made.

Abstract: A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output (“I/O”) unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

Abstract: An alignment module receives a sequence of un-aligned data words, finds a frame alignment word, and aligns the data words based on the position of the frame alignment word in the un-aligned data words. Comparators compare segments of two consecutive un-aligned data words to a frame alignment word and generate a first logic signal when there is a match. A shift register and a counter are used to determine which comparator generates the first logic signal. The counter sends a count to a barrel shifter, which shifts the un-aligned data words according to the count to generate aligned data words.

Abstract: The present invention relates to a method and an universal module for testing functions of communication ports of a computer, including both parallel port and serial port. The module includes a logic control unit and connects to a communication port (a serial or a parallel port) for testing the open or short conditions of the ports through walk 1? and a walk 0? logic tests. The testing module not only can check the open condition of a parallel port, but also can check the open and short conditions of a parallel port and a serial port.

Abstract: The present invention provides an apparatus for testing a device (102) for storing data, which has a device for comparing actual data with set point data for individual storage areas and a device for supplying a comparison signal (106) for each storage area, which comparison signal (106) has a first state if the actual data is identical to the set point data, and a second state if the actual data is not identical to the set point data. The testing apparatus has a circuit board (100) on which the storage device (102) can be mounted, and a device (108) for comparing the states of the comparison signals at the pins of the storage device (102) which are assigned to the comparison signals (106), and for supplying a status signal (110) which, as a function of the state of the comparison signal, has a first state if the storage device (102) is operationally capable, and has a second state if the storage device (102) is defective.

Abstract: A system and method for processing tester information is provided having a system-under-test. A pattern is written to the system-under-test, and a pattern is read therefrom. The pattern written is then compared to the pattern read from the system-under-test. The signal from the comparison is processed, and the signal from the signal processing is then analyzed.

Abstract: Methods, apparatus, and systems are presented for communicating structured data in a system utilizing devices having different data processing capabilities. The methods, apparatus, and systems involve transmitting a unit of data from a first device, wherein the unit of data comprises at least a version-specific portion and a version identifier associated with the version-specific portion, receiving the unit of data at a second device distinct from the first device, processing the version-specific portion at the second device if the second device recognizes the associated version identifier, and disregarding the version-specific portion at the second device if the second device does not recognize the associated version identifier. Disregarding the version-specific portion may comprise examining a data length field in the data unit associated with the version-specific portion to determine a length value and skipping an amount of data corresponding to the length value.