Abstract: Provided are a Fail Bit (FB) repair solution determination method and device, which are applied to a chip including multiple subdomains. The chip further includes Redundancy (RD) circuits, and the RD circuits are configured to repair FBs in the subdomains. The method includes that: after one or more available RD circuits are determined for a target FB presently to be repaired in a subdomain, a reliability value of each available RD circuit is acquired from an RD circuit reliability list, the RD circuit reliability list including reliability values of multiple RD circuits, and a repair solution for the target FB in the subdomain is determined according to the reliability value of the available RD circuit. The reliability value of the RD circuit is obtained by performing big data analysis on relationships between generated FBs and RD circuits where NFBs are located in the RD circuits.

Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Abstract: A fault detection method is used to determine whether a power switch coupled to a DC bus of a power conversion circuit is faulted. The method includes: detecting a bus voltage to provide a voltage signal and acquiring at least one detection value according to the voltage signal; providing control signals sequentially to turn off or turn on the power switch; determining that the power switch is a short-circuit fault if a first detection value is greater than or equal to a first threshold value when the power switch is turned off; determining that the power switch is an open-circuit fault if a second detection value is less than a second threshold value when the power switch is turned on; and providing an alarm signal or a disable signal when the power switch is the short-circuit fault or the open-circuit fault.

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Abstract: Systems and method are provided for detecting an anomaly of a sensor of a vehicle. In one embodiment, a method includes: storing a plurality of sensor correlation groups based on vehicle dynamics; processing a subset of signals based on the sensor correlation groups to determine when an anomaly exists; processing the subset of signals based on the sensor correlation group to determine which sensor of the sensor correlation group is anomalous; and generating notification data based on the sensor of the correlation group that is anomalous.

Abstract: A test instrument can be coupled to a test point in a network and measure signals in the network that are received via a port connected to the test point. The test instrument may connect to the network via multiple test points. The measurements of the signals received through one or more of the test points are correlated to detect a problem in the network and determine a suggested action.

Abstract: A circuit having a digital output for connecting an electrical wire that is connected to an actuator, the digital output having a high level in a first voltage range, a low level in a second voltage range, and a third voltage range that is formed between the first voltage range and the second voltage range. The circuit being configured to output a test voltage, wherein the test voltage differs by a voltage difference from the high level and the low level.

Abstract: A test circuit includes a comparator and a comparison control circuit. The comparator is configured to compare a first input signal with a second input signal to generate a comparison result signal. The comparison control circuit is configured to perform at least one of an operation for latching the comparison result signal as reference data and an operation for outputting the comparison result signal as a first output signal. The comparison control circuit is configured to provide expectation data as the first input signal and read data as the second input signal in accordance with the reference data.

Abstract: A semiconductor device includes an external terminal, an input buffer having an input terminal connected to the external terminal, a voltage generating circuit configured to generate a test voltage supplied to the input terminal, and a control circuit configured to determine whether the input buffer is deteriorated based on the test voltage supplied to the input terminal and an output level of the input buffer responding to the test voltage.

Abstract: A corresponding value of a data state metric associated with each of a value of a plurality of values of a memory access operation parameter used in one or more memory access operation is measured. An optimal metric value based on the measured values of the predetermined data state metric is determined. An optimal value of the memory access operation parameter from the plurality of values of the memory access operation parameter is selected.

Abstract: Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result.

Abstract: An electronic device, a signal validator, and a method for signal validation are provided. The electronic device includes a circuit board generating a plurality of signals and a signal validator. The signal validator records a current voltage level of each signal as a sequence code and records a time interval between the sequence code and a previous sequence code as a delay time corresponding to the sequence code when a voltage level of one of the plurality of signals changes. The signal validator sequentially determines whether the sequence code matches with a prearranged sequence code. When the sequence code matches with the prearranged sequence code, the signal validator determines whether each delay time corresponding to each sequence code exceeds a predetermined delay time. When the delay time is less than the predetermined delay time, the signal validator determines that the plurality of signals passes signal validation.

Abstract: A system for changing a sensed parameter group for a motor includes a data collector communicatively coupled to a plurality of input sensors, each of the plurality of input sensors operatively coupled to a motor, wherein the motor comprises a component of an industrial environment; a controller, comprising: a data acquisition circuit structured to interpret a plurality of detection values corresponding to a sensed parameter group, wherein the sensed parameter group comprises at least a portion of the plurality of input sensors; a pattern recognition circuit structured to determine a recognized pattern value in response to the plurality of detection values; and a sensor learning circuit structured to update the sensed parameter group in response to the recognized pattern value.

Abstract: Systems and methods for changing a sensed parameter group include a data collector communicatively coupled to a plurality of input sensors, each of the plurality of input sensors operatively coupled to a one of a mixer or an agitator, wherein the one of the mixer or the agitator comprises a component of an industrial environment; a controller, comprising: a data acquisition circuit structured to interpret a plurality of detection values corresponding to a sensed parameter group, wherein the sensed parameter group comprises at least a portion of the plurality of input sensors; a pattern recognition circuit structured to determine a recognized pattern value in response to the plurality of detection values; and a sensor learning circuit structured to update the sensed parameter group in response to the recognized pattern value.

Abstract: A system for changing a sensed parameter group for a pump or fan includes a data collector communicatively coupled to a plurality of input sensors, each of the plurality of input sensors operatively coupled to a one of a pump or a fan, wherein the one of the pump or the fan comprises a component of an industrial environment; a controller, comprising: a data acquisition circuit structured to interpret a plurality of detection values corresponding to a sensed parameter group, wherein the sensed parameter group comprises at least a portion of the plurality of input sensors; a pattern recognition circuit structured to determine a recognized pattern value in response to the plurality of detection values; and a sensor learning circuit structured to update the sensed parameter group in response to the recognized pattern value.

Abstract: A method for checking data in a storage unit of a system on a chip; a monitoring unit, which may be activated or deactivated by the system on a chip, being implemented in the system on a chip. When it is activated, the monitoring unit storing error correction codes for executing error correction methods, in the storage unit, such that, for a predefined number of data blocks of the storage unit, in each instance, a data block including an associated error correction code is stored. When access to data in the storage unit is intended to take place, the monitoring unit addresses the respective data and an associated error correction code and checks the addressed data prior to the respective access, using the addressed error correction code, and correcting them when required.

Abstract: A method is provided for testing discrete output signals of a device-under-test (DUT). The method includes receiving an electrical quantity at each conductive path of a plurality of conductive paths that are each coupled to respective discrete output signals of the DUT in one-to-one correspondence. The method further includes controlling application of the electrical quantity to each of the conductive path independent of application of the electrical quantity along the other conductive paths, so that a the electrical quantity is applied simultaneously to all of the conductive paths, the electrical quantity applied to each conductive path being toggled at a unique frequency having a unique period.

Abstract: Provided is a test apparatus for testing a device under test (DUT), the apparatus operating at an operating frequency that is lower than an operating frequency of the DUT. The test apparatus includes a clock source which generates a clock according to the operating frequency of the test apparatus, a clock multiplier configured to multiply the generated clock source by a multiplication number which is set according to the operating frequency of the DUT and output a first clock for the DUT, a phase converter configured to shift a phase of the generated clock according to the multiplication number and output a plurality of second clocks having different phases, and a test pattern comparator configured to sequentially collect pieces of data from the DUT by sequentially applying the plurality of second clocks having different phases.

Abstract: In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.

Abstract: A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.

Abstract: A method for testing an integrated circuit, comprising: accessing a database associated with a test template, wherein said test template is configured to test a selected function of the integrated circuit; storing, in said database, data corresponding to at least partial predicted results of one or more random instruction sequences generated based on said test template; generating, by an automated test generation tool, a random instruction sequence based on said test template; executing said instruction sequence by a hardware exerciser, in the integrated circuit; and comparing results of said instruction sequence with said at least partial predicted results, to verify a function of said integrated circuit.

Abstract: In an approach to simulating an electronic device, a copy of a design under test is created. A delayed buffer for the copy is created, where the inputs to the design under test are stored in the delayed buffer. A test program is run on the design under test and the copy, where the test program running on the copy is delayed in time by the delayed buffer. Responsive to determining that an event has occurred on the design under test, the test program on the copy is halted. The cause of the event is determined by using the inputs stored in the delayed buffer to scan the copy.

Abstract: A system includes a power supply configured to adjust a voltage supplied to a device under test (DUT) based on one of an input voltage of the DUT supplied to a power supply sense input of the power supply and a feedback signal indicative of an internal voltage of the DUT supplied to the power supply sense input, and a relay circuit configured to transition between supplying the input voltage to the power supply sense input and supplying the feedback signal to the power supply sense input. When supplying the feedback signal to the power supply sense input, the relay circuit establishes an electrical path between the input voltage and the power supply sense input to prevent the power supply sense input from floating during the transition.

Abstract: An integrated circuit (IC) chip for providing a safety-critical value includes first and second processing paths. The first processing path includes a first processing element and is coupled to receive a first input signal on a first input pin and to provide a first output signal that provides the safety-critical value on an output pin. The second processing path includes a second processing element and is coupled to receive a second input signal and to provide a second output signal. The first processing path and the second processing path are independent of each other. A smart comparator on the IC chip receives the first output signal and the second output signal and initiates a remedial action responsive to a difference between the first output signal and the second output signal reaching a configurable threshold.

Abstract: Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number. The filter circuit further includes a logic gate configured to pass one of the pulses of the clock signal responsive to the output signal from the control circuit being enabled and filter another of the pulses responsive to the output signal from the control circuit being not enabled.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: A video game test system can determine an objective measure of elapsed time between interaction with a video game controller and the occurrence of a particular event within the video game. This objective measure enables a tester to determine whether a video game is objectively operating slowly or just feels slow to the tester, and may indicate the existence of coding errors that may affect execution speed, but not cause visible errors. The system may obtain the objective measure of elapsed time by simulating a user's interaction with the video game. Further, the system may identify data embedded into a frame of an animation by the video game source code to identify the occurrence of a corresponding event. The system can then measure the elapsed time between the simulated user interaction and the occurrence or triggering of the corresponding event.

Abstract: A read channel is configured to obtain an analog readback waveform from a magnetic recording medium of a disk drive at a sampling rate of one sample per one written bit. A buffer is coupled the read channel. Circuitry is configured to inject a plurality of different phase offsets into the read channel for each of a plurality of revolutions of the medium. The circuitry is also configured to store, in a buffer, an amplitude of the readback waveform for each of the different phase offsets. The circuitry is further configured to generate an oversampled readback waveform using the amplitudes stored in the buffer.

Abstract: Systems and techniques are disclosed for an enhanced automated protocol for secure application testing. An example method includes receiving, via a first component of a system and from a user device, selection of testing information, the testing information including a test device to perform one or more selected test suites, and the test suites being associated with an application. Test suite information is generated via a second component of the system based on the selected test suites, with the first component instructing the second component to generate the testing information according to the particular protocol. The test suite information is provided via the second component to the test device, with the test suite information being provided in response to polling from the test device. Test results are received via the second component, with the test results being routed by the second component to the first component for presentation via the user device.

Abstract: A method for controlling a correctable error reporting function and applicable to a server device is provided, including: receiving, by control unit, a plurality of first error messages sent by a first hardware component in which a plurality of correctable errors occurs in a plurality of hardware components; determining, by the control unit, according to the first error messages, error types of the errors occurring in the first hardware component; determining, by the control unit, whether the number of occurrences of the errors of the error types that occur in the first hardware component within first preset duration reaches a preset number of times; and if the determining result is yes, controlling, by the control unit, the first hardware component to stop performing an error reporting function corresponding to the first error type.

Abstract: An application test system can determine an objective measure of elapsed time between interaction with a user interface device and the occurrence of a particular event within the application, such as a video game. This objective measure enables a tester to determine whether an application is objectively operating slowly or just feels slow to the tester, and may indicate the existence of coding errors that may affect execution speed, but not cause visible errors. The system may obtain the objective measure of elapsed time by simulating a user's interaction with the application. Further, the system may identify data embedded into a frame of an animation by the application source code to identify the occurrence of a corresponding event. The system can then measure the elapsed time between the simulated user interaction and the occurrence or triggering of the corresponding event.

Abstract: An apparatus for fault diagnosis and back-up of advanced driver assistance system sensors based on deep learning, the apparatus including: an individual sensor diagnosis unit configured to quantitatively evaluate a reliability of an output result of each sensor at each moment on the basis of a model for an output of each sensor under a normal operation; an inter-sensor mutual diagnosis unit configured to extract shared representation between the sensors and quantitatively evaluate a normal-operation reliability of the output result of each sensor on the basis of the extracted shared representation; and an integrated diagnosis unit configured to quantitatively evaluate a final reliability of each sensor on the basis of output results of the individual sensor diagnosis unit and the inter-sensor mutual diagnosis unit.

Abstract: A time measurement unit measures the time interval between edges to be monitored in a signal under test DUT_Output including serial data output from a device under test (DUT) 400. A comparison judgment unit calculates the number of bits of the serial data included between the edges to be monitored, based on the time interval thus measured. Furthermore, the comparison judgment unit compares the number of bits thus calculated with an expected value thereof.

Abstract: A method, computer program product and/or system is disclosed. According to an aspect of this invention, a device under test (DUT) is switched to a functional test mode. In some embodiments of the present invention, the DUT receives a general scan design (GSD) pattern while in the functional test mode. In some embodiments, the DUT executes a first functional test corresponding to the GSD pattern. In yet other embodiments, the DUT further comprises a state machine that controls the execution of the first functional test. The DUT may further store the output address, the output data, and the status to an address register, a data register, and a status register, respectively and/or send the output address, the output data, and the status to an address register to an automatic testing equipment (ATE).

Abstract: A mechanism is provided to improve the availability of an ICS and an external system that uses data from the ICS by ensuring operation of the ICS and operation of the system even if an anomaly has occurred in a device in the ICS. The mechanism receives measured data from the plurality of devices, calculates prediction data by using the measured data and correlation information used for deriving prediction data for correlated devices, and provides the measured data and the prediction data.

Abstract: A read channel is configured to obtain an analog readback waveform from a magnetic recording medium of a disk drive at a sampling rate of one sample per one written bit. A buffer is coupled the read channel. Circuitry is configured to inject a plurality of different phase offsets into the read channel for each of a plurality of revolutions of the medium. The circuitry is also configured to store, in a buffer, an amplitude of the readback waveform for each of the different phase offsets. The circuitry is further configured to generate an oversampled readback waveform using the amplitudes stored in the buffer.

Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.

Abstract: A file system can allocate data of a storage system into data units, wherein a set of data units can be grouped into a storage region within a volume. A process of verifying validity of data within a storage region can include obtaining a first set of error-detecting codes from a subset of the data stored in a storage system, such as from a data unit of a file system object. Each of the first set of error-detecting codes can be associated with a corresponding data unit within the storage region. A second set of error-detecting codes can be generated based at least in part on the first set of error-detecting codes, and the second set of error-detecting codes can be associated with the storage region so that the second set of error-detecting codes can be used to verify the validity of the data within the storage region.

Abstract: Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.

Abstract: Routing a circuit design for implementation within an integrated circuit can include determining a set of candidate paths from available paths of the integrated circuit for connecting source-sink pairs of the circuit design, wherein the set of candidate paths is initially a subset of the available paths, and generating, using a processor, an expression having a plurality of variables expressed as a conjunction of routing constraints representing legal routes of the source-sink pairs using only the candidate paths. A routing result for the circuit design can be determined by initiating execution of a SAT solver on the expression using the processor.

Abstract: Techniques for reporting defects in a flash memory back-up system include organizing backed-up data into multiple stripes of a logical block address (LBA). A stripe is a set of pages across all available flash memory devices which have the same block and page address. In response to encountering an error in a block of flash memory during back-up of a stripe of data in one or more last pages of a logical block address, the stripe of data is re-written at a page address in the next LBA and preceding LBA metadata is embedded for the stripe of backed-up data in the re-written stripe of data in the next LBA including an indication of the location of new error block in the preceding LBA.

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: An electric power supply device for a plurality of light sources on a motor vehicle. The device includes a plurality of control units configured to control electric power supply of at least one respective light source. The control units each include a diagnostic unit configured to deliver a diagnostic signal for the respective light source. According to the invention, the device is designed to deliver two binary signals for the identification of a partial failure and for the identification of a total failure of light sources.

Abstract: Methods and apparatus are described for converting a pre-silicon Open Verification Methodology or Universal Verification Methodology (OVM/UVM) device under test (DUT) into a design implementable on a programmable integrated circuit (IC) and for converting the pre-silicon OVM/UVM stimulus from the driver and expected response from the scoreboard into timing aware stimulus-response vectors that can be applied through the tester onto the pads of the programmable IC that contains the implemented design. This approach can handle the clock and other input stimuli changing concurrently in the pre-silicon testbench, and the vectors generated therefrom will be in the proper form so as to work deterministically on the silicon on the tester.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a device interface board (DIB) configured to interface with a device under test (DUT); and a primitive configured to control the device interface board and testing of the device under test. The primitive is an independent self contained test control unit comprising: a backplane interface configured to couple with the device interface board; a power supply component configured to control power to the backplane interface; and a site module configured to control testing signals sent to the device interface board and device under test. The site module is reconfigurable for different test protocols. The primitive can be compatible with a distributed testing infrastructure. In one exemplary implementation, the primitive and device interface board are portable an operable to perform independent testing unfettered by other control components.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: Invention achieves reduced amount of terminals to control a test mode, test function and test results of a given standard for at least one “wrapped core” (40,100) (a core 100 surrounded by a wrapper boundary register (40) as “wrapper chain”). Test flexibility and speed of testing the core (100) are also improved. Suggested serial test interface comprises a state machine (210) and an instruction register (213) for wrapper-instructions, supplied through a single physical data input terminal (1a). The state machine (210) reads wrapper-instructions held by the instruction register (213) and generates on-chip wrapper control signals (30) of the given standard for the wrapper boundary register (40) of the core (100). At least one wrapper-instruction read from the Instruction Register (213) provides at least one wrapper control signal (30). The single input terminal (1a) also supplies an input test signal SDI for coupling to the wrapper boundary register (40) as on chip logical input test signal WSI.

Abstract: The disclosure discloses methods and systems for managing an authentication device such as a card reader coupled to a multi-function device. The multi-function device includes a memory for storing information related to one or more users, one or more pre-authorized users and alert setting instructions. The multi-function device includes an authentication device, coupled to a universal serial bus peripheral port of the device, and configured for: receiving authentication information from a user via an input method. The multi-function device further includes a control system configured for authenticating the user to access the multi-function device for one or more functions, based on the authentication information. The control system is further configured for generating an alert for the one or more pre-authorized users when the authentication device is disconnected or is malfunctioned, and for transmitting the alert to the one or more pre-authorized users, for one or more pre-defined actions.