Device Response Compared To Expected Fault-free Response Patents (Class 714/736)
  • Patent number: 10490296
    Abstract: Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: November 26, 2019
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Michael R. Ouellette, Deepak I. Hanagandi, Aravindan J. Busi, Kiran K. Narayan, Michael A. Ziegerhofer
  • Patent number: 10489240
    Abstract: A file system can allocate data of a storage system into data units, wherein a set of data units can be grouped into a storage region within a volume. A process of verifying validity of data within a storage region can include obtaining a first set of error-detecting codes from a subset of the data stored in a storage system, such as from a data unit of a file system object. Each of the first set of error-detecting codes can be associated with a corresponding data unit within the storage region. A second set of error-detecting codes can be generated based at least in part on the first set of error-detecting codes, and the second set of error-detecting codes can be associated with the storage region so that the second set of error-detecting codes can be used to verify the validity of the data within the storage region.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: November 26, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Cornel Emilian Rat, William Tipton, Chesong Lee, Rajsekhar Das, Erik Hortsch, Arushi Aggarwal
  • Patent number: 10445456
    Abstract: Routing a circuit design for implementation within an integrated circuit can include determining a set of candidate paths from available paths of the integrated circuit for connecting source-sink pairs of the circuit design, wherein the set of candidate paths is initially a subset of the available paths, and generating, using a processor, an expression having a plurality of variables expressed as a conjunction of routing constraints representing legal routes of the source-sink pairs using only the candidate paths. A routing result for the circuit design can be determined by initiating execution of a SAT solver on the expression using the processor.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: October 15, 2019
    Assignee: XILINX, INC.
    Inventor: Henri Fraisse
  • Patent number: 10387280
    Abstract: Techniques for reporting defects in a flash memory back-up system include organizing backed-up data into multiple stripes of a logical block address (LBA). A stripe is a set of pages across all available flash memory devices which have the same block and page address. In response to encountering an error in a block of flash memory during back-up of a stripe of data in one or more last pages of a logical block address, the stripe of data is re-written at a page address in the next LBA and preceding LBA metadata is embedded for the stripe of backed-up data in the re-written stripe of data in the next LBA including an indication of the location of new error block in the preceding LBA.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventor: Kelvin Wong
  • Patent number: 10353001
    Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 16, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Rajesh Maruti Bhagwat, Nitin Satishchandra Kabra, Jay Shah
  • Patent number: 10339005
    Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Edward McGlaughlin, Joseph M. Jeddeloh
  • Patent number: 10308178
    Abstract: An electric power supply device for a plurality of light sources on a motor vehicle. The device includes a plurality of control units configured to control electric power supply of at least one respective light source. The control units each include a diagnostic unit configured to deliver a diagnostic signal for the respective light source. According to the invention, the device is designed to deliver two binary signals for the identification of a partial failure and for the identification of a total failure of light sources.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: June 4, 2019
    Assignee: VALEO ILUMINACION
    Inventors: Miguel-Angel Pena, Antonio Domingo Illan, Jose-Ramon Martinez-Perez, Juan Lara Cabeza, Juan-Jose Santaella, Tomas Martinez-Zaldivar
  • Patent number: 10310014
    Abstract: Methods and apparatus are described for converting a pre-silicon Open Verification Methodology or Universal Verification Methodology (OVM/UVM) device under test (DUT) into a design implementable on a programmable integrated circuit (IC) and for converting the pre-silicon OVM/UVM stimulus from the driver and expected response from the scoreboard into timing aware stimulus-response vectors that can be applied through the tester onto the pads of the programmable IC that contains the implemented design. This approach can handle the clock and other input stimuli changing concurrently in the pre-silicon testbench, and the vectors generated therefrom will be in the proper form so as to work deterministically on the silicon on the tester.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: June 4, 2019
    Assignee: XILINX, INC.
    Inventors: Subodh Kumar, Aniruddha Talukder, Kameswari SB Angada
  • Patent number: 10241146
    Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a device interface board (DIB) configured to interface with a device under test (DUT); and a primitive configured to control the device interface board and testing of the device under test. The primitive is an independent self contained test control unit comprising: a backplane interface configured to couple with the device interface board; a power supply component configured to control power to the backplane interface; and a site module configured to control testing signals sent to the device interface board and device under test. The site module is reconfigurable for different test protocols. The primitive can be compatible with a distributed testing infrastructure. In one exemplary implementation, the primitive and device interface board are portable an operable to perform independent testing unfettered by other control components.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: March 26, 2019
    Assignee: Advantest Corporation
    Inventors: Mei-Mei Su, Ben Rogel-Favila
  • Patent number: 10209304
    Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 19, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10151794
    Abstract: Invention achieves reduced amount of terminals to control a test mode, test function and test results of a given standard for at least one “wrapped core” (40,100) (a core 100 surrounded by a wrapper boundary register (40) as “wrapper chain”). Test flexibility and speed of testing the core (100) are also improved. Suggested serial test interface comprises a state machine (210) and an instruction register (213) for wrapper-instructions, supplied through a single physical data input terminal (1a). The state machine (210) reads wrapper-instructions held by the instruction register (213) and generates on-chip wrapper control signals (30) of the given standard for the wrapper boundary register (40) of the core (100). At least one wrapper-instruction read from the Instruction Register (213) provides at least one wrapper control signal (30). The single input terminal (1a) also supplies an input test signal SDI for coupling to the wrapper boundary register (40) as on chip logical input test signal WSI.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: December 11, 2018
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventor: Ulrike Mueller-Schniek
  • Patent number: 10104240
    Abstract: The disclosure discloses methods and systems for managing an authentication device such as a card reader coupled to a multi-function device. The multi-function device includes a memory for storing information related to one or more users, one or more pre-authorized users and alert setting instructions. The multi-function device includes an authentication device, coupled to a universal serial bus peripheral port of the device, and configured for: receiving authentication information from a user via an input method. The multi-function device further includes a control system configured for authenticating the user to access the multi-function device for one or more functions, based on the authentication information. The control system is further configured for generating an alert for the one or more pre-authorized users when the authentication device is disconnected or is malfunctioned, and for transmitting the alert to the one or more pre-authorized users, for one or more pre-defined actions.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 16, 2018
    Assignee: XEROX CORPORATION
    Inventors: Peter Granby, Rajana Mukesh Panchani
  • Patent number: 10042786
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 7, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
  • Patent number: 10042687
    Abstract: Techniques for performing redundant multi-threading (“RMT”) include the use of an RMT compare instruction by two program instances (“work-items”). The RMT compare instruction specifies a value from each work-item to be compared. Upon executing the RMT compare instructions, the work-items transmit the values to a hardware comparator unit. The hardware comparator unit compares the received values and performs an error action if the values do not match. The error action may include sending an error code in a return value back to the work-items that requested the comparison or emitting a trap signal. Optionally, the work-items also send addresses for comparison to the comparator unit. If the addresses and values match, then the comparator stores the value at the specified address. If either or both of the values or the addresses do not match, then the comparator performs an error action.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 7, 2018
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Daniel I. Lowell, Manish Gupta
  • Patent number: 10025895
    Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: July 17, 2018
    Assignee: OPTIMA DESIGN AUTOMATION LTD
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Patent number: 9891281
    Abstract: A method includes receiving from a user, via a user interface, coverage-event characteristics. Using a processor, output data of test runs executed on a device-under-test is analyzed to identify one or a plurality of coverage events that possess the coverage-event characteristics and to identify one or a plurality of contributing test runs in said test runs that contributed to said one or a plurality of coverage events. Information on said one or a plurality of contributing test runs is outputted via an output device.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 13, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yael Kinderman, Erez Bashi, Oded Oren
  • Patent number: 9804875
    Abstract: A software component for automated processing of multi-usage data, implementing functions requiring various levels of security or limits of responsibility. The software component includes a plurality of virtual machines, each virtual machine being adapted for executing at least one function requiring a level of security or a limit of responsibility which is predetermined and a hypervisor adapted for controlling execution of the plurality of virtual machines.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: October 31, 2017
    Assignee: AIRBUS (S.A.S.)
    Inventors: Severine Vermande, Philippe Biondi
  • Patent number: 9766837
    Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Edward McGlaughlin, Joseph M. Jeddeloh
  • Patent number: 9595350
    Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: March 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Henning F. Spruth, Qadeer A. Qureshi, Reinaldo Silveira
  • Patent number: 9594615
    Abstract: A method for data storage includes reading from a memory device data that is stored in a group of memory cells as respective analog values, and classifying readout errors in the read data into at least first and second different types, depending on zones in which the analog values fall. A memory quality that emphasizes the readout errors of the second type is assigned to the group of the memory cells, based on evaluated numbers of the readout errors of the first and second types.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: March 14, 2017
    Assignee: APPLE INC.
    Inventors: Yael Shur, Eyal Gurgi, Moshe Neerman, Naftali Sommer
  • Patent number: 9568498
    Abstract: A printed circuit board has first terminals for contacting terminals of a socket, second terminals for contacting terminals of a test fixture of an automatic test equipment, which are adapted for contacting the terminals of the socket of a device under test, transmission lines for connecting the first terminals and the terminals, and an extracting circuit electrically coupled to one of the transmission lines and configured to extract the signal being exchanged between the device under test and the automatic test equipment. The extracting circuit has a resistor or an electrical resistor network, wherein a loss added on the signal being exchanged between the device under test and the automatic test equipment over the one transmission line due to the presence of the printed circuit board is smaller than 6 dB.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: February 14, 2017
    Assignee: Advantest Corporation
    Inventors: Jose Antonio Alves Moreira, Marc Moessinger
  • Patent number: 9568536
    Abstract: A test circuitry is configured to test for transition delay defects in a first inter-die interconnect connecting a first die and a second die. A test data value is initially received and temporarily stored in a data storage element. The test data is subsequently looped between the storage element and the second die through a feedback loop including the first inter-die interconnect and a second inter-die interconnect. A data conditioner conditions the test data value received from the second die so as to make it distinguishable from the test data value sent to the second die. A clock pulse generator generates a delayed clock pulse. A selection logic applies the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. A readout unit for reading out a test data value stored in the data storage element.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: February 14, 2017
    Assignees: IMEC, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sandeep Kumar Goel, Erik Jan Marinissen
  • Patent number: 9563533
    Abstract: Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync points provide a unique identifier field and a context to the data that will follow it. All trace data streams may generate a sync point with this unique identifier. These unique identifiers allow synchronization between multiple trace data streams. When multiple trace data streams are on, it is possible that the data input rate may be higher than the data output rate. If synchronization is lost in such a case, there must be a scheme to resynchronize the streams. This invention is a technique for this needed resynchronization.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: February 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manisha Agarwala, John Johnsen
  • Patent number: 9542263
    Abstract: An electronic device has a runtime integrity checker for monitoring contents of storage locations in an address range. The runtime integrity checker has a location selector for selecting the storage locations by generating addresses within the address range for locations to be checked, an interface unit coupled to the location selector for receiving the addresses for accessing the locations to be checked via a bus interface, and a processor coupled to the interface unit for retrieving the contents from the locations to be checked. A mask unit is provided for processing a mask for defining the locations to be checked based on bits in the mask. The hardware enables selective monitoring of non contiguous storage locations or data areas.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 10, 2017
    Assignee: NXP USA, INC.
    Inventors: Arthur Stuart Mackay, Graham Edmiston
  • Patent number: 9529699
    Abstract: A system, medium and method for automatically generating test data to be applied to test a target software code is disclosed. Input parameter data is received from a user via a displayed user interface, wherein the input parameter data is directed to a user selected data type, the data type being a Boolean, string, or integer. One or more preestablished stored testing algorithms is automatically selected based on the user selected data type and one or more values are applied to the selected one or more preestablished stored testing algorithms in accordance with the user selected data type. At least one set of test data from the one or more identified applicable testing algorithms is automatically generated, wherein the at least one set of test data generated from the identified testing algorithms can be used as inputs for testing the target software code.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: December 27, 2016
    Assignee: Wipro Limited
    Inventors: Anoop Rajan, Sourav Bhattacharya
  • Patent number: 9484116
    Abstract: At least one general-purpose server is connected to a PE module via Ethernet (trademark). A control unit of the PE module controls a PE circuit and multiple fail memory in a real-time manner, temporarily stores fail information stored in the multiple fail memory, performs data processing on the fail information, and transfers the fail information thus processed to the general-purpose server. Each general-purpose server is controlled according to a computer program so as to perform redundancy analysis for a DUT based on the data received from the PE module.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: November 1, 2016
    Assignee: ADVANTEST CORPORATION
    Inventors: Masaaki Kosugi, Takashi Ohguro, Michisuke Sakamoto, Toshiro Fujii, Takahiro Honma, Hideto Omori
  • Patent number: 9470734
    Abstract: According to this method, an electromagnetic spectrum emitted by the electronic component during operation is measured and the measured electromagnetic spectrum is compared with a predetermined template defining at least one safe operating range in order to detect possible malfunction or risk of malfunction of the electronic component.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: October 18, 2016
    Assignee: THALES
    Inventors: Didier Regis, Marc Gatti, Damien Jugie, Sebastien Thomas
  • Patent number: 9473172
    Abstract: A system and method for receiving includes an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream. A plurality of storage devices is configured to sample the serial stream. An output demultiplexer is configured to demultiplex the sampled serial stream into a plurality of output streams. A PRBS checker is configured to compare a PRBS pattern on the plurality of output streams with a predicted PRBS pattern. A phase rotator is configured to adjust a data control clock based upon the comparison of the PRBS checker to reduce latency in the receiver.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: October 18, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Leonard R. Chieco, Frank R. Keyser, III, Michael A Sorna
  • Patent number: 9396097
    Abstract: Disclosed are methods, circuits, apparatuses, systems and associated computer executable code for generating a unit test. According to some embodiments, there is provided computerized system including test generation software, which software may include code analyzing logic to identify within a code under test or within an associated Code Statement Segment (CSS): (1) one or more dependencies, and (2) one or more fields read by the CUT or Associated CSS. The may also be include a code statement provider to provide: (1) at least one CSS constructed to resolve at least one identified dependency, and (2) at least one CSS constructed to modify at least one identified field.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: July 19, 2016
    Assignee: TYPEMOCK LTD.
    Inventor: Eli Lopian
  • Patent number: 9291671
    Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: March 22, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Yasuyoshi Sunaga, Hideki Sakakibara, Yuko Ito, Tomoji Nakamura, Atsushi Hazeyama, Kozaburo Kurita, Koki Tsutsumida
  • Patent number: 9274171
    Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, John R. Goss, Eric D. Hunt-Schroeder, Andrew K. Killorin
  • Patent number: 9244111
    Abstract: A testing device determines values of various electrical variables associated with a device within a process system. The testing device provides bi-directional electrical communication with a device to be monitored and automatically provides a connection configuration between a processing unit and a set of input/output ports. The processing unit outputs a test signal and a configuration control signal to the input/output port control circuitry. The input/output port control circuitry provides a connection configuration to direct the test signal to the device to be monitored and directs a return signal from the monitored device to the processing unit. The processing unit measures an electrical characteristic of the return signal and determines at least two electrical variables associated with the monitored device based upon the measured electrical characteristic of the return signal.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: January 26, 2016
    Inventors: Ronald P. Clarridge, Gerald T. Allen, Jr.
  • Patent number: 9245652
    Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: January 26, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kay Hesse, Suresh Periyacheri
  • Patent number: 9229057
    Abstract: A semiconductor test system includes a user device configured to operate a reference device in accordance with an interface signal based on a timing signal having a variable operating frequency, a pattern synthesis apparatus configured to measure an interval between adjacent edges of the timing signal transmitted from the user device, and extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data, and a test device configured to receive the test pattern data, reconstruct the timing signal based on the measured interval, generate a test driving signal such that the logic value is extracted from a device under test (DUT) based on the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Yeol Kim, In-su Yang, Min Sung Kim, Jae Hyun Baek, Jin-Kyu Choi, Ho Sun Yoo
  • Patent number: 9201092
    Abstract: Embodiments of the invention relate to an apparatus and a method for testing a plurality of devices under test. The apparatus for testing a plurality of devices under test comprises a common device output line and a driver unit configured to provide a stimulus to the DUTs. The driver unit is configured such that the stimulus reaches different DUTs at different times, thereby creating stimuli time shifts at the DUTs. The apparatus further comprises a receiver unit electrically coupled to the common device output line and a plurality of DUTs connections, electrically coupled to the common device output line, so that DUT terminals of the plurality of DUTs are electrically coupleable via the common device output line to the receiver unit.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: December 1, 2015
    Assignee: ADVANTEST CORPORATION
    Inventors: Klaus-Peter Behrens, Marc Moessinger
  • Patent number: 9201111
    Abstract: A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventor: Yong-Ho Kong
  • Patent number: 9201480
    Abstract: An emulation system for determining an arbitrary charging protocol in USB charging ports and for optimally charging portable devices. The emulation system comprises a power switch for powering on the emulation system, a high-speed data switch for transferring data to and from the portable device, a USB receptacle port including data pins (DP and DM), VBUS, and GND. The emulation system further comprises a profile database that stores one or more charging profiles including one or more stimulus-response pairs for each charging profile. The emulation circuit further includes emulation circuitry for detecting stimulus generated by the portable device and for generating responses according to the charging profiles.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: December 1, 2015
    Assignee: STANDARD MICROSYSTEMS CORPORATION
    Inventor: Christopher Fischbach
  • Patent number: 9170784
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for creating mobile device applications. In one aspect, a method includes determining that a user has entered one or more user inputs into an integrated development environment, to select or arrange a component that defines a portion of an application, and transmitting interpreter code that corresponds to the component to a mobile device, where the interpreter code, when interpreted by a command interpreter on the mobile device, causes the mobile device to generate a mock-up of the portion of the application defined by the component.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: October 27, 2015
    Assignee: Google Inc.
    Inventor: Mark S. Friedman
  • Patent number: 9157934
    Abstract: A test apparatus for testing a device under test, includes a low-speed comparator, a high-speed comparator that is operable faster than the low-speed comparator, and a switching section that switches, according to a signal output from the device under test, which one of the low-speed comparator and the high-speed comparator is used to measure a signal under measurement output from the device under test. The test apparatus may further include a termination resistance that is arranged in parallel with the high-speed comparator.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: October 13, 2015
    Assignee: ADVANTEST CORPORATION
    Inventor: Takashi Kato
  • Patent number: 9143276
    Abstract: A nested CRC code generation method for data transmission error control, comprising: segmenting the data to be computed, allocating a CRC code computing channel to each of the data segments according to the data type, computing CRC sub-codes by the computing channels, sorting the CRC sub-codes, and generating a nested CRC code by sending the sorted CRC sub-codes to the final CRC code computing channel directly or by using the sorted CRC sub-codes as the new data to be computed, repeating the above CRC sub-code computing process and sending the final sorted CRC sub-codes to the final CRC code computing channel. A nested CRC code generation device for data transmission error control, comprising: a data segmenting module, a computing channel selecting module, a multi-channel CRC code computing module, a data sorting module, a set of registers, a data distributor, a counter and a single-channel CRC code computing module.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: September 22, 2015
    Assignee: Hua Zhong University of Science and Technology
    Inventors: Wenli Zhou, Binbin Duan
  • Patent number: 9130843
    Abstract: A method of sending hypertext transfer protocol (HTTP) adaptive streaming (HAS) content from a content source to a client over a transmission control protocol (TCP) connection between the content source and the client may include receiving a request for one or more first HAS data chunks from the client; sending the one or more first HAS data chunks to the client; generating idle delay values indicating an amount of delay in the TCP connection during an idle time period, the idle time period being a time period over which no HAS data chunks are being sent from the content source to the client; receiving a request for a second HAS data chunk from the client; setting the size of a starting TCP congestion window based on the idle delay values; and sending the second HAS chunk to the client using the starting TCP congestion window.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: September 8, 2015
    Assignee: Alcatel Lucent
    Inventors: Shahid Akhtar, Viorel Craciun, Pieter Liefooghe, Ather Chaudhry
  • Patent number: 9116785
    Abstract: A tester on a device under test to test component circuitry of the device under test, the tester comprising: logic configured with firmware to implement test circuitry comprising: protocol generators that are configurable to generate protocols; pattern generators that are configurable to provide test patterns that are drivable according to one or more of the protocols; and a system controller to select, in response to a program input, a test pattern and a protocol with which to test the component circuitry.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 25, 2015
    Assignee: Teradyne, Inc.
    Inventor: Joshua Mason Ferry
  • Patent number: 9116205
    Abstract: An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Patent number: 9116875
    Abstract: According to one embodiment, a test circuit is provided comprising a tester configured to perform a test routine comprising a plurality of test commands for testing an electronic circuit, wherein the tester comprises a checker configured to, if a test command of the plurality of test commands is to be performed, check, whether there is currently a state in which performing the test command could lead to a damage of the electronic circuit and configured to, in case it determines that there is currently a state in which performing the test routine could lead to a damage of the electronic circuit, output a signal indicating that performing the test routine could lead to a damage of the electronic circuit.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: August 25, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Bernhard Moessler, Achim Osterloh
  • Patent number: 9116873
    Abstract: Methods, systems, and computer readable media for adjusting load at a device under test are disclosed. According to one method, the method occurs at a testing platform. The method includes determining whether a current operations rate associated with a device under test (DUT) is near a target operations rate, wherein the current operations rate is associated with one or more simulated users being simulated by the testing platform. The method also includes adjusting the current operations rate by increasing or decreasing the number of simulated users interacting with the DUT in response to determining that the current operations rate associated with the DUT is not near a target operations rate.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: August 25, 2015
    Assignee: IXIA
    Inventors: Partha Majumdar, Pratik Ganguly, Sirshendu Rakshit, Rohan Chitradurga
  • Patent number: 9112539
    Abstract: Systems and methods for data processing. In one case, a data processing system includes a data detector circuit configured to apply a data detection algorithm to a detector input to yield a second detected output, and a data decoder circuit configured to apply a data decoding algorithm to a decoder input to yield a decoded output. The decoder input is derived from an interim data set calculated as a combination of at least a first detected output and the second detected output.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: August 18, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Fan Zhang
  • Patent number: 9058901
    Abstract: A semiconductor apparatus includes: a receiver configured to receive a plurality of input signals through a plurality of pads; a signal processing unit configured to process the input signals received by the receiver and output the processed signals as a plurality of internal signals; a MUX unit configured to select the plurality of internal signals as a plurality of MUX output or select test input data and a plurality of latch signals as the plurality of MUX output signals in response to an input/output select signal; a latch unit configured to output the plurality of MUX output signals as the plurality of latch signals and a final output signal in response to a latch clock signal; and a clock selection unit configured to output any one of a test clock signal and an internal clock signal as the latch clock signal in response to a test mode signal.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: June 16, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young Jun Yoon
  • Patent number: 9021325
    Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 28, 2015
    Assignee: LSI Corporation
    Inventors: Coralyn S. Gauvin, Gabriel L. Romero
  • Patent number: 9015537
    Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Griffin, Dustin J. Vanstee
  • Patent number: 9003254
    Abstract: A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion under test, a comparator and a comparison result recorder. The circuit portion under test receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. The comparator outputs comparison results according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The system receives at least a portion of test signals and at least a portion of ideal response signals in a dynamically configurable time-interleaved manner via one or more physical channels from a test equipment.
    Type: Grant
    Filed: February 16, 2014
    Date of Patent: April 7, 2015
    Inventor: Ssu-Pin Ma