Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

Abstract: Techniques for performing redundant multi-threading (“RMT”) include the use of an RMT compare instruction by two program instances (“work-items”). The RMT compare instruction specifies a value from each work-item to be compared. Upon executing the RMT compare instructions, the work-items transmit the values to a hardware comparator unit. The hardware comparator unit compares the received values and performs an error action if the values do not match. The error action may include sending an error code in a return value back to the work-items that requested the comparison or emitting a trap signal. Optionally, the work-items also send addresses for comparison to the comparator unit. If the addresses and values match, then the comparator stores the value at the specified address. If either or both of the values or the addresses do not match, then the comparator performs an error action.

Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.

Abstract: A method includes receiving from a user, via a user interface, coverage-event characteristics. Using a processor, output data of test runs executed on a device-under-test is analyzed to identify one or a plurality of coverage events that possess the coverage-event characteristics and to identify one or a plurality of contributing test runs in said test runs that contributed to said one or a plurality of coverage events. Information on said one or a plurality of contributing test runs is outputted via an output device.

Abstract: A software component for automated processing of multi-usage data, implementing functions requiring various levels of security or limits of responsibility. The software component includes a plurality of virtual machines, each virtual machine being adapted for executing at least one function requiring a level of security or a limit of responsibility which is predetermined and a hypervisor adapted for controlling execution of the plurality of virtual machines.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.

Abstract: A method for data storage includes reading from a memory device data that is stored in a group of memory cells as respective analog values, and classifying readout errors in the read data into at least first and second different types, depending on zones in which the analog values fall. A memory quality that emphasizes the readout errors of the second type is assigned to the group of the memory cells, based on evaluated numbers of the readout errors of the first and second types.

Abstract: A printed circuit board has first terminals for contacting terminals of a socket, second terminals for contacting terminals of a test fixture of an automatic test equipment, which are adapted for contacting the terminals of the socket of a device under test, transmission lines for connecting the first terminals and the terminals, and an extracting circuit electrically coupled to one of the transmission lines and configured to extract the signal being exchanged between the device under test and the automatic test equipment. The extracting circuit has a resistor or an electrical resistor network, wherein a loss added on the signal being exchanged between the device under test and the automatic test equipment over the one transmission line due to the presence of the printed circuit board is smaller than 6 dB.

Abstract: A test circuitry is configured to test for transition delay defects in a first inter-die interconnect connecting a first die and a second die. A test data value is initially received and temporarily stored in a data storage element. The test data is subsequently looped between the storage element and the second die through a feedback loop including the first inter-die interconnect and a second inter-die interconnect. A data conditioner conditions the test data value received from the second die so as to make it distinguishable from the test data value sent to the second die. A clock pulse generator generates a delayed clock pulse. A selection logic applies the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. A readout unit for reading out a test data value stored in the data storage element.

Abstract: Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync points provide a unique identifier field and a context to the data that will follow it. All trace data streams may generate a sync point with this unique identifier. These unique identifiers allow synchronization between multiple trace data streams. When multiple trace data streams are on, it is possible that the data input rate may be higher than the data output rate. If synchronization is lost in such a case, there must be a scheme to resynchronize the streams. This invention is a technique for this needed resynchronization.

Abstract: An electronic device has a runtime integrity checker for monitoring contents of storage locations in an address range. The runtime integrity checker has a location selector for selecting the storage locations by generating addresses within the address range for locations to be checked, an interface unit coupled to the location selector for receiving the addresses for accessing the locations to be checked via a bus interface, and a processor coupled to the interface unit for retrieving the contents from the locations to be checked. A mask unit is provided for processing a mask for defining the locations to be checked based on bits in the mask. The hardware enables selective monitoring of non contiguous storage locations or data areas.

Abstract: A system, medium and method for automatically generating test data to be applied to test a target software code is disclosed. Input parameter data is received from a user via a displayed user interface, wherein the input parameter data is directed to a user selected data type, the data type being a Boolean, string, or integer. One or more preestablished stored testing algorithms is automatically selected based on the user selected data type and one or more values are applied to the selected one or more preestablished stored testing algorithms in accordance with the user selected data type. At least one set of test data from the one or more identified applicable testing algorithms is automatically generated, wherein the at least one set of test data generated from the identified testing algorithms can be used as inputs for testing the target software code.

Abstract: At least one general-purpose server is connected to a PE module via Ethernet (trademark). A control unit of the PE module controls a PE circuit and multiple fail memory in a real-time manner, temporarily stores fail information stored in the multiple fail memory, performs data processing on the fail information, and transfers the fail information thus processed to the general-purpose server. Each general-purpose server is controlled according to a computer program so as to perform redundancy analysis for a DUT based on the data received from the PE module.

Abstract: A system and method for receiving includes an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream. A plurality of storage devices is configured to sample the serial stream. An output demultiplexer is configured to demultiplex the sampled serial stream into a plurality of output streams. A PRBS checker is configured to compare a PRBS pattern on the plurality of output streams with a predicted PRBS pattern. A phase rotator is configured to adjust a data control clock based upon the comparison of the PRBS checker to reduce latency in the receiver.

Abstract: According to this method, an electromagnetic spectrum emitted by the electronic component during operation is measured and the measured electromagnetic spectrum is compared with a predetermined template defining at least one safe operating range in order to detect possible malfunction or risk of malfunction of the electronic component.

Abstract: Disclosed are methods, circuits, apparatuses, systems and associated computer executable code for generating a unit test. According to some embodiments, there is provided computerized system including test generation software, which software may include code analyzing logic to identify within a code under test or within an associated Code Statement Segment (CSS): (1) one or more dependencies, and (2) one or more fields read by the CUT or Associated CSS. The may also be include a code statement provider to provide: (1) at least one CSS constructed to resolve at least one identified dependency, and (2) at least one CSS constructed to modify at least one identified field.

Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Abstract: A testing device determines values of various electrical variables associated with a device within a process system. The testing device provides bi-directional electrical communication with a device to be monitored and automatically provides a connection configuration between a processing unit and a set of input/output ports. The processing unit outputs a test signal and a configuration control signal to the input/output port control circuitry. The input/output port control circuitry provides a connection configuration to direct the test signal to the device to be monitored and directs a return signal from the monitored device to the processing unit. The processing unit measures an electrical characteristic of the return signal and determines at least two electrical variables associated with the monitored device based upon the measured electrical characteristic of the return signal.

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract: A semiconductor test system includes a user device configured to operate a reference device in accordance with an interface signal based on a timing signal having a variable operating frequency, a pattern synthesis apparatus configured to measure an interval between adjacent edges of the timing signal transmitted from the user device, and extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data, and a test device configured to receive the test pattern data, reconstruct the timing signal based on the measured interval, generate a test driving signal such that the logic value is extracted from a device under test (DUT) based on the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT.

Abstract: An emulation system for determining an arbitrary charging protocol in USB charging ports and for optimally charging portable devices. The emulation system comprises a power switch for powering on the emulation system, a high-speed data switch for transferring data to and from the portable device, a USB receptacle port including data pins (DP and DM), VBUS, and GND. The emulation system further comprises a profile database that stores one or more charging profiles including one or more stimulus-response pairs for each charging profile. The emulation circuit further includes emulation circuitry for detecting stimulus generated by the portable device and for generating responses according to the charging profiles.

Abstract: Embodiments of the invention relate to an apparatus and a method for testing a plurality of devices under test. The apparatus for testing a plurality of devices under test comprises a common device output line and a driver unit configured to provide a stimulus to the DUTs. The driver unit is configured such that the stimulus reaches different DUTs at different times, thereby creating stimuli time shifts at the DUTs. The apparatus further comprises a receiver unit electrically coupled to the common device output line and a plurality of DUTs connections, electrically coupled to the common device output line, so that DUT terminals of the plurality of DUTs are electrically coupleable via the common device output line to the receiver unit.

Abstract: A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for creating mobile device applications. In one aspect, a method includes determining that a user has entered one or more user inputs into an integrated development environment, to select or arrange a component that defines a portion of an application, and transmitting interpreter code that corresponds to the component to a mobile device, where the interpreter code, when interpreted by a command interpreter on the mobile device, causes the mobile device to generate a mock-up of the portion of the application defined by the component.

Abstract: A test apparatus for testing a device under test, includes a low-speed comparator, a high-speed comparator that is operable faster than the low-speed comparator, and a switching section that switches, according to a signal output from the device under test, which one of the low-speed comparator and the high-speed comparator is used to measure a signal under measurement output from the device under test. The test apparatus may further include a termination resistance that is arranged in parallel with the high-speed comparator.

Abstract: A nested CRC code generation method for data transmission error control, comprising: segmenting the data to be computed, allocating a CRC code computing channel to each of the data segments according to the data type, computing CRC sub-codes by the computing channels, sorting the CRC sub-codes, and generating a nested CRC code by sending the sorted CRC sub-codes to the final CRC code computing channel directly or by using the sorted CRC sub-codes as the new data to be computed, repeating the above CRC sub-code computing process and sending the final sorted CRC sub-codes to the final CRC code computing channel. A nested CRC code generation device for data transmission error control, comprising: a data segmenting module, a computing channel selecting module, a multi-channel CRC code computing module, a data sorting module, a set of registers, a data distributor, a counter and a single-channel CRC code computing module.

Abstract: A method of sending hypertext transfer protocol (HTTP) adaptive streaming (HAS) content from a content source to a client over a transmission control protocol (TCP) connection between the content source and the client may include receiving a request for one or more first HAS data chunks from the client; sending the one or more first HAS data chunks to the client; generating idle delay values indicating an amount of delay in the TCP connection during an idle time period, the idle time period being a time period over which no HAS data chunks are being sent from the content source to the client; receiving a request for a second HAS data chunk from the client; setting the size of a starting TCP congestion window based on the idle delay values; and sending the second HAS chunk to the client using the starting TCP congestion window.

Abstract: According to one embodiment, a test circuit is provided comprising a tester configured to perform a test routine comprising a plurality of test commands for testing an electronic circuit, wherein the tester comprises a checker configured to, if a test command of the plurality of test commands is to be performed, check, whether there is currently a state in which performing the test command could lead to a damage of the electronic circuit and configured to, in case it determines that there is currently a state in which performing the test routine could lead to a damage of the electronic circuit, output a signal indicating that performing the test routine could lead to a damage of the electronic circuit.

Abstract: An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).

Abstract: A tester on a device under test to test component circuitry of the device under test, the tester comprising: logic configured with firmware to implement test circuitry comprising: protocol generators that are configurable to generate protocols; pattern generators that are configurable to provide test patterns that are drivable according to one or more of the protocols; and a system controller to select, in response to a program input, a test pattern and a protocol with which to test the component circuitry.

Abstract: Methods, systems, and computer readable media for adjusting load at a device under test are disclosed. According to one method, the method occurs at a testing platform. The method includes determining whether a current operations rate associated with a device under test (DUT) is near a target operations rate, wherein the current operations rate is associated with one or more simulated users being simulated by the testing platform. The method also includes adjusting the current operations rate by increasing or decreasing the number of simulated users interacting with the DUT in response to determining that the current operations rate associated with the DUT is not near a target operations rate.

Abstract: Systems and methods for data processing. In one case, a data processing system includes a data detector circuit configured to apply a data detection algorithm to a detector input to yield a second detected output, and a data decoder circuit configured to apply a data decoding algorithm to a decoder input to yield a decoded output. The decoder input is derived from an interim data set calculated as a combination of at least a first detected output and the second detected output.

Abstract: A semiconductor apparatus includes: a receiver configured to receive a plurality of input signals through a plurality of pads; a signal processing unit configured to process the input signals received by the receiver and output the processed signals as a plurality of internal signals; a MUX unit configured to select the plurality of internal signals as a plurality of MUX output or select test input data and a plurality of latch signals as the plurality of MUX output signals in response to an input/output select signal; a latch unit configured to output the plurality of MUX output signals as the plurality of latch signals and a final output signal in response to a latch clock signal; and a clock selection unit configured to output any one of a test clock signal and an internal clock signal as the latch clock signal in response to a test mode signal.

Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion under test, a comparator and a comparison result recorder. The circuit portion under test receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. The comparator outputs comparison results according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The system receives at least a portion of test signals and at least a portion of ideal response signals in a dynamically configurable time-interleaved manner via one or more physical channels from a test equipment.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: Embodiments of the present invention disclose a hidden fault detection circuit and a method of detecting a hidden fault using the hidden fault detection circuit. The hidden fault detection circuit comprises a function module for indicating a working state of an integrated circuit board to which the hidden fault detection circuit belongs; and a hidden fault detection module for detecting a hidden fault existing in the function module according to output of the function module. The hidden fault may be detected and eliminated according to embodiments of the present invention.

Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.

Abstract: In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.

Abstract: The present disclosure generally relates to the automated testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Specifically, the system under test may be analyzed to determine whether it is capable of properly processing control instructions and input signals and/or generating expected output control signals and additional control/feedback information. The data can then be interpreted in the grammar system and/or used as input to a fault isolation engine to determine anomalies in the system under test.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: A system includes at least one sensor and an equipment health monitoring (EHM) unit. The at least one sensor is configured to measure one or more characteristics of an asset, where the asset includes a piece of equipment. The EHM unit includes at least one sensor interface configured to receive at least one input signal associated with the asset from the sensor(s). The EHM unit also includes at least one processing unit operable to be pre-configured to identify a specified fault in the asset using the input signals and an asset-specific model that includes a combination of standard subsystem models. The EHM unit further includes at least one output interface configured to provide an indicator identifying the fault. The standard subsystem models could include standardized fault models configured to identify faults for standard assets.

Abstract: Provided is a test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, the test apparatus comprising a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a masking section that masks the acquisition of data by the data acquiring section, while the device under test is not outputting the clock signal; and a judging section that judges pass/fail of the device under test based on a result of a comparison between the data signal acquired by the data acquiring section and an expected value.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors, including if the die has a defective component. An indication of the defective functional component identification is received. A determination is made if the defective functional component is one of a plurality of similar functional components that can provide the same functionality. The other similar components can be examined to determine if they are parallel components to the defective functional component. The defective functional component is disabled if it is one of the plurality of similar functional components and another component can handle the workflow that would otherwise be assigned to the defective component. Workflow is diverted from the disabled component to other similar functional components.

Abstract: A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the LFSR and one or more save and restore registers; initializing a MISR and running test loops. Upon reaching a predetermined number of test loops, moving a signature of the MISR to a shadow register; then, performing a signature stability test by loading the initial seed to the LFSR; executing the predetermined number of BIST test loops, and comparing a resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register, wherein unloading is performed by way of serial MISR unloads and single bit XORs.