Abstract: A computerized method is disclosed for automated handling of data ingestion anomalies. The method features training a data model based on a first volume of data associated with a first time period. Thereafter, using the data model, a predictive analysis is conducted on a second volume of data associated with a second time period subsequent to the first time period to produce a predicted data ingestion volume. After, a correlative analysis between the predicted data ingestion volume and an actual data ingestion volume during the second time period is conducted to produce a prediction error. A notification is generated based on the prediction error.

Abstract: If an (i?1)-th test case which is a test case for step 1 to step (i?1) is stored, a generation control unit (130) selects a first generation scheme (M1) which uses the (i?1)-th test case to generate an i-th test case which is a test case for step 1 to step i. A test generation unit (170) generates a test case for executing an i-th step in a state where an internal state at an end of the (i?1) steps caused by execution for the (i?1)-th test case is retained, in accordance with the first generation scheme (M1). The test generation unit (170) generates the i-th test case by joining the (i?1)-th test case and the test case for the i-th step.

Abstract: A data structure is specialized in efficiently representing a key-value pair in a highly optimized way. The data structure is a pointer in a traversal graph that takes advantage of constant time traversal for all operations. The data structure has specific instructions for inserting data nodes, router nodes, and how the expansion or collapse of the graph works. The data structure can be applied where the time to get the result back is most prominent. The data structure can be used to reduce the memory footprint to reach the data that is being searched and achieve a worst-case time complexity in constant time.

Abstract: A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.

Abstract: System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

Abstract: Various embodiments for testing and verifying cloud services using computational graphs. In one embodiment, a computational graph is generated that represents corresponding actions performed by a plurality of agents and data associated with the corresponding actions. The computational graph is generated based at least in part on data describing a plurality of calls to an application programming interface (API) or a static analysis of the API. A plurality of test cases are generated for the API by analyzing the computational graph.

Abstract: An example system includes (i) a software product having a plurality of code units that accesses a database, (ii) a processor, and (iii) a non-transitory computer readable storage medium having stored thereon software tests and instructions that cause the processor to: execute the software tests on a first version of the software product; determine a first mapping between each respective software test and one or more of the code units; determine a second mapping between each respective software test and one or more data units in the database; determine that, between a second version and the first version of the software product, a particular code and data unit have changed; select, from the first and the second mappings, a set of software tests with mappings to the particular code unit or data unit; and execute the set of software tests on the second version of the software product.

Abstract: A system and method for automatically generating a dependency graph based on input and output requirements of information. The method includes obtaining, by a processing device, a list of a plurality of modules executing on one or more processing devices, the plurality of modules associated with a plurality of input requirements and a plurality of output requirements. Each module is configured to generate an output dataset of a respective output requirement of the plurality of output requirements based on an input dataset of a respective input requirement of the plurality of input requirements. The method includes determining, by the processing device, an execution order of the plurality of modules based on the plurality of input requirements and the plurality of output requirements. The method includes establishing, by the processing device, a plurality of connections between the plurality of modules based on the execution order.

Abstract: A performance testing method for determining a performance of a device under test having non-linear characteristics is disclosed. The performance testing method comprises the following steps: generating a hard clipper model of said device under test; generating a test signal having predefined properties; forwarding said test signal to the device under test, wherein the device under test generates an output signal based on said test signal; feeding said hard clipper model with said test signal, thereby generating a model output signal; and comparing said output signal to said model output signal in order to determine the performance of the device under test. Moreover, a measurement system for determining a performance of a device under test having non-linear characteristics is disclosed.

Abstract: An application-performance management (APM) system manages the performance of a service on a highly redundant high-availability platform that configures duplicate instances of hardware, software, or infrastructure components. The APM system verifies the resilience of the platform by conducting a series of tests that each measure the performance of platform components while simulating a failure path comprising one or more distinct combinations of component failures. If the service is not highly critical, the APM system simulates single-failure failure paths, but more critical services are tested by simulating multiple concurrent failures. Self-learning cognitive modules of the APM system select the failure paths to be tested and then infer from the measurements which failure paths present an unacceptably high risk of service outage. The APM system then directs downstream systems to revise the architecture to mitigate any such risks.

Abstract: A modeling system is provided. The modeling system includes a test model creator, the test model creator being adapted for providing a test model based on an integrated modeling environment and considering a domain specific profile. The system further includes a test scenario generator, the test scenario generator being adapted for providing a plurality of test scenarios based on the test model, as well as a scenario translator, the scenario translator being adapted for translating the test scenarios, into domain-specific language.

Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

Abstract: A testing device performing a worst case scenario test includes a machine learning device and the machine learning device observes data representing a test item and data representing an operation state and specifications of a manufacturing machine as state variables representing a current state of an environment. Further, the machine learning device acquires determination data representing a suitability determination result of an operation state of the manufacturing machine obtained when the test item is executed, and performs learning by using the state variables and the determination data in a state where manufacturing machine operation state data and manufacturing machine specification data are associated with test item data.

Abstract: Aspects of the present invention relates to a communications module for a door station, comprising a connection interface for communications with at least one door station in accordance with a door station communication protocol, a network interface for communications via a network in accordance with a network communication protocol, and a controller coupling the network interface and the connection interface, wherein the controller is configured to set or change the door station communications protocol of the connection interface. Further aspects of the present invention relate to a method of operating a communications module of a door station.

Abstract: Embodiments of the present invention disclose an alarm information processing method, including: acquiring, by an EMS, a first alarm information set reported by a VNFM, where the first alarm information set is generated after the VNFM performs correlation analysis on at least one piece of NFVI alarm information and at least one piece of VIM alarm information; acquiring, by the EMS, a second alarm information set reported by a VNF, where the second alarm information set includes at least one piece of VNF alarm information; and performing, by the EMS, correlation analysis on the first alarm information set and the second alarm information set, and dispatching a configured work order for alarm information that has a correlation relationship. By using the present invention, a cross-layer association between alarm information can be implemented to reduce a quantity of work orders.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for distributing a value among a plurality of accounts. One of the methods includes receiving, from a first terminal associated with a first account, a request for generating values, wherein the request comprises a sum of the values to be generated and a count of multiple second accounts, to which the values are to be distributed. The method also includes determining an average based on the sum and the count, generating multiple values in response to the request, the generated values comprising one or more value pairs and zero or one individual value, wherein a count of the generated values equals the count of second accounts in the request. The method further includes distributing the multiple values to the second accounts, wherein each of the second accounts is associated with a second terminal.

Abstract: Techniques for creating a nomenclature to represent one or more groups within a process are provided. The techniques include obtaining a process, wherein the process comprises one or more groups, and creating a nomenclature to represent the one or more groups, wherein the nomenclature facilitates usability of the process in at least one of an operation and design environment. Techniques are also provided for generating a database of one or more processes, wherein each process is represented by a nomenclature.

Abstract: A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.

Abstract: Provided are a method and a system capable of efficiently detecting security vulnerability of program. The system for detecting the security vulnerability according to an embodiment of the present invention includes a vulnerability detecting module that acquires crash information, a binary analysis module that determines priority of binary information and whether to execute the route detection, and a route detecting module that executes the route detection to generate a new test case.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement defect solutions. In one aspect, a method includes receiving a log file and testing results generated from a code base for an application; processing the log file through a pattern-mining algorithm to determine a usage pattern of code modules within the code base; clustering defects from the testing results based on a respective functionality of the application reported within each of the defects; generating testing prioritizations for test cases for the application by assigning weightages to the test cases based on the clusters of defects and the usage pattern of the code modules within the code base; sequencing a set of the test cases based on the test prioritizations; and transmitting the sequence to a test execution engine.

Abstract: Tools and techniques are described to detect possible holes in automated testing of software under development. Full line coverage by tests does not necessarily indicate actual coverage of execution scenarios, e.g., condition coverage, decision coverage, and other kinds of execution scenario coverage may be lacking even when all source code statements are nominally covered. When source code changes are submitted, and corresponding test-sets remain unchanged, users are notified that adequate testing is not assured by the current test-set. Testing assurance code in a development tool chain may flag a pull request, test-set, or source code submission to indicate a lack of testing assurance. In some cases, an assurance-enhanced tool may require that new or different tests be provided with updated source code as a prerequisite for that source code to be accepted for inclusion in a repository or a build, for example.

Abstract: Systems and methods for GPU command streaming in accordance with embodiments of the invention are disclosed. In one embodiment, a method for receiving and processing an encoded GPU command stream includes obtaining an encoded GPU command stream from at least one hosting server system using a rendering system, decoding the encoded GPU command stream into a decoded GPU command stream using the rendering system, obtaining a set of high density assets using the rendering system, mapping a first set of runtime generated identifiers to a second set of runtime generated identifiers using the rendering system so that the second set of runtime generated identifiers is correctly associated with the set of GPU commands, and producing a set of images using the rendering system by processing the decoded GPU command stream and the set of high density assets using a processor.

Abstract: In a method of testing a software item, an error condition may occur during an automated test of a software item. In response to the error, the test remains in an active state. An alteration to the test is accepted. Once altered, a test may continue using the altered test.

Abstract: A method and system for improving automated software testing is provided. The method includes identifying software elements of a software test specification executed by a hardware device of an IT system. Existing software objects associated with a software module for testing are mapped to the identified software elements and with physical operational values of the software module. The identified software elements of the software test specification and associated software parameters are verified and software values of the identified software elements are extracted. The software values are executed with respect to a library database and the software test specification in executed with respect to the software module. In response, software module test software for operationally testing software modules and associated hardware devices is generated resulting in improved operation of the software modules and associated hardware devices.

Abstract: A reliability and performance analysis system is disclosed. The reliability and performance analysis system includes a logic analyzer and a server. The logic analyzer includes a set of probes capable of retrieving signals of a digital device. The retrieved signals are integrated and stored into a storage module of the logic analyzer. The retrieved signals are then transmitted to a remote server which are utilized to select specific signals to analyze the reliability and performance of the digital device. The storage module can increase the stability of the logic analyzer such that the logic analyzer can proceed a long-term signal retrieving process and a user can obtain an analysis result by connecting to the server directly.

Abstract: A processor includes logic to implement a reconfigurable test access port with finite state machine control. A plurality of test access ports may each include a finite state machine for enabling implementation of different test interfaces to the processor, including JTAG IEEE 1149.1, JTAG IEEE 1149.7, and serial wire debug.

Abstract: A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.

Abstract: A machine learning engine is configured to create a customized anomaly detector for use by a system resource, such as a virtual machine instance running specific operations. Anomalies are determined by comparing aspects of current data to “normal” baseline data indicating a normal range of performance and operation of a system resource. Operation by a system resource that is outside of this normal range of performance and operation may be considered an anomaly. The machine learning engine may be used to create customized monitoring that detects anomalies in operation and/or performance of a system resource based on at least some custom parameters that are unique to the particular system that is to be monitored. The parameters may include operational parameters, which may be selected specifically for the system to be monitored. The parameters may also include some technical parameters which are used by many other systems to monitor hardware performance.

Abstract: An electronic device includes a processor and a memory coupled to the processor and storing computer readable program code that when executed by the processor causes the processor to perform operations including generating, at given time intervals, a plurality of topology graphs that correspond to a service chain that comprises a plurality of virtual network functions (VNFs) and that is operating in a software defined network (SDN)/network function virtualization (NFV) computing environment, each of the plurality of topology graphs corresponding to a different one of the time intervals. Operations may include comparing a first one of the plurality of topology graphs that is received at a first time to a second one of the plurality of topology graphs that is received at a second time that is after the first time to determine if the service chain has a fault.

Abstract: Methods and apparatuses are described for determining a small subset of tests that provides substantially the same coverage as the set of tests. During operation, a system (e.g., a computer system) can determine a set of tests by, for each object in a set of objects, selecting up to a pre-determined number of tests that provide test coverage for the object. Next, the system can determine a subset of tests by iteratively performing a loop, which can comprise: selecting a test in the set of tests; removing, from the set of objects, one or more objects that are covered by the selected test; and optionally removing, from the set of tests, one or more tests that do not cover any objects in the remaining set of objects. The system can terminate the loop after a termination condition is met and report the selected tests as the subset of tests.

Abstract: The invention relates to an individual sorting device (10) for sorting tablets which have been pressed by a tableting machine using press punches. The individual sorting device (10) comprises a tablet feed (20), a pressing force signal input (30) for receiving pressing force signals which can be assigned to the fed tablets, a programmable control unit (40), and a storage unit (50). The individual sorting device (10) is suitable for separating tablets to which an unacceptable pressing force signal can be assigned, said unacceptable pressing force signal lying outside of an accepted pressing force range, from tablets to which an acceptable pressing force signal can be assigned, said acceptable pressing force signal lying within the accepted pressing force range.

Abstract: A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.

Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.

Abstract: Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to locate transaction-level events in the set of signal for one or more communication channels. Data indicating locations of the set of transaction-level events is output by the computer system.

Abstract: Systems and methods for implementing security mechanisms in integrated devices and related structures. This method can include validating a device ID, generating a random value based on selected seed parameters, performing logic operations from hardware using the random value, and validating the integrated device based on logic operations from software using the random value. The system can include executable instructions for performing the method in a computing system. Various embodiments of the present invention represent several implementations of a security mechanism for integrated devices. These implementations provide several levels of encryption or protection of integrated devices, which can be tailored depending on the hardware and/or software requirements of specific applications.

Abstract: A circuit verifying apparatus, which calculates code coverage of a measurement-target logic circuit written in a hardware description language, including: a coverage observing unit which measures whether a code corresponding to a measurement-target signal extracted from each of plural observation points, which are arranged inside the measurement-target logic circuit, is carried out or not; and a coverage collecting unit which collects measurement results acquired by the coverage observing unit, and measures quantitatively a ratio of tested codes to whole codes which describe the measurement-target logic circuit, and outputs the ratio.

Abstract: A method of determining test data for use in testing a software. The method includes determining that at least part of a software structure of the software to be tested is similar to, or the same as, a software structure associated with a defect. The method also includes retrieving information regarding operational circumstances for causing the defect in the software associated with the defect. The method further includes creating, based upon the retrieved information, test data for testing the software to be tested.

Abstract: Some embodiments include apparatuses and methods having a memory structure included in a memory device and a control unit included in the memory device. The control unit can provide information obtained from the memory structure during a memory operation to a host device (e.g., a processor) in response to a command from the host device. If the control unit receives a notification from the host device indicating that the host device has detected an error in the information obtained from the memory structure, then a repair unit included in the memory device performs a memory repair operation to repair a portion in the memory structure.

Abstract: A method for automated error detection and verification of software comprises providing a model of the software, the model including one or more model inputs and one or more model outputs, and a plurality of blocks embedded within the model each with an associated block type, the block types each having a plurality of associated block-level requirements. The method further comprises topologically propagating from the model inputs, a range of signal values or variable values, and error bounds, across computational semantics of all the blocks to the model outputs. Each behavior pivot value for a given block is identified and examined to determine if modifying or extending the propagated range by the error bound will or may cause a signal value to fall on either side of the behavioral pivot value. All occurrences of the signal value that will or may fall on either side of the behavioral pivot value are reported.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Abstract: An advanced fault simulator that can audit the fault coverage of large-scale integrated circuit (IC) designs is described herein. Specifically, an IC design's Hardware Description Language and/or Electronic System-Level source files are compiled into a database, stuck-at, transition and/or inter-process communication faults for the design are generated and equivalent faults are collapsed. Furthermore, all faults are partitioned into disjointed fault sets, and a set of worker threads are created to process those fault sets concurrently. The worker threads can run either locally on a multiprocessor platform, or remotely on different computers that are connected via an intranet and/or the Internet. Moreover, each worker thread can create a plurality of child threads to further accelerate the multithreaded concurrent fault simulation of the IC design. After the simulation is finished, a fault report is generated that depicts the fault coverage of the IC design and all undetected and detected faults.

Abstract: Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design are analyzed to determine information of potential logic relationship between the scan cells. The information of potential logic relationship between the scan cells may comprise information of fan-in cones for the scan cells. Based at least in part on the information of potential logic relationship between the scan cells, scan chains may be formed. The formation of scan chains may be further based on layout information of the circuit design. The formation of scan chains may be further based on compactor information of the circuit design.

Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.

Abstract: Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.

Abstract: A test pattern generating apparatus that generates a test pattern to be communicated with a device under test having a plurality of terminals, the test pattern generating apparatus comprising a primitive generating section that generates a cycle primitive indicating a signal pattern to be communicated with each of the terminals during a base cycle, based on instructions from a user; a device cycle generating section that generates a device cycle indicating signal patterns of a plurality of base cycles, by arranging a plurality of the cycle primitives based on instructions from the user; and a sequence generating section that generates a sequence of the test pattern to be supplied to the device under test, by arranging a plurality of the device cycles based on instructions from the user.

Abstract: Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.

Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.

Abstract: A system and methods for reasonable formal verification provides a user with coverage information that is used for verification signoff. The coverage is calculated based on formal analysis techniques and is provided to the user in terms of design-centric metrics rather than formal-centric metrics. Design-centric metrics include the likes of a number of reads from or writes to memories and a number of bit changes for counters, among many others. Accordingly, a setup for failure (SFF) function and a trigger the failure (TTF) function take place. During SFF formal analysis is applied in an attempt to reach a set of states close enough to suspected failure states. During TTF formal analysis is applied, starting from the SFF states, to search for a state violating a predetermined property. If results are inconclusive the user is provided with a design-centric coverage metric that can be used in signoff.

Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.

Abstract: A position-based scheduling capability supports interaction between one or more user applications and a scheduler for performing testing via a scan chain of a unit under test. The scheduler receives access requests from one or more user applications, where each access request is a request for access to a segment of the scan chain, respectively. The scheduler determines scheduling of the access requests using a circuit model configured to represent an ordering of the segments of the scan chain. The scheduler may provide the access responses to the user application(s) from which the access requests are received, thereby enabling the user application(s) to issue test operations toward a processor configured to generate test data to be applied to the scan chain. The scheduler may obtain the test operations and send the test operations toward a processor configured to generate test data to be applied to the scan chain.