Simulation Patents (Class 714/741)
  • Patent number: 10305755
    Abstract: A reliability and performance analysis system is disclosed. The reliability and performance analysis system includes a logic analyzer and a server. The logic analyzer includes a set of probes capable of retrieving signals of a digital device. The retrieved signals are integrated and stored into a storage module of the logic analyzer. The retrieved signals are then transmitted to a remote server which are utilized to select specific signals to analyze the reliability and performance of the digital device. The storage module can increase the stability of the logic analyzer such that the logic analyzer can proceed a long-term signal retrieving process and a user can obtain an analysis result by connecting to the server directly.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 28, 2019
    Assignee: ZEROPLUS TECHNOLOGY CO., LTD.
    Inventor: Chiu-Hao Cheng
  • Patent number: 10267850
    Abstract: A processor includes logic to implement a reconfigurable test access port with finite state machine control. A plurality of test access ports may each include a finite state machine for enabling implementation of different test interfaces to the processor, including JTAG IEEE 1149.1, JTAG IEEE 1149.7, and serial wire debug.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventor: Cheng Mao
  • Patent number: 10151791
    Abstract: A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: December 11, 2018
    Assignee: Advanced Testing Technologies, Inc.
    Inventors: Robert Spinner, Eli Levi, Jim McKenna, William Harold Leippe, William Biagiotti, Richard Engel
  • Patent number: 10102056
    Abstract: A machine learning engine is configured to create a customized anomaly detector for use by a system resource, such as a virtual machine instance running specific operations. Anomalies are determined by comparing aspects of current data to “normal” baseline data indicating a normal range of performance and operation of a system resource. Operation by a system resource that is outside of this normal range of performance and operation may be considered an anomaly. The machine learning engine may be used to create customized monitoring that detects anomalies in operation and/or performance of a system resource based on at least some custom parameters that are unique to the particular system that is to be monitored. The parameters may include operational parameters, which may be selected specifically for the system to be monitored. The parameters may also include some technical parameters which are used by many other systems to monitor hardware performance.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 16, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Anton Vladilenovich Goldberg
  • Patent number: 10057112
    Abstract: An electronic device includes a processor and a memory coupled to the processor and storing computer readable program code that when executed by the processor causes the processor to perform operations including generating, at given time intervals, a plurality of topology graphs that correspond to a service chain that comprises a plurality of virtual network functions (VNFs) and that is operating in a software defined network (SDN)/network function virtualization (NFV) computing environment, each of the plurality of topology graphs corresponding to a different one of the time intervals. Operations may include comparing a first one of the plurality of topology graphs that is received at a first time to a second one of the plurality of topology graphs that is received at a second time that is after the first time to determine if the service chain has a fault.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 21, 2018
    Assignee: CA, INC.
    Inventors: Michael Paul Shevenell, Preetdeep Kumar, Ravindra Kumar Puli
  • Patent number: 10042741
    Abstract: Methods and apparatuses are described for determining a small subset of tests that provides substantially the same coverage as the set of tests. During operation, a system (e.g., a computer system) can determine a set of tests by, for each object in a set of objects, selecting up to a pre-determined number of tests that provide test coverage for the object. Next, the system can determine a subset of tests by iteratively performing a loop, which can comprise: selecting a test in the set of tests; removing, from the set of objects, one or more objects that are covered by the selected test; and optionally removing, from the set of tests, one or more tests that do not cover any objects in the remaining set of objects. The system can terminate the loop after a termination condition is met and report the selected tests as the subset of tests.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: August 7, 2018
    Assignee: SYNOPSYS, INC.
    Inventor: Vernon A. Lee
  • Patent number: 9950347
    Abstract: The invention relates to an individual sorting device (10) for sorting tablets which have been pressed by a tableting machine using press punches. The individual sorting device (10) comprises a tablet feed (20), a pressing force signal input (30) for receiving pressing force signals which can be assigned to the fed tablets, a programmable control unit (40), and a storage unit (50). The individual sorting device (10) is suitable for separating tablets to which an unacceptable pressing force signal can be assigned, said unacceptable pressing force signal lying outside of an accepted pressing force range, from tablets to which an acceptable pressing force signal can be assigned, said acceptable pressing force signal lying within the accepted pressing force range.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 24, 2018
    Assignee: KORSCH AG
    Inventors: Walter Hegel, Arno Rathmann
  • Patent number: 9739827
    Abstract: A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 22, 2017
    Assignee: Advanced Testing Technologies, Inc.
    Inventors: Robert Spinner, Eli Levi, Jim McKenna, William Harold Leippe, William Biagiotti, Richard Engel
  • Patent number: 9720793
    Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
  • Patent number: 9678150
    Abstract: Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to locate transaction-level events in the set of signal for one or more communication channels. Data indicating locations of the set of transaction-level events is output by the computer system.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: June 13, 2017
    Assignee: XILINX, INC.
    Inventors: Graham F. Schelle, Yi-Hua E. Yang, Philip B. James-Roxby, Paul R. Schumacher, Patrick Lysaght
  • Patent number: 9418247
    Abstract: Systems and methods for implementing security mechanisms in integrated devices and related structures. This method can include validating a device ID, generating a random value based on selected seed parameters, performing logic operations from hardware using the random value, and validating the integrated device based on logic operations from software using the random value. The system can include executable instructions for performing the method in a computing system. Various embodiments of the present invention represent several implementations of a security mechanism for integrated devices. These implementations provide several levels of encryption or protection of integrated devices, which can be tailored depending on the hardware and/or software requirements of specific applications.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: August 16, 2016
    Assignee: MCUBE INC.
    Inventors: Sanjay Bhandari, Tony Maraldo
  • Patent number: 9280622
    Abstract: A circuit verifying apparatus, which calculates code coverage of a measurement-target logic circuit written in a hardware description language, including: a coverage observing unit which measures whether a code corresponding to a measurement-target signal extracted from each of plural observation points, which are arranged inside the measurement-target logic circuit, is carried out or not; and a coverage collecting unit which collects measurement results acquired by the coverage observing unit, and measures quantitatively a ratio of tested codes to whole codes which describe the measurement-target logic circuit, and outputs the ratio.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: March 8, 2016
    Assignee: NEC CORPORATION
    Inventor: Shusaku Uchibori
  • Patent number: 9244821
    Abstract: A method of determining test data for use in testing a software. The method includes determining that at least part of a software structure of the software to be tested is similar to, or the same as, a software structure associated with a defect. The method also includes retrieving information regarding operational circumstances for causing the defect in the software associated with the defect. The method further includes creating, based upon the retrieved information, test data for testing the software to be tested.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 26, 2016
    Assignee: Accenture Global Services Limited
    Inventor: Basil Eljuse
  • Patent number: 9135100
    Abstract: Some embodiments include apparatuses and methods having a memory structure included in a memory device and a control unit included in the memory device. The control unit can provide information obtained from the memory structure during a memory operation to a host device (e.g., a processor) in response to a command from the host device. If the control unit receives a notification from the host device indicating that the host device has detected an error in the information obtained from the memory structure, then a repair unit included in the memory device performs a memory repair operation to repair a portion in the memory structure.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 15, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Kurt Ware
  • Patent number: 9098619
    Abstract: A method for automated error detection and verification of software comprises providing a model of the software, the model including one or more model inputs and one or more model outputs, and a plurality of blocks embedded within the model each with an associated block type, the block types each having a plurality of associated block-level requirements. The method further comprises topologically propagating from the model inputs, a range of signal values or variable values, and error bounds, across computational semantics of all the blocks to the model outputs. Each behavior pivot value for a given block is identified and examined to determine if modifying or extending the propagated range by the error bound will or may cause a signal value to fall on either side of the behavioral pivot value. All occurrences of the signal value that will or may fall on either side of the behavioral pivot value are reported.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: August 4, 2015
    Assignee: Honeywell International Inc.
    Inventors: Devesh Bhatt, David V. Oglesby, Kirk A. Schloegel, Gabor Madl
  • Patent number: 9086454
    Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: July 21, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
  • Patent number: 9032266
    Abstract: An advanced fault simulator that can audit the fault coverage of large-scale integrated circuit (IC) designs is described herein. Specifically, an IC design's Hardware Description Language and/or Electronic System-Level source files are compiled into a database, stuck-at, transition and/or inter-process communication faults for the design are generated and equivalent faults are collapsed. Furthermore, all faults are partitioned into disjointed fault sets, and a set of worker threads are created to process those fault sets concurrently. The worker threads can run either locally on a multiprocessor platform, or remotely on different computers that are connected via an intranet and/or the Internet. Moreover, each worker thread can create a plurality of child threads to further accelerate the multithreaded concurrent fault simulation of the IC design. After the simulation is finished, a fault report is generated that depicts the fault coverage of the IC design and all undetected and detected faults.
    Type: Grant
    Filed: June 17, 2012
    Date of Patent: May 12, 2015
    Inventor: Terence Wai-Kwok Chan
  • Patent number: 9015543
    Abstract: Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design are analyzed to determine information of potential logic relationship between the scan cells. The information of potential logic relationship between the scan cells may comprise information of fan-in cones for the scan cells. Based at least in part on the information of potential logic relationship between the scan cells, scan chains may be formed. The formation of scan chains may be further based on layout information of the circuit design. The formation of scan chains may be further based on compactor information of the circuit design.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: April 21, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai
  • Patent number: 8977921
    Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: March 10, 2015
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Hong Ho, Daniel Smathers
  • Patent number: 8972785
    Abstract: Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Brian C. Kahne
  • Patent number: 8904247
    Abstract: A test pattern generating apparatus that generates a test pattern to be communicated with a device under test having a plurality of terminals, the test pattern generating apparatus comprising a primitive generating section that generates a cycle primitive indicating a signal pattern to be communicated with each of the terminals during a base cycle, based on instructions from a user; a device cycle generating section that generates a device cycle indicating signal patterns of a plurality of base cycles, by arranging a plurality of the cycle primitives based on instructions from the user; and a sequence generating section that generates a sequence of the test pattern to be supplied to the device under test, by arranging a plurality of the device cycles based on instructions from the user.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: December 2, 2014
    Assignee: Advantest Corporation
    Inventor: Takuya Toyoda
  • Patent number: 8812922
    Abstract: Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: August 19, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Wei Zou, Huaxing Tang, Wu-Tung Cheng
  • Patent number: 8813019
    Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: August 19, 2014
    Assignee: NVIDIA Corporation
    Inventors: Avinash Rath, Sanjith Sleeba, Ashish Kumar
  • Patent number: 8806401
    Abstract: A system and methods for reasonable formal verification provides a user with coverage information that is used for verification signoff. The coverage is calculated based on formal analysis techniques and is provided to the user in terms of design-centric metrics rather than formal-centric metrics. Design-centric metrics include the likes of a number of reads from or writes to memories and a number of bit changes for counters, among many others. Accordingly, a setup for failure (SFF) function and a trigger the failure (TTF) function take place. During SFF formal analysis is applied in an attempt to reach a set of states close enough to suspected failure states. During TTF formal analysis is applied, starting from the SFF states, to search for a state violating a predetermined property. If results are inconclusive the user is provided with a design-centric coverage metric that can be used in signoff.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: August 12, 2014
    Assignee: Atrenta, Inc.
    Inventors: Mohamad Shaker Sarwary, Maher Mneimneh
  • Patent number: 8799732
    Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif
  • Patent number: 8775884
    Abstract: A position-based scheduling capability supports interaction between one or more user applications and a scheduler for performing testing via a scan chain of a unit under test. The scheduler receives access requests from one or more user applications, where each access request is a request for access to a segment of the scan chain, respectively. The scheduler determines scheduling of the access requests using a circuit model configured to represent an ordering of the segments of the scan chain. The scheduler may provide the access responses to the user application(s) from which the access requests are received, thereby enabling the user application(s) to issue test operations toward a processor configured to generate test data to be applied to the scan chain. The scheduler may obtain the test operations and send the test operations toward a processor configured to generate test data to be applied to the scan chain.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: July 8, 2014
    Assignee: Alcatel Lucent
    Inventors: Michele Portolan, Bradford Van Treuren, Suresh Goyal
  • Patent number: 8762113
    Abstract: A method includes capturing data that is representative of actions performed by each of a plurality of human user operated clients as they interact with an online software application, loading at least one or more portions of the captured data into one or more automated simulation clients, and using the one or more automated simulation clients to perform load testing of an online server system. A system includes a data capturing stage, one or more automated simulation clients, and a configuration stage.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 24, 2014
    Assignee: Sony Computer Entertainment America LLC
    Inventors: Sreelata Santhosh, Mark Vaden, Brian Fernandes
  • Publication number: 20140143625
    Abstract: A failure prediction device generates a failure predictor pattern in accordance with previous cases of failure that has occurred in a first system, the failure predictor pattern being used to detect a predictor of failure in the first system configuration. When a system configuration is changed from the first system configuration to a second system configuration, the failure prediction device calculates the difference information that indicates the difference between the system configurations by using the number of changes that is the accumulated number of times that a change of the configuration item which is included in a system is executed. The failure prediction device determines, in accordance with the calculated difference information, whether the failure predictor pattern is applicable to the detection of a predictor of failure in the second system configuration.
    Type: Application
    Filed: August 28, 2013
    Publication date: May 22, 2014
    Applicant: FUJITSU LIMITED
    Inventors: YUKIHIRO WATANABE, Hiroshi OTSUKA, YASUHIDE MATSUMOTO
  • Patent number: 8732838
    Abstract: Evaluating a threat model for structural validity and descriptive completeness. A threat modeling application provides a progress factor or other overall score associated with the structural validity and descriptive completeness of the threat model being evaluated. The structural validity is evaluated based on a data flow diagram associated with the threat model. The descriptive completeness is evaluated by reviewing descriptions of threat types in the threat model. The progress factor encourages modelers to provide effective models to a model reviewer, thus saving time for the model reviewer.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: May 20, 2014
    Assignee: Microsoft Corporation
    Inventors: Ivan Medvedev, Adam Shostack, Lawrence William Osterman
  • Patent number: 8719651
    Abstract: An apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan chain is generated from at least a portion of the flip flops in the first group. At least one scan chain is generated from at least a portion of the flip flops in the second group.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: May 6, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Nilabha Dev, Sameer Chakravarthy Chillarige, Shaleen Bhabu
  • Patent number: 8713391
    Abstract: A system for testing an integrated circuit, in which the system includes a deserializer, a frame sync module, and a diagnostic module. The deserializer is external to the integrated circuit and is configured to receive messages in a serial data format, wherein the messages include test results associated with the integrated circuit, and deserialize the messages into data frames. The frame sync module is configured to provide control code based on the data frames, wherein the control code includes, in a digital format, status information associated with the messages deserialized into the data frames. The diagnostic module is configured to generate, based on the control code, diagnostic data associated with states of the integrated circuit.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: April 29, 2014
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Ho, Daniel Smathers
  • Patent number: 8707232
    Abstract: Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: April 22, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Huaxing Tang, Wu-Tung J. Cheng, Robert Brady Benware, Xiaoxin Fan
  • Patent number: 8707113
    Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: April 22, 2014
    Assignee: Agilent Technologies, Inc.
    Inventors: Douglas Manley, Randy A. Coverstone
  • Patent number: 8707221
    Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analyses to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 22, 2014
    Assignee: Flextronics AP, LLC
    Inventor: Michael Anthony Durkan
  • Patent number: 8689069
    Abstract: Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: April 1, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke
  • Patent number: 8689070
    Abstract: Scan chain diagnosis techniques are disclosed. Faulty scan chains are modeled and scan patterns are masked to filter out loading-caused failures. By simulating the masked scan patterns, failing probabilities are determined for cells on a faulty scan chain. One or more defective cells are identified based upon the failing probability information. A noise filtering system such as the one based upon adaptive feedback may be adopted for the identification process.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: April 1, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai
  • Patent number: 8683282
    Abstract: A computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yoav Avraham Katz, Michal Rimon, Elad Yom-Tov, Avi Ziv
  • Patent number: 8661305
    Abstract: The various embodiments of the present invention provide a method for automatically generating a unique set of test vectors for verifying design intent of integrated circuit chips. The method includes obtaining configuration parameters associated with a plurality of integrated circuit chips, generating an Executable Verification Plan pertaining to the configuration parameters of a plurality of integrated circuit chips in one or more execution PCs (EPs), creating a plurality of data structures corresponding to the configuration parameters, communicating the data structures created to a DCMS server, mapping the data structures of the Execution PCs with one or more data structures present in a database of the DCMS server, customizing the executable verification plan based on changes in the configurations of the integrated circuit chips, generating a unique set of test vectors based on mapping of the data structures and performing automatic design verification of the plurality of integrated circuit chips.
    Type: Grant
    Filed: July 10, 2011
    Date of Patent: February 25, 2014
    Inventors: Ravishankar Rajarao, Chinthana Ednad
  • Patent number: 8635566
    Abstract: A circuit design is simulated on a computing system. Simulating the circuit design includes selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design. A parity error is inserted in the first memory location during simulation of the design.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 21, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Christopher E. Hsiong
  • Patent number: 8621301
    Abstract: A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches).
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 31, 2013
    Assignee: Alcatel Lucent
    Inventors: Suresh Goyal, Michele Portolan, Bradford Van Treuren
  • Patent number: 8621305
    Abstract: Methods and apparatus are provided for determining whether a built-in-test fault code (BITFC) data sequence generated by a built-in-test (BIT) of a particular module of a complex system is indicative of an actual fault condition. A regression function is generated for the particular module based on stored BITFC data sequences generated by the BIT and stored repair data for that module from a fault history database. Later, during operation of the particular module, the BIT generates a new BITFC data sequence. A processor can then load the new BITFC data sequence and execute the regression function with respect to the new BITFC data sequence to determine whether the new BITFC data sequence is indicative of an actual fault condition at the particular module or is indicative of a false fault condition at the particular module.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 31, 2013
    Assignee: Honeywell International Inc.
    Inventors: Joel Bock, Phil Scandura, Raj Mohan Bharadwaj
  • Patent number: 8615724
    Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analysis to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: December 24, 2013
    Assignee: Flextronics AP LLC
    Inventor: Michael Anthony Durkan
  • Patent number: 8572448
    Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: October 29, 2013
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Hong Ho, Daniel Smathers
  • Patent number: 8560900
    Abstract: Adjusting receiving parameters without known data is disclosed, including: receiving an indication of whether data associated with a sector is error correcting code (ECC) uncorrectable; in the event that the indication is that the data is uncorrectable, determining a plurality of statistical information outputs using a detector; and using at least a subset of the plurality of statistical information outputs to adjust a set of one or more receiver parameters.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: October 15, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Jason Bellorado, Marcus Marrow, Yu Kou
  • Patent number: 8560893
    Abstract: A method and system are provided for automatically generating executable system-level tests from an initial action or partially specified scenario by accumulating necessary complement actions and forming a set of constraints required by the initial action and the necessary complement actions. The set of constraints is solved by a constraint solving engine to provide an at least partial sequence of the actions and parameters thereto that satisfies the set of constraints. The sequence of actions that comply with the set of constraints are used to generate an executable system-level test code.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: October 15, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yoav Hollander, Efrat Gavish, Vitaly Lagoon, Matan Vax
  • Patent number: 8549372
    Abstract: A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: October 1, 2013
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski
  • Patent number: 8527826
    Abstract: A computer-implemented method of verifying logic in a simulation-based behavioral latch model by performing actions including: inserting a value checking module in the behavioral latch model, the value checking module connected to one of a set of latches outside of a scan chain within the behavioral latch model; comparing a value of the one of the set of latches outside of the scan chain with a delta value for the one of the set of latches outside of the scan chain; and providing an error message in response to determining the value and the delta value are distinct.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nutan J. P. Kumar, Srinivas V. N. Polisetty
  • Patent number: 8516356
    Abstract: Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: August 20, 2013
    Assignee: Infineon Technologies AG
    Inventors: Simon Brewerton, Neil Hastie
  • Patent number: 8499209
    Abstract: Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: July 30, 2013
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Elham K. Moghaddam, Nilanjan Mukherjee, Mark A Kassab, Xijiang Lin
  • Patent number: RE44487
    Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 10, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: William A. Hughes, Chen-Ping Yang, Greggory D. Donley, Michael K. Fertig