Abstract: A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Abstract: A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.

Abstract: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.

Abstract: A system and method of testing a wireless communication device during device production comprises designating as a data log buffer when the device is being produced, at least part of random access memory (RAM) of the device that is allocated for virtual machine and/or application usage when the device is operational; and testing the device and storing test log data in the buffer. After testing, the data can be obtained from the buffer and processed using a debugging and log analysis tool.

Abstract: An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.

Abstract: An auto-trim circuit that sets trim bits for an integrated circuit includes a coarse bit calibration circuit for determining a first portion of the trim bits as a set of coarse bits, and a fine bit calibration circuit for determining a second portion of the trim bits as a set of fine bits wherein said fine bits.

Abstract: A fault location estimation system includes single-fault-assumed diagnostic unit nodes; error-observation node basis candidate classification unit; inclusion fault candidate group selection unit; inter-pattern overlapping unit; and multiple-fault simulation checking unit.

Abstract: A system for making real-time predictions about an arc flash event on an electrical system is disclosed. The system includes a data acquisition component, an analytics server and a client terminal. The data acquisition component is communicatively connected to a sensor configured to acquire real-time data output from the electrical system. The analytics server is communicatively connected to the data acquisition component and is comprised of a virtual system modeling engine, an analytics engine and an arc flash simulation engine.

Abstract: A method, apparatus and computer program product are provided for use in a system that includes one or more processors, and multiple threads that are respectively associated with the one or more processors. One embodiment of the invention is directed to a method that includes the steps of generating one or more test cases, wherein each test case comprises a specified set of instructions in a specified order, and defining a plurality of thread hardware allocations, each corresponding to a different one of the threads. The thread hardware allocation corresponding to a given thread comprises a set of processor hardware resources that are allocated to the given thread for use in executing test cases. The method further includes executing a particular one of the test cases on a first thread hardware allocation, in order to provide a first set of test data, and thereafter executing the particular test case using a second thread hardware allocation, in order to provide a second set of test data.

Abstract: A method for testing the safety automation logic used in a manufacturing cell includes recording control signals of a safety-related component such as an E-Stop, light curtain, gate lock, or a safety mat using a host machine, and then disconnecting the component from the host machine. The recorded test signals are transmitted to an automation controller in accordance with a test scenario from a test scenario generator module (TSGM) to emulate operation of the component. The automation logic may be certified using the playback of the recorded test signals. A system for testing the safety automation logic includes the controller, host machine, and TSGM. The host machine records the control signals and plays back the test signals on the controller to emulate operation of the component. The automation control logic may be certified using the test signals, e.g., by comparing these to the test specification or standard.

Abstract: A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in the failing test; correlating the signal events to coverage bins to generate a sequence of coverage bins; creating cross coverage event sequence bins based on the sequence of coverage bins; and outputting the created coverage event sequence bins for testing the device.

Abstract: A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip.

Abstract: A verification scenario generation device including a first input unit which accepts input of a device list showing devices connected with a circuit to be verified, parameter setting information for the devices, and a test bench combination list corresponding to the devices, a test bench library which holds the test bench, and a test bench generation unit to generate a test bench for verification, a scenario template generation unit which generates a scenario template. The device further includes a data combination list generation unit which generates a combination list of data kinds, a verification item generation unit which generates verification items based on a combination list of the data kind and a combination list of the test bench input, and a verification scenario generation unit which generates a verification scenario based on the scenario template, and the verification items.

Abstract: A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes estimating or calculating a maximum scan chain length L and creating a maximum number of scan chains of length L in each hierarchical block. The method further includes distributing remaining scan bits in each hierarchical block into additional scan chains, and creating chip-level scan chains by using the scan chains of maximum length L and by forming additional chip-level scan chains of maximum length L by distributing the additional scan chains of maximum length LR, plus any remaining top-level scan bits, among the additional chip-level scan chains of maximum length L.

Abstract: An electronic device includes a scan-based circuit that includes a combinational decompressor, a combinational compressor, scan chains, and logic which typically includes a number of storage elements. Cycle time normally needed to shift data into or out of a scan cell to/from an external interface of the electronic device is reduced by use of one or more additional storage element(s) located between the external interface and one of the combinational elements (decompressor/compressor). The one or more additional storage element(s) form a pipeline that shifts compressed data in stages, across small portions of an otherwise long path between the external interface and one of the combinational elements. Staged shifting causes the limit on cycle time to drop to the longest time required to traverse a stage of the pipeline. The reduced cycle time in turn enables a corresponding increase in shift frequency.

Abstract: A computer implemented method of verifying events generated by an agent includes detecting an input signal at an input of the agent, generating an expected output signal based at least in part on the input signal, detecting an output signal at an output of the agent, wherein the output signal is a translation of the input signal generated by the agent, and comparing the output signal with the expected output signal to verify whether the agent produced the output signal correctly based on the input signal.

Abstract: The present invention provides a circuit state scan-chain for emulating and verifying integrated circuit design, a data collection system and an emulation and verification method using the scan-chain. The said integrated circuit includes a number of registers and the corresponding input terminal combinational logic and output terminal combinational logic. The construction of the said scan-chain includes the first multiplex module and the second multiplex module arranged with regard to each register, changing the operation mode of the said integrated circuit by controlling the first multiplex module and the second multiplex module, enabling the said integrated circuit to switch among the normal mode, holding mode and snapshot mode, and enabling the registers to form a scan-chain loop in the snapshot mode.

Abstract: A method and a system for defining groups of tests that may be concurrently performed or overlapped are provided. Channel-independent test groups are determined such that each group includes tests that the input/output channels may be utilized simultaneously without conflicts. The channel-independent test groups are divided into block-under-test (BUT) conflict test groups and total-independence test groups. The total-independence test groups may be performed concurrently. Performance of the BUT-conflict test groups may be overlapped such that the input/output channels are used concurrently, but the execution of the tests by the blocks of the device-under-test (DUT) is performed sequentially.

Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract: A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

Abstract: A computer network for providing a test environment is disclosed. The computer network may include at least one simulated network for simulating at least a portion of the infrastructure of a production network. The computer network may further include a network simulation module in communication with the simulated network for simulating at least one parameter of the production network, and a plurality of client simulation computers in communication with the simulated network via the network simulation module. Each client simulation computer may be configured to replicate at least one of a hardware configuration and a software configuration of a production network client.

Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing.

Abstract: An apparatus and method to design an integrated circuit (IC) to reduce the toggling during shifting in and shifting out of test patterns in a IC having scan chains, while maintaining random-like filling of the “don't cares” of a test set. An average pattern of test patterns of a test set is found for both cases of where the test set is fully specified and not fully specified, inverters are judiciously inserted into the scan path and each test pattern is then modified by XOR-ing it with the average test pattern to produce a modified test pattern, which produces less toggling, translating to less power consumption. Further, the random filling of don't cares, as opposed to 0-fill, 1-fill, or adjacent fill, increases defect detection through collateral coverage.

Abstract: A method includes retrieving a group test parameter determined based on test results associated with a plurality of integrated circuit devices. A particular integrated circuit device is tested using a test program and the group test parameter.

Abstract: A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined in conjunction with circuit description data to identify fault locations. For at least certain of the fault locations, the logic-level conditions at neighboring locations which describe the behavior of a failing response are identified. Those logic level conditions are combined into a macrofault for that location. The macrofault is then validated and can be then used to identify more tests for further refining the diagnosis. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A method, system, and computer program product for automated root cause identification of a failure of a logic controller have been provided. The method includes receiving logic controller failure information, receiving a logic model of logic code for the logic controller, and mapping the logic controller failure information to the logic model to identify a logic failure model state. The method further includes determining a potential trigger of the failure of the logic controller as a root cause via tracing through at least one path in the logic model to reach the logic failure model state. The method also includes identifying the root cause in the logic code via mapping the root cause from the logic model to the logic code, and outputting the logic code with the identified root cause of the failure of the logic controller.

Abstract: A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.

Abstract: Executing a simulation of a computer platform, the simulation including simulation models. A dynamic quantum is accessed whose current value specifies a maximum number of units of execution a simulation model is allowed to perform without synchronizing with another simulation model. The dynamic quantum may be received from a user. Respective simulation models are invoked for execution with the current value of the dynamic quantum provided to each of the simulation models. The method also comprises modifying the value of the dynamic quantum based on a simulation event.

Abstract: A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.

Abstract: To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. A simulation part performs a simulation based on a description of the logic function described in a hardware description language. A second symbol replacing part replaces an indeterminate value generated in the simulation by the simulation part with a symbol. The simulation part generates a symbol expression and propagates it to an element at a later stage when the symbol replaced by the second symbol replacing part reaches an element being processed. Therefore, unintentional erasing of the indeterminate value generated during the simulation can be prevented.

Abstract: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.

Abstract: A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an integrated circuit that includes a plurality of domains and latches. The error injection test includes injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains. A checkpoint is created of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed. A mainlines test of the integrated circuit is executed. The mainline test includes applying the checkpoint to the integrated circuit, and performing a recovery reset of the stopped domain. It is determined if the mainline test executed correctly and the results of the determining are output.

Abstract: A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.

Abstract: A method and apparatus that is configured to issue an echo extended link service with a payload of data patterns that are known in the art of fiber channel to produce jitter. The inventive apparatus is configured to use an echo extended link service to send data with a specified data pattern. Failing data patterns are compared against data patterns that are known in the art of fiber channel to create jitter and the results may be presented to the user.

Abstract: A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

Abstract: A method and system for testing a semiconductor device is disclosed. The method provides an integrated test program defined by a plurality of test items, and a test program defined by a sub-set of the test items. Test data is derived by batch sample testing of the semiconductor device, and an error rate for a test item is computed and then compared to a reference data value. On the basis of the comparison between the error rate and the reference data value, the test program may be modified in real-time.

Abstract: A method for testing logic devices configured across asynchronous clock domains includes deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto. The deactivation of a local clock signal for each of the plurality of latches is implemented in a manner so as to permit data capture within the first plurality of latches, and wherein the deactivation of a local clock signal for each of the plurality of latches is further implemented in a manner so as to permit at-speed data launch therefrom to downstream latches with respect thereto during at-speed testing.

Abstract: Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element 5 and a symbol injection part for a passive element 7, an occurrence probability providing part 9, an equal occurrence probability providing part 11, and a switching part 13. A per-test X-fault diagnosis flow by the diagnostic device 1 consists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element 7, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution.

Abstract: A first FF outputs a first signal. A second FF captures the first signal and outputs a second signal. Each of the first and the second FF has a clock terminal to capture a clock signal. A third FF captures the first signal in parallel with the second FF. The third FF has a clock terminal to capture the clock signal in parallel with the clock terminal of the second FF. A buffer delays arrival of the clock signal to the clock terminal of the third FF. A comparing circuit compares the second signal and the third signal. An error collecting circuit captures a result of comparison to judge whether a timing error occurs in the second FF.

Abstract: A testing system includes an integrated circuit having an analog design under test and a processor; an digital-to-analog converter (DAC), coupled to the analog design under test and the processor, for converting a digital testing sequence output of the processor into an analog testing sequence fed into the analog design under test; a analog-to-digital converter (ADC), coupled to the analog design under test and the processor, for converting an analog testing response of the analog design under test into a digital testing response fed into the processor; and an external tester, coupled to the processor of the integrated circuit, for sequentially outputting a program sequence to the processor; wherein the processor executes the program sequence without un-predictable conditional jump to get a testing result of the testing system and then outputs the testing result to the external tester.

Abstract: A method for diagnosing a degree of interference between a plurality of faults in a system under test, the faults being detected by means of applying a test suite to the system under test, includes: 1) for each of the plurality of faults, and for each of a plurality of test syndromes, where a test syndrome is a pattern of passing and failing tests of the test suite, determining relative frequencies at which particular ones of the faults are coupled with particular ones of the syndromes; and 2) using the relative frequencies at which particular ones of the faults are coupled with particular ones of the syndromes to calculate and display to a user, via a graphical user interface, and for the test suite as a whole, test suite degrees of interference between pairs of the faults. Other embodiments are also disclosed.

Abstract: According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112, a sum of the outputs from the scan chains 111 and an expected value written in an expected value storage circuit 113 from the outside are compared with each other in an expected value decision circuit 114, the sum being outputted from the output compression circuit 112, a pass/fail decision result obtained by the comparison can be outputted from an output terminal 116 of the expected value decision circuit 114 to the outside, and the decision result can be stored regardless of the reset of a system.

Abstract: A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module.

Abstract: An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an emulation control unit for allowing one of the two of the plurality of IFs to perform an operation of emulating an IF of a connection partner device having operation specifications different from those of the LSI, when two IFs are connected to each other via a transmission line.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Abstract: A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function.

Abstract: This test generator takes data flow block diagrams and uses requirements-based templates, selective signal propagation, and range comparison and intersection to generate test cases containing test vectors for those diagrams. The templates are based on the functionality and characteristics of a block type, and each block type has associated templates. These templates provide maps for the creation of test values that verify the functionality of particular instances of that block type. Signal propagation allows the generation of diagram-level test cases that verify particular characteristics of a single embedded block. The methods disclosed for signal propagation utilize range intersection, equivalence classes, and block type formulae to create efficient and complete test cases. This test generation method would preferably be repeated until all blocks in a data flow block diagram were verified in their respective contexts, and it creates test cases that cover multiple time steps.

Abstract: A method for generating test cases for software and a test case generator comprising a simulator that drives software under test from one input state to the next. The simulator is constrained by predetermined criteria to visit states that meet the criteria thus preserving computer resources. The states reached by the simulator are tested.

Abstract: A calibration system within a test system is disclosed. The calibration system may include a netlist, a path correction module, and a processor in signal communication with the path correction module. The netlist may include a list of electrical characteristics of components in the test system and a topology of the test system. The calibration system can be used with a variety of test system topologies.