Abstract: A coverage-directed test generation technique for functional design verification relies on events that are clustered according to similarities in the way that the events are stimulated in a simulation environment, not necessarily related to the semantics of the events. The set of directives generated by a coverage-directed test generation engine for each event is analyzed and evaluated for similarities with sets of directives for other events. Identified similarities in the sets of directives provide the basis for defining event clusters. Once clusters have been defined, a common set of directives for the coverage-directed test generation engine is generated that attempts to cover all events in a given cluster.

Abstract: One embodiment of the invention provides a method for simulating the operation of a system. The method includes providing a fault tree representation of the system. The fault tree defines a set of problems that may occur in the system, and specifies propagations in the system whereby a problem may create one or more errors that may in turn be detected by error detectors to produce corresponding error reports. The fault tree representation allows the presence of a problem in the system to be simulated, and the set of error reports resulting from the simulated problem to be determined. This simulation can be repeated for different problems to compare the sets of error reports potentially produced by the different problems.

Abstract: The present invention facilitates clock and data recovery for serial data streams by selecting a clock phase for each input data transition and generating a recovered clock. In order to identify data transitions, the received serial data stream is sampled N times per ideal bit time, where the minimum value for N must be greater than 2/(1?(2*jitter_ratio)) and jitter_ratio is the fractional representation of the portion of the ideal bit time during which transitions can be expected or estimated to occur. On identifying a transition, a toggle phase is set. In order to avoid stale clock phase selection resulting from jitter and the like, one phase after the toggle phase is blocked or prevented from being selected for the clock. Finally, a clock phase is selected N/2 phases from the toggle phase and a recovered clock is generated by combining the individually selected clock phases.

Abstract: Various methods and apparatuses are described in which a software programming interface connects one or more functional checker components and one or more protocol checker components to an interconnect monitor component. A computer readable medium stores code for the one or more functional checker components for Intellectual Property (IP) cores, one or more protocol checker components, the interconnect monitor component, and the software programming interface. The monitor component has code to build data structures containing protocol data types requested by a checker component and code on where to deliver data based upon a particular type of data requested by the checker component.

Abstract: The present invention provides a method and a system of generic implementation of sharing test pins with I/O cells. The method includes a step of making a general change in a testlib file. The testlib file is suitable for controlling I/O cell pins to gain test access. The general change restricts I/O cells for sharing with test pins. The method further includes a step of making iogen changes for sharing. Optionally, the method may include a step of making a cell level change in the testlib file. The cell level change overrides restrictions defined by the general change.

Abstract: A Bayesian network correlating coverage data and input data to a test verification system for coverage directed test generation (CDG) of a device under test. In one embodiment, the Bayesian network is part of a CDG engine which also includes a data analyzer which analyzes coverage data from a current test run of a test verification system and from previous test runs to determine which coverage events from a coverage model have occurred therein, at what frequency and which ones have not yet occurred, a coverage model listing coverage events which define the goal of the test verification system and a task manager coupled to the data analyzer and the Bayesian network which refers to the coverage model and queries the Bayesian network to produce input data to achieve desired coverage events.

Abstract: A method of optimising a digital test signal for testing an analogue or mixed-signal circuit comprising determining a measure, for example a figure of merit, that is indicative of differences between the output of a fault free and the output of a known faulty circuit in response to an applied digital input signal. The digital input signal is then varied and another figure of merit is calculated for the fault free and the known faulty circuit for the new input signal. This is repeated a number of times, the digital input signal being varied each time. An optimum test signal is selected based on the determined figures of merit.

Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.

Abstract: A method for performing testing of a simulated direct access storage device in a testing simulation environment is disclosed. The method provides a software representation of a plurality of hardware components within the simulated direct access storage device. The method also uses a control program module within the testing simulation environment, wherein the control program module interacts with the software representation of the plurality of hardware components, and a testing program for interacting with the control program module and the software representation of the plurality of hardware components. In response to detection of an occurrence of a pre-selected event within the simulated direct access storage device, one or more codes are sent from the testing program to the software representation of the plurality of hardware components and whether or not a response by the control program module to the one or more codes is correct is determined.

Abstract: An apparatus for selecting test patterns in accordance with an embodiment of the present invention has a first test pattern selecting module configured to define selected test patterns and unselected test patterns, a fault simulation module configured to simulate whether test patterns detect faults, a weighting module configured to add a weight to each of the first undetected faults, a fault sampling module configured to extract second undetected faults from the first undetected faults to which the added weights are given, and a second test pattern selecting module configured to extract additionally selected test patterns based on the added weight.

Abstract: A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal. The observation circuit is controlled by the signals, and receives input data from observation points in the test target circuit. The observation circuit includes a plurality of flip-flops. The observation circuit performs a reset operation in response to the reset signal. The observation circuit selectively performs a signature-compression operation, and a serial operation of outputting the test result, in response to the operation mode signal. The signature-compression operation is performed, using input data generated in the test target circuit in accordance with test patterns for a normal functional operation.

Abstract: In a method and system for testing a test sample (190), a simulation program (130) is used to augment test results provided by a legacy test system (101). The legacy test system (101) includes a measuring device (110) providing a test input (112) to the test sample (190) and receiving a test output (116) from the test sample (190) in response to the test input (112). The simulation program (130) simulates the test sample (190) by predicting a simulated output (134) of the test sample (190) in response to receiving a simulated input (132). A plurality of simulated failures is simulated in the simulation program (130), with each simulated failure generating a corresponding simulated output. The simulation program (130) includes a model (140) for the measuring device (110), the model (140) providing the simulated input (132). A comparator (160) compares the test output (134) with the simulated output (134) to determine a match.

Abstract: A system of the present invention tests the design of a universal serial bus (USB) smartcard device and includes a bus analyzer for running test cases to generate USB bus traffic. A processor is operatively connected to the bus analyzer for receiving and transforming data about USB traffic into a selected data format that is usable across different smartcard development environments.

Abstract: A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network.

Abstract: A method for improved ATE (automatic test equipment) timing calibration at a DUT (device under test). The method includes step of accessing a DUT component using an ATE component and performing physical calibration on a first portion of signal pathways coupling the ATE component to the DUT component. A simulation based calibration is performed on a second portion of signal pathways coupling the ATE component to the DUT component. The physical calibration results are combined with simulation based calibration results to calibrate timing propagation delay between the ATE component and the DUT component.

Abstract: Provided are a method, system, and program for simulating I/O requests to test a system coupled to an adaptor having a port used for transmitting and receiving I/O requests to the system. A user test command is received indicating an I/O test object. The adaptor processes the I/O test object indicated in the user test command to generate a sequence of simulated I/O requests and transmits the generated simulated I/O requests to the system.

Abstract: A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical parameters are combined to form one path group. For each path group, a statistical group figure is, then, calculated and, for the totality of paths considered, a statistical total figure is calculated. Finally, the critical paths of the circuit are determined by taking into consideration the total figure, comparing the group figures at or above a critical path transit time Tc.

Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

Abstract: A method and system for resolving testcase collection inconsistencies between a testcase list which includes testcases that have triggered harvest events within a simulation model, and a harvest hit table which records harvest events that have been triggered during simulation of the simulation model. First, the harvest hit table is updated from a simulation client to include a harvest event triggered by a testcase during simulation of the simulation model. The testcase is then collected within the testcase list. Finally, testcases identified within the testcase list are compared to testcases identified within the harvest hit table to determine inconsistencies therebetween.

Abstract: An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

Abstract: A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator.

Abstract: A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.

Abstract: A search engine apparatus having a built-in functional test may include an input generator, a search engine, a pseudo search engine and a comparator. The inputs generator is suitable for generating outputs including commands and points associated with the commands. The search engine and the pseudo search engine are communicatively coupled to the inputs generator. The search engine suitable for performing search and edit operations and the pseudo search engine is suitable for simulating the search engine by generating pseudo search engine outputs. The comparator is communicatively coupled to the search engine and the pseudo search engine, and is suitable for comparing outputs received from the search engine and pseudo search engine.

Abstract: A method and/or system for computer-based testing includes, for example, instantiating an expansion module, and providing to the expansion module a resource storage element within a resource file. The method and/or system also includes, for example loading information from the resource storage element into the expansion module during delivery of the test, and providing the information from the expansion module to the test driver during the delivery of the test. Various alternative embodiments are also disclosed.

Abstract: Generating a test sequence includes receiving a circuit representation describing a circuit, and a fault associated with the circuit representation. A miter circuit model associated with a good circuit model and a faulty circuit model is established according to the circuit representation. A satisfiability problem corresponding to the fault as associated with the miter circuit model is also established. Whether the satisfiability problem is satisfiable is determined. If the satisfiability problem is satisfiable, a test sequence is generated for the fault as associated with the miter circuit model.

Abstract: This invention relates to an apparatus and an associated method that tests the response of a computer component. The apparatus includes a modeler, a tester, and a test generator. The modeler provides a model of the computer component object behavior. The tester provides stimulus values to be applied to the computer component object. The test generator converts the model of the computer component object behavior and the stimulus values into test script. The test script can be executed by an automated test executor.

Abstract: A tester or method of testing a mass storage interface queues error functions for simulation responsive to condition criteria of such storage simulation. Such bridge-chip tester may comprise ATA registers to receive data from an ATA or ATAPI-type interface. A main access emulator may emulate data storage processes responsive to commands of a command register of the ATA registers. A test controller may be operable to load a queue with predetermined error functions to be emulated by the tester. The queue may release error functions of the queue for emulation responsive to data of at least one of the command register and the emulator.

Abstract: A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Abstract: Systems and methods for digital-based, standards-compatible, testing of analog circuits embedded inside integrated circuits. In this regard, one such system can be broadly described by a test stimulus generator that transmits a binary-level test-stimulus signal into an analog circuit located inside an integrated circuit; a converter that converts an analog output signal from the analog circuit into a digital output signal; a boundary-scan register chain that transmits the digital output signal out of the integrated circuit, and a test equipment that receives the digital output signal using the IEEE 1149.1 boundary-scan standard and analyzes the digital output signal to compute one or more specifications of the analog circuit located inside the integrated circuit.

Abstract: A system is provided for automatically generating ATAP test solutions. The system includes ATAP simulation circuitry, a bus, an ATAP test bench file, an output file, and a test program. The ATAP simulation circuitry is switchably coupled to a selected analog cell having an ATAP for applying analog tests. The bus is coupled with the ATAP simulation. The bus is operative to transmit and receive analog test simulation data. The ATAP test bench file is configured to receive the simulation data. The output file is operative to store the simulation data and deliver the simulation data to the ATAP simulation circuitry. The test program is generated by the ATAP simulation circuitry in the output file. The test program is configured to automatically generate ATAP test benches based upon chip-specific information. A method is also provided.

Abstract: The present invention is an apparatus for multi-level loopback test in a community network system and method therefor, in which a loopback test device is installed between an Ethernet switch in a community and a central office so that the loopback test device can be utilized by network management system in central office to perform a three-level loopback test on the community network system to easily obtain the information of whether there is a fault between central office and loopback test device, whether the connection of Ethernet switch is good, and whether loopback test device operates normally.

Abstract: A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

Abstract: A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

Abstract: A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized by extracting a state at each clock period to generate a simulation synchronous sequence. This sequence is manipulated first to include short delays for generating an asynchronous short-delay sequence and second to include long delays for generating an asynchronous long-delay sequence. An overlay is separately performed among the clock periods of the asynchronous short-delay sequence and the asynchronous long-delay sequence to respectively identify a first interval and a second interval. The first interval and the second interval are independently duplicated in successive clock periods to respectively generate a synchronous short-delay sequence and a synchronous long-delay sequence.

Abstract: The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of controlling the simulation of a digital circuit in such a way that desired functions are annotated for subsequent analysis. A hardware design code describing the digital circuit is converted to an assignment decision diagram (ADD) representation that is then annotated with one or more control nodes that are used for maintaining control flow through a simulator. In this way, one or more break points are created that allow the simulator to stop at associated points in the simulation.

Abstract: A technique of generation of a job for a digital testing unit for a test station from a circuit simulation unit includes completing fault simulation on electronic circuitry, then executing a first program without a fault dictionary, generating a pin map of the electronic circuitry and appending any pin groups, generating test vectors using the pin groups by the first program, generating additional pin groups to accommodate any orphan pins, converting the pin maps and pattern files to pin maps and pattern files, executing the first program to generate the fault dictionary, inputting a minimum scope level of analysis of the circuitry, generating the fault dictionary in fault dictionary data files according to the minimum scope level, generating a fault retriever file from the first program; and transporting the fault dictionary data files, test vectors, new pin maps, and fault retriever file to a second program for run-time fault analysis on the electronic circuitry testing unit.

Abstract: A new method and apparatus to verify the performance of a built-in self-test circuit for testing embedded memory in an integrated circuit device is achieved. A set of faults is introduced into an embedded memory behavior model. The embedded memory behavior model comprises a high-level language model. Each member of the set of faults comprises a finite state machine state, a memory address, and a memory data fault. The built-in self-test circuit and the embedded memory behavior model are then simulated. The built-in self-test circuit generates input data and address patterns for the embedded memory behavior model. The embedded memory behavior model outputs memory address and data in response to the input data and address patterns. The input address and data and the memory address and data are compared in the built-in self-test circuit and a fault output is generated if not matching. The fault output and the set of faults are compared to verify the performance of the built-in self-test circuit.

Abstract: The apparatus includes the wiring-model generation section that generates a wiring model in accordance with high-frequency-circuit design information; the random-pattern analysis section that generates and analyzes a dummy random-pattern waveform for transmitting a wiring model in accordance with a command including the bit information of a random-pattern waveform and a differential waveform corresponding to the dummy random-pattern waveform; and the skew analysis section that skews a random-pattern waveform or differential waveform in accordance with a preset skew width.

Abstract: Timing verification of the LSI test data is performed as follows. In test synthesis, a script text for static timing analysis (STA) is generated together with a test circuit. The STA script text is used to perform static timing analysis. Function verification is performed between a netlist generated through the test synthesis and a timing-verified netlist based on the static timing analysis. The function-verified netlist is released to a production division, and the netlist is used to automatically generate a test pattern by an automatic test pattern generation (ATPG) tool. A netlist comprising test vectors for automatic test equipment is acquired from the generated ATPG pattern.

Abstract: A method of verifying test data for testing an integrated circuit device having multiple device time domains includes selecting a virtual tester time domain and, if the cycle duration of the virtual tester time domain is equal to the cycle duration of one of the multiple device time domains, translating the test data for each device time domain other than that one time domain to the virtual tester time domain and otherwise translating the test data for each device time domain to the virtual tester time domain. The translated test data is then applied to a device logic simulator that simulates integrated circuit device.

Abstract: The time, effort and expense required to develop verification software for testing and de-bugging system-on-chip (SOC) designs represents a considerable investment. According to the method of the present invention, a portion of such verification software may be re-used in an operating system (OS) (i.e., a system used for, e.g., general business, technical or scientific applications as opposed to software testing) to capitalize on the investment. The verification software includes low-level device drivers (LLDDs) which were coded for and paired with specific device designs (“cores”) throughout the verification process, and were consequently also verified (i.e., de-bugged) in the process. Thus, the low-level device drivers represent reliable software with detailed knowledge of the corresponding devices.

Abstract: A system and method of verifying an electronic system. A verification kernel is provided and the electronic system is expressed as a logic design. A wrapper is defined, wherein the wrapper is an interface between the logic design and the verification kernel. Tests to be run against the logic design are placed within a diagnostic program and an interface between the diagnostic program and the verification kernel is defined. The tests are then executed against the logic design. The results of the tests are captured and validated against expected results.

Abstract: A system and method automatically analyzes and manages loss factor data of test processes in which a great number of IC devices are tested as a lot with a number of testers. The lot contains a predetermined number of identical IC devices, and the lot test process is performed sequentially according to a predetermined number of test cycles. The system include a means for verifying test results for each of the test cycles and for determining whether or not a re-test is to be performed and an IC device loading/unloading means for loading IC devices to be tested and contained in the lot to a test head and for unloading the tested IC devices from the test head by sorting the tested IC devices according to the test results.

Abstract: A test pattern generator and a method of generating a test pattern. The method includes converting a test pattern into a program and simulating the program to produce a test pattern. The test pattern is applied to a test circuit to obtain simulated test results. The program is written to a memory unit. The test circuit is tested using the program inside the memory unit to produce actual test results. The simulated test results and the actual test results are compared. If the simulated and the actual results match each other, the test circuit is repeatedly test using the test pattern until no delay between loop backs is found. However, if there is a mismatch between the simulated and the actual results, the program is adjusted and the test circuit re-tested until a match between the simulated results and the actual results is found.

Abstract: A method of testing for the presence of faults in digital logic circuits is described. The method involves re-ordering a number of test vectors for testing digital circuits by selecting faults at random from an original fault list to form a sample fault list FN and then forming a vector set TN?1 and then simulating the vector set TN?1 against the fault list FN. Any vector from the set TN?1 which does not detect any fault is discarded and the remaining vectors are saved as vector set TN. The method steps are repeated N times (with N having a value of 1 to M. Duplicated vector patterns in each vector set are removed and then the final vector set is initialized to produce a final vector set TF.

Abstract: A method of generating a pattern for testing a logic circuit includes judging whether generation of a test pattern is to be undertaken. If it is judged that generation of a test pattern is to be undertaken, a fault is selected for which the test pattern is to be generated. Generation is attempted of at least one test pattern necessary for detecting the selected fault. Fault simulation is carried out to find a test pattern, from among copies of the at least one test pattern, by which the most undetected faults are detected. If at least one test pattern is generated, the test pattern is re-activated.

Abstract: A fault or an exception is injected into a target thread. Instructions are processed and a target thread is recognized. As a result, an asynchronous procedure call is queued. The asynchronous procedure call is run on the target thread and the context of the target thread is modified. The target thread is executed in the modified context and an exception is raised in the target thread as a result of the modified context. The exception is handled and processing of the instruction continues.

Abstract: A program defect condition is input to a defect-data programming apparatus which programs defect data for evaluation of a reticle inspection apparatus, thereby generating program defect information, program-defect-information-free source CAD data is converted to CAD data of a format with which the CAD data is input to the reticle inspection apparatus, and the program defect information is embedded into the converted CAD data, thereby generating program-defect-information-present CAD data for inspection apparatus. The program-defect-information-present CAD data for inspection apparatus is input to the reticle inspection apparatus together with a program-defect-information-free reticle produced based on the program-defect-information-free source CAD data, for execution of sensitivity evaluation. Program defect information needed to execute sensitivity evaluation of the reticle inspection apparatus is generated on that CAD data which is input to the reticle inspection apparatus, not on a real reticle.

Abstract: A simulation system simulates an operation of a memory. This system includes an error generating step in addition to a memory operation simulating step. An error can easily be generated in a read/write operation of a memory model only by setting a memory address. A set of free bits, which is not used for the simulation of a memory operation, is used as a memory address for indicating the error generation. It is thus unnecessary to prepare a new description of a signal line exclusively for indication of error generation and it is possible to simulate a memory operation containing an error only by the normal descriptions of an address, data, and the like.

Abstract: An IC test system comprises: a test pattern signal applying section for applying a test pattern signal to an IC to be tested, in accordance with a test program; a simulation section for simulating an operation of the test pattern signal applying section in accordance with a simulation program; and a management device which is connected detachably with the test pattern signal applying section, for managing the operation of the test pattern signal applying section and an operation of the simulation section in accordance with a management program, for storing information about each operation of the test pattern signal applying section and the simulation section, and for managing one of the information about the operation of the simulation section and the information about the operation of the test pattern signal applying section in accordance with the other information.