Testing Specific Device Patents (Class 714/742)
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Patent number: 7788561Abstract: Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.Type: GrantFiled: August 14, 2007Date of Patent: August 31, 2010Inventors: Yu Huang, Wu-Tung Cheng, Ruifeng Guo
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Patent number: 7778797Abstract: A system and method for detecting abnormal situations associated with a stirred vessel in a process plant receives statistical data associated with a pressure within a stirred vessel. A pressure signal associated with the pressure in the vessel is filtered by a digital filter to isolate a frequency component corresponding to pressure changes caused by the movement of a blade of an agitator through a fluid. For example, a pressure sensor device disposed at least partially within the stirred vessel may generate the statistical data based on a pressure signal. The statistical data is analyzed to detect whether one or more abnormal situations associated with an agitator of the stirred vessel exist. For example, the statistical data may be analyzed to detect whether the agitator is broken/unbalanced, corroded, missing a blade or multiple blades, etc. If an abnormal situation is detected, an indicator of the abnormal situation may be generated.Type: GrantFiled: September 27, 2007Date of Patent: August 17, 2010Assignee: Fisher-Rosemount Systems, Inc.Inventors: Roger K. Pihlaja, John P. Miller
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Patent number: 7773531Abstract: A method for testing a data packet transceiver as a device under test (DUT) by communicating, between one or more test instruments and the DUT, multiple data packets having at least one mutually distinct signal characteristic, such as data packet type, transmission power or transmission frequency.Type: GrantFiled: July 10, 2008Date of Patent: August 10, 2010Assignee: LitePoint CorporationInventors: Christian Volf Olgaard, Ray Wang, Peter Petersen
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Patent number: 7774669Abstract: The present invention provides systems, devices and methods for generating user-defined test patterns within serial controller to facilitate signal testing and verification. These user-defined test patterns may be generated to more accurately reflect the actual traffic of a device-under-test or system, as well as allow a test engineer to more accurately test the boundaries of the device or system. In various embodiments of the invention, a programmable patterns generator is provided for generating user-defined test patterns that may be used during a testing procedure. This programmable pattern generator allows a user to define a particular test pattern by providing bit-by-bit test values, by defining a combination of canned sequences, or by supplementing one or more canned sequences with additional test bits.Type: GrantFiled: June 11, 2007Date of Patent: August 10, 2010Assignee: LSI CorporationInventors: Gabriel L. Romero, Coralyn S. Gauvin
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Patent number: 7770083Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.Type: GrantFiled: March 25, 2009Date of Patent: August 3, 2010Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 7770080Abstract: A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined in conjunction with circuit description data to identify fault locations. For at least certain of the fault locations, the logic-level conditions at neighboring locations which describe the behavior of a failing response are identified. Those logic level conditions are combined into a macrofault for that location. The macrofault is then validated and can be then used to identify more tests for further refining the diagnosis. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: GrantFiled: January 10, 2007Date of Patent: August 3, 2010Assignee: Carnegie Mellon UniversityInventors: Ronald DeShawn Blanton, Rao H. Desineni, Wojciech Maly
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Patent number: 7765080Abstract: A system and method for testing multiple smart card devices in parallel and asynchronously are provided. The system includes a smart card module that may be easily inserted in a digital test system. The smart card module includes multiple smart card instrument channels, each one of which testing a separate smart card device independently and asynchronously from the others. The smart card instrument channels employ a novel modulation technique based on palette waveforms that are formed of transitions between two data bits.Type: GrantFiled: May 19, 2006Date of Patent: July 27, 2010Assignee: Nextest Systems CorporationInventors: Clifford V. Ludwig, Dan P. Bullard, Michael R. Ferland, Eric N. Parker, James W. St. Jean, David D. Reynolds
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Patent number: 7765443Abstract: One embodiment of the invention is a portion of a test system that includes a timing generation circuit and a formatter that are coupled together, which are on a single CMOS (complementary metal oxide semiconductor) integrated circuit. The timing Generation circuit generates software words. The formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. It is noted that the formatter includes a drive circuit and a response circuit. Specifically, the drive circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent strobe marker.Type: GrantFiled: May 7, 2004Date of Patent: July 27, 2010Assignee: Credence Systems CorporationInventors: Ahmed Rashid Syed, Burnell G. West
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Patent number: 7757143Abstract: A semiconductor device includes one or more test terminals and a test control circuit is disclosed. The test control circuit tests an internal circuit according to the signals received from the one or more test terminals. Afterwards, specification information held in a specification information holding unit is renewed such that one or more inputs of the test control circuit are fixed to a predetermined level.Type: GrantFiled: February 21, 2007Date of Patent: July 13, 2010Assignee: Mitsumi Electric Co., Ltd.Inventor: Masato Momii
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Patent number: 7757145Abstract: The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.Type: GrantFiled: March 18, 2008Date of Patent: July 13, 2010Assignee: Qimonda AGInventors: Wolfgang Ruf, Martin Schnell
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Patent number: 7757142Abstract: Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.Type: GrantFiled: July 16, 2008Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Mohit Kapur, Seongwon Kim
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Patent number: 7746183Abstract: Disclosed herein is a measurement apparatus for improving performances of standard cells in a standard cell library when verifying performance of the standard cell library through a ring oscillator among various test element groups (TEGs). A built-in circuit is used to measure and verify performance of the standard cell library through a TEG. Therefore, it is possible to effectively improve performances of the standard cells in the standard cell library. Particularly, it is possible to not only remove human errors or internal errors of equipment, but also perform the measurement more readily, rapidly and accurately. Further, it is possible to curtail the use of high-performance equipment or manpower and time required in a measurement process.Type: GrantFiled: June 24, 2008Date of Patent: June 29, 2010Assignee: Dongbu HiTek Co., Ltd.Inventors: Seong-Heon Kim, Woo Chol Shin, Kyeong Soon Cho
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Patent number: 7747901Abstract: Control commands are transmitted via an emulation interface holding a test clock signal at a constant value and switching a test mode select signal a number of times corresponding to the control command. A receiving system counts switches of the test mode select signal switches while the test clock is constant and interprets the number of switches as a corresponding control command.Type: GrantFiled: July 20, 2006Date of Patent: June 29, 2010Assignee: Texas Instruments IncorporatedInventor: Gary L. Swoboda
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Patent number: 7747908Abstract: A system and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation is presented. A test pattern generator/tester re-uses test patterns in different configurations that alter cache states and translation lookaside buffer (TLB) states, which produces different timing scenarios on a broadband bus. The test pattern generator/tester creates multiple test patterns for a multi-processor system and executes the test patterns repeatedly in different configurations without rebuilding the test patterns. This enables a system to dedicate more time executing the test patterns instead of building the test patterns. By repeatedly executing the same test patterns in a different configuration, the invention described herein produces different start cache states, different TLB states, along with other processor units, each time the test patterns execute that, in turn, changes the bus timing.Type: GrantFiled: July 18, 2007Date of Patent: June 29, 2010Assignee: International Business Machines CorporationInventors: Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Chakrapani Rayadurgam, Batchu Naga Venkata Satyanarayana
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Patent number: 7743291Abstract: A semiconductor memory device includes a memory cell array, a plurality of data input/output terminals, a plurality of signal paths for writing data supplied to the data input/output terminals to the memory cell array in parallel, a plurality of latch circuits temporarily holding the data on the signal paths, respectively, and a selector selectively supplying the data to the latch circuits from a test data terminal during a test operation. The data can be thereby supplied from the test data terminal to the latch circuits in parallel during the test operation. The number of terminals used at an operation test can be, therefore, greatly decreased.Type: GrantFiled: July 5, 2007Date of Patent: June 22, 2010Assignee: Elpida Memory, Inc.Inventor: Nobuo Yamamoto
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Patent number: 7743296Abstract: A method of programming a programmable logic device (PLD), in accordance with an embodiment, includes receiving trigger unit information of a logic analyzer via a software interface for monitoring internal PLD signals and providing trigger unit output signals based on the internal PLD signals for the corresponding trigger units; and receiving trigger expression information of the logic analyzer via the software interface as a text string of logic operators and operands, wherein the operands represent the trigger unit output signals. The method may further include generating configuration data based on the trigger unit information and the trigger expression information; and providing the configuration data to the PLD, wherein a trigger expression based on the trigger expression information is stored within memory of the PLD.Type: GrantFiled: March 26, 2007Date of Patent: June 22, 2010Assignee: Lattice Semiconductor CorporationInventors: David Pierce, Michael Hammer, Brian M. Caslis
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Patent number: 7743304Abstract: A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.Type: GrantFiled: February 17, 2006Date of Patent: June 22, 2010Assignee: Verigy (Singapore) Pte. Ltd.Inventors: Erik H. Volkerink, Edmundo De La Puente
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Patent number: 7743288Abstract: A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.Type: GrantFiled: June 1, 2005Date of Patent: June 22, 2010Assignee: Altera CorporationInventor: Shoujun Wang
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Patent number: 7743301Abstract: A semiconductor integrated circuit includes an MISR (Multiple-Input Signature Register) for generating and storing compressed code based upon code from a ROM, and for reading out and outputting the compressed data that has been stored. The MISR has a clock change-over unit for changing over a clock in such a manner that the MISR is caused to operate at a high-speed clock when the compressed data is generated and stored, and at a low-speed clock when the stored compressed data is read out and output.Type: GrantFiled: May 25, 2006Date of Patent: June 22, 2010Assignee: NEC Electronics CorporationInventor: Yasunori Sawai
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Patent number: 7743295Abstract: A system and method for testing an integrated circuit is disclosed. One embodiment includes at least one central processing unit, at least one volatile memory area, and an interface, wherein the volatile memory area is connected to the interface to be written thereto by the interface. The system includes a test device connected with the integrated circuit which is configured to stop the program execution, write data in the volatile memory by using the interface, and start the program execution.Type: GrantFiled: March 14, 2007Date of Patent: June 22, 2010Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Klaus Scheibert, Harry Siebert
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Patent number: 7739563Abstract: A semiconductor integrated circuit is configured to test a high-speed memory at the actual operation speed of the memory, even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data.Type: GrantFiled: April 7, 2008Date of Patent: June 15, 2010Assignee: Panasonic CorporationInventor: Osamu Ichikawa
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Patent number: 7739573Abstract: A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.Type: GrantFiled: January 10, 2007Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Jonathan J. DeMent, Sang H. Dhong, Gilles Gervais, Alain Loiseau, Kirk D. Peterson, John L. Sinchak
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Patent number: 7729891Abstract: Methods, apparatus and systems are provided that enable the generation of random regression suites for verification of a hardware or software design to be formulated as optimization problems. Solution of the optimization problems using probabilistic methods provides information on which set of test specifications should be used, and how many tests should be generated from each specification. In one mode of operation regression suites are constructed that use the minimal number of tests required to achieve a specific coverage goal. In another mode of operation regression suites are constructed so as to maximize task coverage when a fixed number of tests are run or within a fixed cost.Type: GrantFiled: June 6, 2005Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Shai Fine, Shmuel Ur, Avi Ziv, Simon Rushton
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Patent number: 7730376Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling. Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling. Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.Type: GrantFiled: March 27, 2008Date of Patent: June 1, 2010Assignee: Intel CorporationInventor: Debendra Das Sharma
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Patent number: 7725780Abstract: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.Type: GrantFiled: October 19, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Michael R. Ouellette, Jeremy Rowland
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Patent number: 7702981Abstract: A boundary scan technique to generate toggling waveform such as a square wave signal to perform structural testing is disclosed. An instr_extesttoggle command is provided that enables IEEE 1149.1 boundary scan cell to selectively generate the toggling signal on the pre-specified output pads of the integrated circuit. The frequency of the toggling signal may be controlled by the JTAG clock signal and the frequency of the toggling signal may be independent of the length of the boundary scan chain. Such an approach circumvents provisioning test points on the interconnects of a printed circuit board.Type: GrantFiled: March 29, 2007Date of Patent: April 20, 2010Assignee: Intel CorporationInventors: James Grealish, Dave F. Dubberke, Milo J. Juenemann, Christopher J. Koza, Eric T. Fought
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Patent number: 7702984Abstract: A high volume testing/formatting process is provided for Universal Serial Bus-based (USB-based) electronic data flash cards (USB devices) that meets the increasing demand for USB electronic data flash cards (USB devices). A test host is simultaneously coupled to the multiple USB devices (e.g., using a multi-port card reader or a probe fixture), a controller endpoint value is read from each of the USB devices and verified with a known good value, and then testing/formatting is performed on each of the USB devices by writing predetermined data into each USB device in a pipelined manner, then reading out and testing the predetermined data. In one embodiment, the test host implements a special a USB driver that blocks standard USB registration procedures upon detecting the plurality of USB devices. Control and/or boot code data are written onto the flash memory device (i.e., instead of being provided on a controller ROM).Type: GrantFiled: January 23, 2007Date of Patent: April 20, 2010Assignee: Super Talent Electronics, Inc.Inventors: Charles C. Lee, I-Kang Yu, Edward W. Lee, Abraham C. Ma, Ming-Shiang Shen
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Patent number: 7689884Abstract: An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.Type: GrantFiled: April 23, 2007Date of Patent: March 30, 2010Assignee: Advanced Micro Devices, Inc.Inventor: Markus Seuring
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Patent number: 7689871Abstract: A method for monitoring a system, having a control unit defined as a master and a number of control units defined as slaves, with the aid of a monitoring module, in which in reply to an inquiry from the master and the slaves a response is given in each instance and a joint response provided on the basis of these responses is checked by the monitoring module.Type: GrantFiled: May 9, 2005Date of Patent: March 30, 2010Assignee: Robert Bosch GmbHInventor: Per Hagman
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Patent number: 7689879Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.Type: GrantFiled: May 9, 2006Date of Patent: March 30, 2010Assignee: Micron Technology, Inc.Inventor: Joseph M. Jeddeloh
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Patent number: 7680493Abstract: According to one embodiment, a low phase noise testing system includes a tester providing a high phase noise digital channel output. The low phase noise testing system further includes a crystal filter configured to receive the digital channel output and to pass a narrow frequency range from the digital channel output, whereby the high phase noise digital channel output is converted to a low phase noise clock for use by a device under test. The crystal filter can be, for example, a monolithic crystal filter or a discrete crystal filter.Type: GrantFiled: May 10, 2007Date of Patent: March 16, 2010Assignee: Broadcom CorporationInventor: Timothy F. Scranton
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Patent number: 7676711Abstract: A test circuit for testing a command signal at a package level in a semiconductor device includes: a logic level determining unit for determining logic levels of a plurality of command flag signals in response to a plurality of internal command signals in a test mode; a storage unit for storing the plurality of command flag signals in response to a store control signal and outputting the plurality of command flag signals in series in response to an output control signal; and an output unit for driving an output signal of the storage unit to a data pad.Type: GrantFiled: June 28, 2007Date of Patent: March 9, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Hong-Sok Choi
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Patent number: 7676713Abstract: An intertwined test specification (ITTS) is used for controlling Automated Test Equipment (ATE) to apply a sequence of stimulus signals to a device under test (DUT) during a stimulus run and to validate returned response signals during a validation run. The ITTS has response validation scripts intertwined with stimulus invoking scripts where the response validation scripts are conditionally executed during the validation run but not during the stimulus invoking run. Response signals are logically associated with unique stimulus identification codes so that appropriate response signals can be matched with corresponding validation scripts even if the response signals are returned out-of-order to the ATE or to a response logging unit interposed between the ATE and the DUT.Type: GrantFiled: October 28, 2005Date of Patent: March 9, 2010Assignee: Integrated Device Technology, Inc.Inventor: Ryan Holmqvist
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Patent number: 7676712Abstract: According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.Type: GrantFiled: January 18, 2002Date of Patent: March 9, 2010Assignee: Mentor Graphics CorporationInventors: Greg Bensinger, Jean-Marc Brault, Hans Erich Multhaup
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Patent number: 7676716Abstract: A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced.Type: GrantFiled: July 8, 2008Date of Patent: March 9, 2010Assignee: LSI CorporationInventors: Jeffrey S. Brown, Mark F. Turner, Marek J. Marasch
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Patent number: 7673193Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.Type: GrantFiled: August 18, 2005Date of Patent: March 2, 2010Assignee: Rambus Inc.Inventors: Adrian E. Ong, Naresh Baliga
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Patent number: 7673207Abstract: A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module.Type: GrantFiled: June 15, 2007Date of Patent: March 2, 2010Assignee: Marvell International Ltd.Inventors: Masayuki Urabe, Akio Goto
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Patent number: 7673208Abstract: An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include an indication of the failure-causing test data and the corresponding test analysis data. Embodiments are provided which enable that the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test, together with respective diagnosis data.Type: GrantFiled: April 23, 2007Date of Patent: March 2, 2010Assignee: Advanced Micro Devices, Inc.Inventor: Markus Seuring
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Patent number: 7661051Abstract: An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.Type: GrantFiled: April 4, 2007Date of Patent: February 9, 2010Assignee: LSI CorporationInventors: Gurjinder Singh, Ara Bicakci
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Patent number: 7661053Abstract: A device response template generator software program includes an interactive graphical-user-interface (GUI) for sending commands to devices under test and to capture and display the command responses. The GUI enables patternization of the command response to that the information contained in the response can be read, in the form of variable values, automatically, during subsequent execution of the commands by the same device or a group of devices. These values of the variables may be analyzed and may also be sent to other running testing scenarios.Type: GrantFiled: December 18, 2008Date of Patent: February 9, 2010Assignee: Sapphire Infotech, Inc.Inventors: Manoj Betawar, Dinesh Goradia
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Patent number: 7657799Abstract: Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.Type: GrantFiled: May 4, 2006Date of Patent: February 2, 2010Assignee: Agere Systems, Inc.Inventors: Yasser Ahmed, Robert Joseph Kapuschinsky, Ashok Khandelwal, Samuel Khoo, Lane A. Smith
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Patent number: 7656178Abstract: A method for calibrating a semiconductor device tester is disclosed. In accordance with method of the present invention, a timing is calibrated using a programmable delay device and calibration boards so as to remove a timing difference between channels and compensate a linearity of the programmable delay device for an adjustment of a timing by building and using a database of the round trip delay actually generated during the test.Type: GrantFiled: August 6, 2007Date of Patent: February 2, 2010Assignee: UniTest Inc.Inventor: Jong Koo Kang
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Patent number: 7657803Abstract: A memory controller with a self-test function includes a test controlling unit configured to generate test data in a test mode, a data transmission unit configured to generate a data read timing signal to transmit the data read timing signal and the generated test data synchronized with the data read timing signal, and a data input/output (I/O) unit configured to feedback the transmitted test data and the transmitted data read timing signal to the data transmission unit, such that the data transmission unit receives fed-back test data and a fed-back data read timing signal. The data transmission unit reads the fed-back test data based on the fed-back data read timing signal, and the test controlling unit compares the fed-back test data with the generated test data. Therefore, the memory controller may perform a fast self-test.Type: GrantFiled: June 25, 2007Date of Patent: February 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Kwan-Yeob Chae
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Patent number: 7653847Abstract: Methods and structures for performing field flawscan to reduce manufacturing costs of a dynamic mapped storage device. In a dynamic mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof permit flawscan testing of a storage device to be completed substantially concurrently with processing write requests for its intended application. A fraction of the storage device may be certified by an initial flawscan performed during manufacturing testing. Statistical sampling sufficient to assure a high probability of achieving specified capacity may be performed to reduce manufacturing time and costs in testing. Final flawscan of the remainder of the storage locations may be performed substantially concurrently with processing of write requests after the device is installed for its intended application.Type: GrantFiled: October 19, 2006Date of Patent: January 26, 2010Assignee: Seagate Technology LLCInventors: Bruce A. Liikanen, Eric D. Mudama, John W. VanLaanen, Andrew W. Vogan
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Patent number: 7650544Abstract: Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.Type: GrantFiled: September 12, 2008Date of Patent: January 19, 2010Assignee: Hynix Semiconductor Inc.Inventors: Ji-Eun Jang, Kee-Teok Park
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Patent number: 7650255Abstract: A method of multi-site testing a batch of semiconductor units using a multi-site automated tester (100). The tester (300) includes a handler (320) coupled to a contactor (330) including a first plurality of contact sites. The method includes the step of loading the first plurality of units into the first plurality of contact sites (201). The first plurality of units are simultaneously tested (202) using a test program to determine bin information for each of the first plurality of units, wherein the bin information defines each of the first plurality units as being a passed unit or a reject unit. The passed units are offloaded from respective contact sites of the first plurality of contact sites to create vacant contact sites (203), while keeping the reject unit(s) at respective contact sites of the first plurality of contact sites. Untested units from the batch are then loaded to fill the vacant contact sites (204).Type: GrantFiled: May 2, 2008Date of Patent: January 19, 2010Assignee: Texas Instruments IncorporatedInventors: Chi Tsung Lee, Sheng Pin Chen, Ming Chuan You, Shou Ping Hsu
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Patent number: 7640124Abstract: In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.Type: GrantFiled: March 14, 2007Date of Patent: December 29, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Hideaki Konishi, Ryuji Shimizu, Masayasu Hojo, Haruhiko Abe, Satoshi Masuda, Naofumi Kobayashi
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Patent number: 7640132Abstract: A recording medium recording thereon a program for a test apparatus including test modules that test devices under test is provided. The program includes: a common function provision program which is executed on a controller for controlling the test apparatus and provides a function common to each type of the test modules; and a plug-in processing program which is executed on the controller and plugs-in an individual function provision program for providing a function appropriate for the type of each of the test modules.Type: GrantFiled: April 23, 2007Date of Patent: December 29, 2009Assignee: Advantest CorporationInventors: Tetsu Katagiri, Takehisa Suzuki
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Patent number: 7627790Abstract: An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a precisely controlled jitter pattern. The IC also measures periods between selected edges of the same or different ones of the DUT output signal, the DUT input signal, and a reference clock signal. Additionally, when the DUT input and output signals convey repetitive patterns, the IC can measure the voltage of the DUT input out output signal as selected points within the pattern by comparing it to an adjustable reference voltage. Processing circuits external to the IC program the IC to provide a specified amount of jitter to the test signal, control the measurements carried out by the measurement circuit, and process measurement data to determine the amount of jitter and other characteristics of the DUT output signal, and to calibrate the jitter in the DUT input signal.Type: GrantFiled: November 18, 2004Date of Patent: December 1, 2009Assignee: Credence Systems CorporationInventors: Arnold M. Frisch, Thomas Arthur Almy
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Patent number: RE41343Abstract: Monitoring a converter (1) includes detecting whether a value of an input variable (2) for the converter (1) assumes a first prescribed input reference value (41) and checking whether an output variable (3) from the converter (1) likewise assumes a corresponding, second prescribed output reference value (61). This means that the operation of the converter is tested only at occasional instants, specifically only using individual, prescribed values. The fact that only prescribed values (41, 61) are compared with instantaneous values of the input and output variables (2, 3) means that the invention can be implemented using very simple means. The method is particularly suitable for monitoring the operation of a converter (1) in a control or protective device for an electrical switchgear assembly. In this context, when a malfunction in the converter (1) is detected, all protective functions which are dependent on the converter (1) are preferably turned off.Type: GrantFiled: June 10, 2005Date of Patent: May 18, 2010Inventor: Guido Wenning