Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Abstract: A method may include receiving, via a processor, an indication that a user is performing one or more activities on a project code. The method may then involve receiving an insurance policy associated with the user and the project code in response to receiving the indication, monitoring the one or more activities performed on the project code by the user, and determining whether the one or more activities correspond to one or more expected activities associated with the insurance policy. The method may also include sending a notification indicative of one or more inconsistent activities to a user device in response to the one or more activities not corresponding to the one or more expected activities.

Abstract: Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.

Abstract: Disclosed are various embodiments for improving the resiliency and performance of clustered memory. A computing device can generate at least one parity page from at least a first local page and a second local page. The computing device can then submit a first write request for the first local page to a first one of a plurality of memory hosts. The computing device can also submit a second write request for the second local page to a second one of the plurality of memory hosts. Additionally, the computing device can submit a third write request for the parity page to a third one of the plurality of memory hosts.

Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first plurality of sets of parity data to memory cells in the array that each protect data stored in a row of memory cells of the array can be written to the array. Further, a second plurality of sets of parity data to memory cells in the array that each protect data stored in a column of memory cells of the array can be written to the array. The first plurality of sets of parity data and the second plurality of sets of parity data can be sent to a processor for further ECC processing. Error correction data can be received from a processor that indicates a cluster of data that includes a threshold quantity of errors. An error correction can be performed on the cluster of data.

Abstract: A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.

Abstract: A memory system having non-volatile media and a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media. The non-volatile media has a set of memory units. The memory system stores an indicator indicating whether the memory system is operating in a user mode or a manufacturing mode. A defect manager of the memory system identifies a threshold based on the indicator, monitors an error rate in reading data from the non-volatile media and, in response to the error rate reaching the threshold, screens the non-volatile media for defective memory units.

Abstract: An error correction code (ECC) decoder includes a syndrome calculation block and a path controller. The syndrome calculation block is configured to perform a syndrome calculation for generating a syndrome from a codeword. The path controller is configured to output data transmitted through first to third paths. The first path is a path for transmitting the codeword to the path controller when no error is detected. The second path includes a single-error decoding logic circuit, and the single-error decoding logic circuit corrects a single error of the codeword to transmit the corrected codeword to the path controller through the second path. The third path includes a multi-error decoding logic circuit, and the multi-error decoding logic circuit corrects at least two errors of the codeword to transmit the corrected codeword to the path controller.

Abstract: A one-time programmable (OTP) memory can be programmed over a number of programming sessions in which each programming session writes a different portion of the memory. To provide the OTP memory with data integrity check capability, the OTP memory stores multiple error detection code entries. With each programming session, a new error detection code is stored in a previously unused entry. When the OTP memory is read, the error detection code corresponding to the latest programming session is used to verify the content of the OTP memory.

Abstract: Uncorrectable (UNC) marking on a non-volatile memory is provided. In response to a UNC marking command issued by a host, a cyclic redundancy check (CRC) engine provides a specific CRC code to mark a logical address segment as uncorrectable, wherein the logical address segment is requested to be marked as uncorrectable by the UNC marking command. As long as the specific CRC code is recognized, a CRC procedure is not required and the data requested by the host is directly determined as uncorrectable.

Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining features for each of a plurality of component codes corresponding to the data by decoding each of the plurality of component codes, determining an extrinsic value output for each of the component codes based on the features, and after the extrinsic value output for each of the component codes is determined, decoding each of the plurality of component codes based on the extrinsic value outputs of all other component codes of the component codes. Each of the component codes depends on all other component codes.

Abstract: An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.

Abstract: The present disclosure relates to a low-complexity syndrome based decoding apparatus and method and a low-complexity syndrome based decoding apparatus includes: a hard decision unit which performs hard decision on a current input value to output a hard decision vector; a syndrome calculator which performs a syndrome operation on the hard decision vector and determines an error type of the hard decision vector based on the syndrome operation result; and a decoder which selects a predetermined decoding algorithm in accordance with the error type to perform the decoding, and the error type includes at least one of no error, a single error, and a double error.

Abstract: An integrated circuit includes a receiver configured to receive a message word and an integrated hardware decoding circuit. The decoding circuit includes a calculation unit to calculate a syndrome of the message word according to a predetermined BCH code, a logarithmization unit to establish a logarithm of each of one or more syndrome components, an arithmetic circuit to establish a logarithm of each of one or more zeros of the error locator polynomial of the BCH code on the basis of the logarithms of the syndrome components, and a bit inverter circuit to invert the one or more bits of the message word, the positions of which are specified by the logarithms of the zeros of the error locator polynomial. The integrated circuit further includes a data processing circuit to process further the message word processed by the bit inverter circuit.

Abstract: A ring bus and a credit allocation method are provided. The ring bus includes a slave module and multiple master modules. The slave module includes an injection table and a state table, and is configured to generate a credit signal including a node identity and an active code. The master modules are coupled to the slave module to form a ring path. The slave module determines whether the credit signal is a newly injected credit signal, and determines the node identity of the credit signal according to the injection table or the state table. The slave module transmits the credit signal to the master module corresponding to the node identity through the ring path according to the node identity. The slave module uses a corresponding idle entry to receive a credit request signal provided by the master device consuming a credit of the credit signal.

Abstract: Technology for correcting memory read errors including a preprocessing majority logic decode based on a plurality of identity structures of a parity check matrix, before ECC decoding using the parity check matrix, to estimate a set of erased or punctured bits of a codeword.

Abstract: A decoding method includes that when encoding at a sending terminal, for a m-order primitive polynomial P(x), a primitive field element in galois field GF(2m) is represented by ?; a lookup table f(?j) for different power exponents of ? is established, where the value of j is selected from all the integers ranging from 0 to 2m?1, with a total number of 2m; a generator polynomial G(x) is expanded to obtain a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ?; a remainder polynomial R(x), obtained by dividing code word polynomial Q(x) by the generator polynomial G(x), is a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ?; and the coefficients of the generator polynomial G(x) and the remainder polynomial R(x) are both calculated using data found in the lookup table f(?j).

Abstract: According to one embodiment, a processing circuit is described including a first input path and a second input path, a processing element configured to receive a first input bit and a second input bit via the first input path and the second input path and configured to perform a logic operation which is commutative with respect to the first input bit and the second input bit and a sorter configured to distribute the first input bit and the second input bit to the first input path and the second input path according to a predetermined sorting rule.

Abstract: A data storage device includes a non-volatile memory and a controller operationally coupled to the non-volatile memory. The controller is configured to access information stored at the non-volatile memory. The information includes a user data portion and an error correcting code (ECC) portion corresponding to the user data portion. The controller is further configured to modify the ECC portion in response to an error rate associated with the information exceeding a threshold. The one or more ECC parameters are modified without erasing or re-programming the user data portion.

Abstract: A device includes a memory device coupled to an error correction code (ECC) decoder. The ECC decoder is configured to generate syndromes corresponding to a representation of a codeword received from the memory device and to perform a single decoding operation on a representation of data included in the representation of the codeword. The single decoding operation is configured to change at least one bit of the representation of the data based on a majority value of a group of the syndromes that are associated with the bit.

Abstract: A method of operation of a storage control system includes: partitioning memory channels with memory devices; selecting a super device with one of the memory devices from one of the memory channels; selecting a super block associated with the super device; and determining a location of a parity within the super block when the super block is formed.

Abstract: A device for correcting an initial binary word affected by an error in 1 or 2 bits and arising from a corrector code endowed with a minimum Hamming distance of 3 or 4, comprises first means for correcting an error of 1 bit and for detecting an error of more than 1 bit in the initial word and second means for correcting an error of 1 bit in a word arising from an inversion module, able to receive a datum indicative of a binary level of confidence, low or high, assigned to each of the bits of at least one part of the initial word, said inversion module being configured to invert the bits of the initial word which suffer the low confidence level, and a multiplexer with at least two inputs which is driven by the means for detecting an error of more than 1 bit in the initial word, said multiplexer being fed on a first input by the output of the first correction means and on a second input by the output of the second correction means.

Abstract: An error detection and correction circuit is provided that reduces the number of errors in a data signal sent over a high-speed serial link with little area overhead and without deteriorating the latency of the data transmission. An error detection and correction circuit on the transmit side may compute parity bits for each data packet of N bit-wise interleaved data packets and insert these parity bits into a serial data stream. A transmitter may send the serial data stream with the data packets and the parity bits over a high-speed serial link to a receiver. An error detection and correction circuit on the receive side may locate and correct single-bit errors and detect double-bit errors in each packet of the data signal. Thus, the error correction circuit may correct up to N errors in the N bit-wise interleaved data packets.

Abstract: An encoder provides (2t?1) redundant symbols in a sequence of n coded symbols, and a decoder corrects up to t erroneous symbols in the sequence of n coded symbols corrupted by a plurality of symbol errors. The decoder uses an improved decoding method, the method solving a plurality of matrix equations, each matrix equation associated with a hypothetical location of error. By monitoring a plurality of solutions associated with hypothetical locations of error, a processor determines the actual number of errors, the locations of the erroneous symbols in the sequence of n symbols, and the erroneous symbol value at each error location. The improved decoder includes erasure processing and a correct symbol determination method similar to erasure processing.

Abstract: Embodiments of the invention describe an apparatus, system and method for executing self-correction logic for serial-to-parallel data converters. Embodiments of the invention receive one of a plurality of serial data streams from a peripheral device, each of the serial data streams having one or more bits. In response to detecting that a shift register chain includes a register select value, embodiments of the invention may store the received serial data stream in one of a plurality of data registers, wherein the one data register is selected based, at least in part, on a position of the register select value in the shift register chain. In response to detecting the shift register chain does contain the register select value, embodiments of the invention may insert the register select value at a register of the shift register chain.

Abstract: Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and/or d) serially generating ECC and using an ECC serial decoder to correct the data.

Abstract: A system and method for enhanced auto-negotiation for NGBASE-T. Link partners can be configured to exchange advanced NGBASE-T configuration information such as type, profile, capability and mode information of the PHY in one or more next page messages. Determined cabling parameters that are reflective of communication channel characteristics can be used in the auto-negotiation selection of a configuration for NGBASE-T operation.

Abstract: Systems and methods for performing wear leveling are disclosed. In one implementation, a controller partitions a memory block into at least a first partition and a second partition. The controller utilizes the first partition of the memory block for storage of data blocks until the first partition reaches a first end of life condition. After the first partition reaches the first end of life condition, the controller utilizes the first partition for storage of data blocks associated with a compression ratio that is less than a compression threshold until the first portion reaches a second end of life condition. The controller additionally utilizes the second partition for the storage of data blocks until the second partition reaches the first end of life condition.

Abstract: A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

Abstract: A system is to receive a word on which to perform error correction; obtain segments, from the word, each segment including a respective subset of samples; update, on a per segment basis, the word based on extrinsic information associated with a previous word; identify sets of least reliable positions (LRPs) associated with the segments; create a subset of LRPs based on a subset of samples within the sets of LRPs; generate candidate words based on the subset of LRPs; identify errors within the word or the candidate words; update, using the extrinsic information, a segment of the word that includes an error; determine distances between the candidate words and the updated word that includes the updated segment; identify best words associated with shortest distances; and perform error correction, on a next word, using other extrinsic information that is based on the best words.

Abstract: A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic to compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold, the SSD stores the block of data without any compression. If it is possible to compress the block of data below the threshold, the SSD compresses the block of data and stores the compressed data in the SSD. In one embodiment of the invention, the SSD has logic to dynamically adjust or select the strength of the error correcting code of the data that is stored in the SSD. In another embodiment of the invention, the SSD has logic to provide intra-page XOR protection of the data in the page.

Abstract: Techniques for optimizing data storage are disclosed herein. In particular, methods and systems for implementing redundancy encoding schemes with data storage systems are described. The redundancy encoding schemes may be scheduled according to system and data characteristics. The schemes may span multiple tiers or layers of a storage system. The schemes may be generated, for example, in accordance with a transaction rate requirement, a data durability requirement or in the context of the age of the stored data. The schemes may be designed to rectify entropy-related effects upon data storage. The schemes may include one or more erasure codes or erasure coding schemes. Additionally, methods and systems for improving and/or accounting for failure correlation of various components of the storage system, including that of storage devices such as hard disk drives, are described.

Abstract: Embodiments related to retransmission in a communication system are described and depicted. In one embodiment, a retransmission entity repeats a transmission of a data transfer unit by the device after a predetermined number of other transmitted data transfer units has been transmitted. The retransmission entity may also determine whether a measure for a time period since the first transmission of the data transfer unit by the device has exceeded a predetermined threshold and to provide a final transmission of the data transfer unit based on the determining that the measure for the time period has exceeded the predetermined threshold.

Abstract: A memory system includes: a first non-volatile memory used for storing data to be accessed in block units; a second non-volatile memory used for storing data to be accessed in word units in random accesses to the second non-volatile memory; and a control section configured to control operations of the first and second non-volatile memories, wherein error correction codes to be applied to data stored in the second non-volatile memory are held in the first non-volatile memory.

Abstract: A first decoder performs decoding on each data set in a first plurality of data sets using a first code; each data set in the first plurality is stored on a different NAND Flash chip. It is determined if the first decoding is successful; if not, a second decoder performs a second decoding on each data set in a second plurality of data sets using a second code; each data set in the second plurality includes at least some data, after the first decoding using the first code, from each data set in the first plurality. The first decoder performs a third decoding on each data set in the first plurality using the first code, where each data set in the first plurality includes at least some data, after the second decoding using the second code, from each data set in the second plurality.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.

Abstract: A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code.

Abstract: A data storage device stores a data unit in a memory page of a storage block along with an error correction code unit for the data unit. Additionally, the data storage device stores an error correction code unit for the data unit in a memory page of another storage block. In various embodiments, one or both of the error correction code units form an error correction code for correcting data bit errors in the data unit. Because the memory page containing the data unit does not have a storage capacity for simultaneously storing the error correction code and the data unit, the data storage device is capable of correcting a greater number of data bit errors in the data unit by using the error correction code in comparison to using an error correction code that would fit in the memory page.

Abstract: According to one embodiment, an error correcting decoder includes a first error correction decoding module, an interleaving module, a delay module, a second error correction decoding module, and a corrector. The first error correction decoding module performs a first error correction decoding to a received signal in accordance with a broadcasting system. The interleaving module rearranges a data array of an output of the first error correction decoding module in a second order. The data array is ordered in a first order which is reverse to the second order. The delay module delays the received signal by a processing time of the first error correction decoding module. The second error correction decoding module performs a second error correction decoding to an output of the interleaving module and an output of the delay module. The corrector configured to correct a delay of an output of the second error correction decoding module based on a packet position defined by the broadcasting system.

Abstract: A system and method for transmitting high speed data on fixed rate and for variable rate channels. The system and method provides the flexibility of adjusting the data rate, the coding rate, and the nature of individual retransmissions. Further, the system and method supports partial soft combining of retransmitted data with previously transmitted data, supports parity bit selection for successive retransmissions, and supports various combinations of data rate variations, coding rate variations, and partial data transmissions.

Abstract: An improved error correction system, method, and apparatus provides encoded sequences of finite field symbols, each with a plurality of associated weighted sums equal to zero, and decodes encoded sequences with a limited number of corruptions. Each of the multiplicative weights used in the weighted sums is preselected from a smaller subfield of a large finite field. Decoding proceeds by determining multiplicative weights using various operations over the smaller subfield. When a limited number of corruptions occur, improved system design ensures that the probability of decoding failure is small. The method and apparatus extend to determine one or more decoding solutions of an underdetermined set of equations, including detection of ambiguous solutions.

Abstract: An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

Abstract: A system and method for achieving greater than 10 Gbit/s transmission rates for twisted pair physical layer devices. An architecture is provided that enables transmission at the next standardized transmission rate over structured cabling.

Abstract: A method for transmitting data is described that includes the steps of: Producing a data frame for transmission, the data frame including a sequence number and user data, saving a copy of the data frame in a retransmission buffer, and if said step of saving a copy requires that data already present in the retransmission buffer is overwritten, selecting the one or more oldest data frames in the retransmission buffer to be overwritten, in case an error is determined in the received data frame, communicating an error message to the transmitter of the data frame, which error message at least comprises an indication of the sequence number of the last correctly received data frame,—upon receipt of such message and if available, retransmitting one or more data frames from the retransmission buffer having a sequence number higher than the sequence number communicated in the message.

Abstract: Embodiments related to retransmission in a communication system are described and depicted. In one embodiment, a retransmission entity repeats a transmission of a data transfer unit by the device after a predetermined number of other transmitted data transfer units has been transmitted. The retransmission entity may also determine whether a measure for a time period since the first transmission of the data transfer unit by the device has exceeded a predetermined threshold and to provide a final transmission of the data transfer unit based on the determining that the measure for the time period has exceeded the predetermined threshold.

Abstract: Message-wise unequal error protection is provided using codeword flipping to separate special and ordinary codewords without discarding any codewords. Special messages are encoded to ensure the codeword weight is less than a certain threshold weight. Ordinary messages are encoded to ensure the codeword weight is greater than the threshold weight. The bits of the codeword are flipped to enforce the weight criterion. Ordinary and special messages are encoded using different encodings to provide different levels of error protection. Upon receipt, codewords are separated into special and ordinary codewords for appropriate decoding. If a codeword is of indeterminate type, it is iteratively processed as both a special codeword and an ordinary codeword. The decoding result of each process is periodically checked to determine which decoding result satisfies decoding criteria.