Abstract: Systems, methods and data structures are provided for representing robust data transmitted within a control system. The data structure includes at least two data fields identifying sub-modules and sub-modes of the control system, and optionally includes a third field for designating a primary operating mode of the control system and/or a fourth field representing a handshaking bit or value. The operating modes, sub-modes and sub-module designators are represented by values of the bits selected such that no single bit transition results in the selection of another valid operating state of the control system. As a result, single bit errors will not produce erroneous operating results. Similar concepts can be optionally applied to ensure that errors in contiguous sets of four, eight or any other number of bits do not produce valid states represented by the data structure.

Abstract: A digital broadcasting transmission/reception system, and a signal processing method thereof for turbo-processing digital broadcasting transport stream and transmitting the processed stream, includes a parity area generating unit preparing a first area for parity insertion with respect to a dual transport stream (TS) which includes a normal stream and a turbo stream as multiplexed, a first interleaver interleaving the dual TS which is transmitted from the parity area generating unit, a turbo processing unit detecting the turbo stream from the interleaved dual TS, exclusively encoding the detected turbo stream for turbo-processing, and stuffing the encoded turbo stream into the dual TS, a deinterleaver deinterleaving the dual TS which is processed by the turbo processing unit, and a transmitting unit transmitting the dual TS which is processed at the deinterleaver.

Abstract: A digital broadcasting transmission system, and a signal processing method thereof, includes a parity area generating unit preparing a first area for parity insertion with respect to a dual transport stream (TS) which includes a normal stream and a turbo stream as multiplexed, a first interleaver interleaving the dual TS which is transmitted from the parity area generating unit, a turbo processing unit detecting the turbo stream from the interleaved dual TS, exclusively encoding the detected turbo stream for turbo-processing, and stuffing the encoded turbo stream into the dual TS, a deinterleaver deinterleaving the dual TS which is processed by the turbo processing unit, and a transmitting unit transmitting the dual TS which is processed at the deinterleaver.

Abstract: A data-packing device, such as a direct memory access controller (DMA), aligns data at a granularity smaller than an error protected unit (EPU) encoded by an error correction code (ECC) in the memory. For example, the data alignment is at a double-word level or a byte level. The data-packing device reads data from the memory, shifting the data, and marks a good data unit as corrupted if the data unit constitutes a fractional portion of a corrupted EPU. The marking of the data unit is performed by inverting a parity bit of the data unit.

Abstract: A communications channel is provided, which includes a receive path having an iterative decoder and an ECC decoder. The iterative decoder has a soft channel detector with a soft output. The ECC decoder is coupled to decode bits produced from soft information received from the soft output and operates on the bits in a bit order that is the same as that on the soft output.

Abstract: An encoder signal processing device comprising an A/D converter converting a periodic analog signal, a memory storing position detection error information and a computing unit including a position data calculator which calculates position data from the digital data and an error correcting section which corrects the position data based on the position detection error information. The memory includes a first memory encoding position error data which is included in the position data by the use of the computing unit and storing a correction coefficient. A second memory decoding the position error data on the basis of the correction coefficient by the use of the computing unit and storing correction data for correcting the position data and error-containing position data generated on the basis of the encoded position error data.

Abstract: A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases among other techniques are described. In one embodiment, an apparatus is to comprise one or more logics to: generate a plurality of check bits based on a set of data, receive a codeword from a memory and to generate a syndrome based on the codeword, and to detect whether an error exists based on the syndrome. In another embodiment, a logic may classify the error if it exists. In a further embodiment, a logic may correct the error if it exists. Other embodiments are also disclosed.

Abstract: A data dependent scrambler for a communications channel that receives a user data sequence including N symbols each with M bits includes a seed finder that selects a scrambling seed and a first scrambler that receives said user data sequence and said scrambling seed from said seed finder. The first scrambler generates a scrambled user data sequence. A first encoder identifies a string of X consecutive zeros in adjacent symbols of the scrambled used data sequence and replaces one of the adjacent symbols with an all-one symbol. The first encoder replaces the other of the adjacent symbols with first bits representing a position of the string of X consecutive zeros and second bits representing bits of the adjacent symbols that are not in the string of X consecutive zeros.

Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.

Abstract: A method, apparatus, and computer-readable media comprises receiving a detected sequence representing a signal on a channel, wherein the detected sequence comprises data bits and one or more error detection code bits; receiving one or more error indications for the detected sequence, each of the one or more error indications identifying one of the data bits of the detected sequence that may have an erroneous value; detecting errors in the detected sequence based on the error detection code bits in the detected sequence; and generating a candidate sequence based on the detected sequence and the one or more error indications when errors are detected in the detected sequence.

Abstract: A high density high reliability memory module with power gating and a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length. The memory module also includes a first plurality of connector locations on the first side extending along a first edge of said board that extends the length of the board and a second plurality of connector locations on the second side extending on said first edge of said board. The memory module further includes a buffer device in communication with the circuit board for accessing up to four ranks of memory devices mounted on the first side and second side of the circuit board. In addition, a power savings means is included for causing all or a portion of the buffer device to be in an inactive mode in response to current activity at the memory module.

Abstract: A cache memory includes error bits corresponding to each line of data. An error detecting circuit uses these error bits to detect if a soft error has occurred within the data of a cache line. If such an error has occurred, then the line may be refilled from the main memory or some other action taken, such as a write back or generation of a soft error abort signal.

Abstract: Error correction on high speed interconnection links—backplane or extended wires (cable, optical fiber)—is exhaustively considered by many telecommunication vendors, especially those who offer “scalable router” products. Since the 64b/66b encoding scheme is a strong candidate of high speed interconnection protocol, error correction on 64b/66b encoded links is of interest. Although the IEEE 802.3 10G Ethernet standard does not specifically refer to packet loss, it can be shown that even only a single-bit error correction can significantly enhance the quality of the link. The present invention presents a simple and fast error-correction scheme that can be used in conjunction with the 64b/66b encoding in products where intra-board (chip-to-chip) or inter-shelf interconnections of high speed elements are required. It utilizes the CRC16 to optimize on error detection, correction, or both: it detects and corrects all single-bit errors and detects all multiple-bit errors.

Abstract: An FEC apparatus and method is provided that uses turbo codes. An input frame is iteratively decoded until an iterative decoding stop command is received under a predetermined control, and the absolute reliability of each symbol in the frame is output. The minimum of the absolute reliabilities is detected as a measurement, and a threshold is detected using the a-priori information and extrinsic information of the each symbol. The measurement is compared with the threshold, and the iterative decoding stop command is output according to the comparison result.

Abstract: An ECC circuit has an error correction function of N (N is a natural number) bits for output data of a memory cell array. A BIST circuit reads background data out of test target addresses, and writes/reads inverted data of the background data in at least a part of the testing target addresses. An N+1 bit error detection circuit outputs a signal indicative of test NG (defective product) when a total of error bit numbers n1 and n2 detected by the ECC circuit during first and second readings exceeds N.

Abstract: Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.

Abstract: System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted.

Abstract: The present invention concerns a method for obtaining an error correcting code of a given first size (N), including a systematic information part of a given second size (K) and a redundancy part. A block turbo-code is first obtained from said systematic information part and from predetermined information elements provided at known locations, said block turbo-code consisting in a product of elementary systematic block codes, at least said predetermined information elements being removed from the obtained block turbo-code to produce a shortened block turbo-code. An additional error correcting code is derived from at least a portion of said shortened block turbo-code and said shortened block turbo-code is stuffed with stuffing elements so as to attain said given first size, said stuffing elements being information elements of said additional error correcting code.

Abstract: An equalizing and error correcting section includes an equalizing section, an error processing sections, and a select section. The equalizing section outputs the received data subjected only to channel compensation and phase rotation compensation and the received data subjected not only to those compensations but also to power amplifier distortion compensation. These two received data items are subjected to an error process separately at the error processing sections. On the basis of the decisions at the error processing sections, the select section makes a final decision whether the receiving process has been successful or unsuccessful. That is, if either of the two decisions has been successful, the receiving process is regarded as successful. Only if both of the two decisions have been unsuccessful, the receiving process is regarded as unsuccessful.

Abstract: The inventive mechanism detects wire stuck-at faults, which can be used with any other ECC code. The inventive mechanism determines the number of 1's (or 0's) in the data portion and the ECC code of the data portion. This counted number is then provided with ECC code. The data portion, its ECC, the counted number, and its ECC are transmitted to the destination. At the destination, the message is decoded, and the number of 1's in the received message is compared with the counted number, if there is a discrepancy, then a wire fault is signaled. The mechanism may also detect any number of faults provided the number of 0 to 1 transitions is not the same as the number of 1 to 0 transitions. The mechanism can be reconfigured to work with any transmission wire width.

Abstract: A digital magnetic recording/reproducing apparatus includes an LVA (List Viterbi Algorithm) detector which produces first to nth best sequences (n>1) of a decoded result, and replaces a likelihood ratio and a path memory of the ith best sequence (i=2, 3, . . . , n) with those of the (2i?1)th best sequence when contents of path memories of the (i?1)th and ith best sequences are equal to each other and an absolute value of a difference between likelihood ratios of the (i?1)th and (2i?1)th best sequences is smaller than a decision threshold. Alternatively, the LVA detector initializes a likelihood ratio of the ith best sequence to be a likelihood ratio of the (i?1)th best sequence with a constant difference value added thereto when contents of path memories of the (i?1)th and ith best sequences are equal to each other.

Abstract: As disclosed herein, an interface for a device adapted to couple to an interconnect may comprise decode and error check logic and a plurality of decode logic units. The decode and error check logic may receive error check bits and a target address from the interconnect and may determine whether the target address was received in error. At least one of the decode logic units also may receive the error check bits and correct the target address using the error check bits in parallel with the decode and error check logic determining whether the target address was received in error.

Abstract: A method is provided for transmission of packets (102) as a sequence of data packets (104). A redundancy or check word (106) is composed for each packet of the sequence of data packets. A transmission packet is composed of a packet, a check word of a prior packet in the sequence of packets, and a check word of a subsequent packet in the sequence of packets. The transmission packets are transmitted in a sequence and received in a sequence. After reception, the transmission packets are separated so that the packets are compared with the corresponding check words transmitted with adjacent packets in the sequence.

Abstract: According to an error detection and correction method to be implemented in a computer system, when an error is detected in data to be written in a memory, fault information is appended to the data without an increase in the number of bits constituting the data, and the resultant data is stored in the memory. An error control code represented by a SEC-DEC code is adopted for encoding and decoding. Data is encoded into a shortened code. At this time, specific bit positions associated with column vectors deleted from a parity check matrix defined in the error control code are allocated to fault information. Thus, a word to be actually stored in the memory is composed of check bits produced from data to be written and fault information, and information bits constituting the data to be written. Decoding is performed on the assumption that the fault information represents 0s. When data having fault information appended thereto is decoded, the fault information is reproduced through error detection and correction.

Abstract: The present invention discloses an information processing method including the following steps:

Abstract: A first stage inner code decoder performs a first error correction process for a plurality of inner code words. A first stage outer code decoder performs a second error correction process for a plurality of outer code words. A second stage inner code decoder performs a third error correction process for one or more inner code words whose number of errors has been decreased by the second error correction process and skips the third error correction process for one or more inner code words whose number of errors has not been decreased by the second error correcting process.

Abstract: An apparatus and method is provided for correcting data words resulting from a package fail within a memory array in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure. The invention correcting exploits single error correcting (SEC)-and double error detecting (DED) codes, requiring no additional check bits, which give a syndrome when the data word has suffered an error coming from at least one error in a package.

Abstract: A cache memory includes a plurality of lines of memory and a plurality of cache coherency state registers. Each of the plurality of cache coherency state registers is associated with one of the plurality of lines of memory. Each of the plurality of cache coherency state registers further includes four elements having one of a first value and a second value to form a four bit code for a MESI Protocol. The four bit code provides a first set of codes having a minimum distance of two from every other code, and a second set of codes having a minimum distance of three from every other code. The first set of codes includes a first code representing an Invalid state, a second code representing a Shared state, and a third code representing an Exclusive state. The second set of codes includes a fourth code representing a Modified state.

Abstract: System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted.

Abstract: A method for correction of errors in a word stored in multi-bit memory cells includes associating a full error code, which includes bit error codes and a set error code, for each set of bits of the word stored in a single memory cell. The method includes associating, with each single error, a bit error code which is not associated with other errors and which is indicative of a position of the bit in the word. The set error code is computed based on the bit error codes associated with the bits in the set. The method also checks to make sure that the full error code for the set has not already been associated with other errors. If the error code has already been used for another error, then the method changes both the set error code and at least one of the bit error codes.

Abstract: A method for generating correction codes that can correct a single error and detect two adjacent errors in an information word for a range of (n, k) values, where k denotes the length of the information word in bits and n denotes the length of the coded information word in bits. The method generates a parity check matrix, then multiplies a received word by the parity check matrix to produce a syndrome corresponding to one of two mutually exclusive sets of syndromes if the word contains at least one error. Information in the word is corrected by inverting a bit containing an error if the produced syndrome corresponds to one of the sets of syndromes. An uncorrectable two bit adjacent error is reported if the produced syndrome corresponds to the other of the two sets of syndromes and no error is reported if the produced syndrome contains all zeros.

Abstract: Error control coding is applied to data streams transmitted through transmission equipment such as a telecommunications switch having a distributed synchronous switch fabric. Each k-symbol dataword is encoded to generate an n-symbol codeword that is then sliced for transmission through the transmission equipment. After routing, error-correction decoding is applied to the resulting routed n-symbol codeword to detect and correct one or more errors in the codeword to generate a k-symbol routed dataword that is identical to the original incoming dataword. Depending on the coding scheme, different types and numbers of errors can be corrected in each codeword. For example, for Reed-Solomon [12, 8, 5] coding with Galois field (24), corrections can be made for up to four erasures with no random errors, up to two erasures and one; random error, or up to two random errors with no erasures.

Abstract: A decoding apparatus and decoding method for performing iteration decoding the suitable number of iterations, and thereby securing the desired transmission quality while decreasing the processing delay. Turbo decoder 301 iterates error correcting decoding on input coded sequences. Error checker 302 decodes an error detecting code contained in a decoded result of the error correcting decoding, and checks whether or not an error remains in the decoded result in turbo decoder 301. Iteration controller 303 instructs turbo decoder 301 to continue the iteration decoding until the number of iterations in the iteration decoding is more than or equal to the constraint number of iterations and error checker 302 determines no error in the decoded result.

Abstract: A method and an apparatus for receiving partially error protected data. A transmission of a binary code is received. The binary code is selected from a first set of codes having a first minimum distance from every other code and a second set of codes having a second minimum distance from every other code. The second minimum distance is greater than the first minimum distance. A first single bit error in the transmission is detected if the transmission is a distance of one unit from one of the codes in the second set of codes.

Abstract: The inventive mechanism detects wire stuck-at faults, which can be used with any other ECC code. The inventive mechanism determines the number of 1's (or 0's) in the data portion and the ECC code of the data portion. This counted number is then provided with ECC code. The data portion, its ECC, the counted number, and its ECC are transmitted to the destination. At the destination, the message is decoded, and the number of 1's in the received message is compared with the counted number, if there is a discrepancy, then a wire fault is signaled. The mechanism may also detect any number of faults provided the number of 0 to 1 transitions is not the same as the number of 1 to 0 transitions. The mechanism can be reconfigured to work with any transmission wire width.

Abstract: The present invention provides checking on information units sent and received as packets over fiber channel networks by providing check bits on the header information and separate check bits on the data.

Abstract: According to an error detection and correction method to be implemented in a computer system, when an error is detected in data to be written in a memory, fault information is appended to the data without an increase in the number of bits constituting the data, and the resultant data is stored in the memory. An error control code represented by a SEC-DEC code is adopted for encoding and decoding. Data is encoded into a shortened code. At this time, specific bit positions associated with column vectors deleted from a parity check matrix defined in the error control code are allocated to fault information. Thus, a word to be actually stored in the memory is composed of check bits produced from data to be written and fault information, and information bits constituting the data to be written. Decoding is performed on the assumption that the fault information represents 0s. When data having fault information appended thereto is decoded, the fault information is reproduced through error detection and correction.

Abstract: The present invention provides a memory system that optimizes, during a sleep mode, a refresh period for a memory device, such as DRAM, which stores meaningful data and for which a refresh operation is required to prevent the loss of data.

Abstract: A packet error detecting device for detecting the existence of an error of the packet data transferred by a packet switching in a DMA transfer, comprising an operation unit formed by hardware for executing a necessary operation to detect a packet error in the packet data received in every block, a DMA controller for DMA transferring data from a memory storing the received data to the operation unit, previous to the DMA transfer of the data toward an external device, and a CPU for performing an error procedure if detecting a packet error as the result of the error detection by the operation unit.

Abstract: A digital modulation circuit which minimizes a DC component of an NRZI modulated code sequence while setting the T.sub.max and T.sub.W not to be varied. An m-n coding mode is determined for each data block composed of the predetermined number of m-bit datawords. That is, an m-n coding mode which minimizes the absolute value of the DSV is selected and the selected m-n coding mode is utilized for the m-n coding of the current data block. The code indicating the selected m-n coding mode is multiplexed to the m-n coded current block. An m--m mapping table is also determined for each data block. That is, such an m--m mapping table that minimizes the absolute value of the DSV is selected and the selected m--m mapping table is utilized for the m--m translation of the current data block. Then, the m--m mapped data block is m-n translated into a code block composed of the same number of n-bit codewords by utilizing the single m-n translation table.

Abstract: The invention discloses techniques for providing automatic retransmission query (ARQ) functions in a communication system. A transmitter in the system applies an input data packet to a first convolutional encoder operating at a first rate to generate an inner code including multiple encoded packets. The encoded packets are interleaved and applied to a second convolutional encoder operating at a second rate which generates an outer code including a transmit packet generated from each of the encoded packets. A first transmit packet is sent to a receiver, which decodes the transmit packet in a Viterbi decoder operating at the second rate to generate a decoded version of the first transmit packet. The decoded version is inverted to provide a first provisional decoding of the input packet. If a cyclic redundancy code (CRC) check of the first provisional decoding is passed, the receiver sends an ACK signal to the transmitter and no retransmission is required.

Abstract: On-line memory monitoring system and methods wherein memory subsystem performance is tracked to detect substandard performance and alert a system administrator of the nature of the substandard performance so corrective action can be taken before a system crash and/or automatic reset occurs. A computer system incorporating the invention includes a memory and a processor, wherein the memory storage includes data storage and error correction code storage for each dataword. The system further includes automatic error detection and correction circuitry and software which monitors the occurrence of correction of errors and compares their frequency with the known frequency of soft errors for the memory devices being used to determine whether an alert is to be given and the nature of any such alert.