Abstract: A method of generating a codeword for a control signal in a wireless communication system is provided. The method includes preparing a control signal and generating a codeword by applying a Reed-Muller (RM) extension matrix to the control signal. The RM extension matrix is generated by extending a RM basic matrix. A control signal can reliably be transmitted by the codeword with low complexity.

Abstract: Methods, systems, and apparatus, including computer program products, featuring generating a plurality of error-correcting code chunks from a plurality of data chunks. The error-correcting code chunks can be used to reconstruct one or more of the data chunks. The data chunks are allocated to a local group of storage nodes. The error correcting code chunks are allocated between the local group of storage nodes and one or more remote groups of storage nodes. Each remote group of storage nodes is allocated one or more unique error-correcting code chunks from the error-correcting code chunks. Any of the error-correcting code chunks not allocated to a remote group of storage nodes are allocated to the local group of storage nodes.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m-1 is received. A code word with length N=2m-1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 ? … ? N - 1 1 ? - 1 … ? - N + 1 ] . The number of parity bit is given by (2m+1).

Abstract: In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding interleavers/deinterleavers in the different subword-processing paths use different interleaving/deinterleaving algorithms.

Abstract: An enhanced four rank enabled buffer device that includes input ports for receiving input data that includes address and command data directed to one or more of up to four ranks of memory devices. The buffer device also includes one or more buffer circuits for driving one or more of the address and command data, a plurality of chip select input lines for selecting between the up to four ranks of memory devices, and a plurality of chip select output lines for accessing the up to four ranks of memory devices. The buffer device further includes a power savings means for causing one or more of the buffer circuits to be in an inactive mode when corresponding chip select input lines are not active. The buffer device is operable to access the up to four ranks of memory devices.

Abstract: The invention is directed to a method and apparatus for decoding encoded data symbols. The invention is also directed to corresponding encoding methods. The decoder arrangement comprises an input for receiving encoded data and an identifier associated with a coding scheme used to create said encoded data. A processor in the decoding arrangement determines from the identifier, a mapping between said encoded data and the original data. A decoder uses the mapping to extract the original data from the encoded data. The operation of the decoder is independent of the coding scheme used in the encoding process.

Abstract: A system and method for achieving greater than 10 Gbit/s transmission rates for twisted pair physical layer devices. An architecture is provided that enables transmission at the next standardized transmission rate over structured cabling.

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.

Abstract: A memory system accesses a block of data, each block including bits logically divided into rows and columns, each column including a row-checkbit column, an inner-checkbit column, and data-bit columns. Each column is stored in a different memory component, and checkbits are generated from databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. The system calculates a row syndrome and an inner syndrome for the block of data, the inner syndrome resulting from any two-bit error in the same row being unique. The system can use the row and inner syndromes to determine whether errors are associated with a failed memory component. If not, the system can use the row and inner syndromes, and inner syndromes for all possible combinations of one-bit errors occurring in two rows with a row syndrome of one to correct two bits.

Abstract: A system that provides error detection and correction for a memory that has a specific failed memory component accesses a block of data from the memory. Each block of data includes an array of bits logically organized into rows and columns, including a column including row-checkbits, a column including inner checkbits and data bits, and columns containing data bits. Each column is stored in a different memory component and the checkbits are generated from the data bits. Next, the system attempts to correct a column of the block by using the checkbits and the data bits to produce a corrected column. The system then regenerates row-parity bits and the inner checkbits for the block of data, wherein the block includes the corrected column, and compares the regenerated row-parity bits and inner checkbits with existing row-parity bits and inner checkbits.

Abstract: A test pattern generating device generates a test pattern with respect to a semiconductor circuit having first and second common circuits and a non-common circuit, wherein each of the common circuits has a scan chain for checking an operation of the circuit by applying a test pattern from the outside of the circuit. A set of scan chains and a set of assumed faults are created for each of the common circuits. Any of the common circuits is determined as the common circuit of a first test target. After the determined common circuit of the first test target is subjected to ATPG and detection of circuit fault, a test pattern generated in successful ATPG about the common circuit of the first test target is diverted to the common circuit determined as the second test target, and ATPG and detection of a circuit fault of the non-common circuit part.

Abstract: Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed.

Abstract: An apparatus for generating a linear code according to the present invention includes a coding unit for coding input bits with a second coding scheme which is different from a first coding scheme for generating the linear code; and a rearrangement unit for generating the linear code by rearranging the bits coded with the second coding scheme. The present invention can provide a coding apparatus and method capable of reducing complexity by adaptively applying it to various coding scheme.

Abstract: An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits.

Abstract: A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words.

Abstract: A decoding device includes a first receiving section for receiving a data packets, a second receiving section for receiving a plurality of error correction packets which includes matrix configuration information regarding the plural data packets, a deciding section for deciding a number of packets to be accumulated to restore a lost data packet, based on the matrix configuration information, an accumulating section for accumulating the data packets received by the first receiving section in the number of packets to be accumulated, and a restoring section for, when a loss of any of the data packets received by the first receiving section is detected, restoring the lost data packet by using at least one of the data packets and the error correction packets.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

Abstract: A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.

Abstract: An memory device including a data region storing a main data, a first index region storing a count data, and a second index region storing an inverted count data, where the data region, the first index region, and the second index region are included in one logical address.

Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.

Abstract: A network device includes input logic and output logic. The input logic receives multiple packets, where each of the multiple packets has a variable length, and generates a first error detection code for one of the received multiple packets. The input logic further fragments the one of the variable length packets into one or more fixed length cells, where the fragmentation produces a cell of the one or more fixed length cells that includes unused overhead bytes that fill up the cell beyond a last portion of the fragmented one of the variable length packets, and selectively inserts the first error detection code into the overhead bytes. The input logic also forwards the one or more fixed length cells towards the output logic of the network device.

Abstract: An encoding system for encoding error control codes may include a first encoder configured to encode an input bit stream to generate first bit streams of C-bits, where c is an integer greater than zero, and a second encoder may be configured to receive the first bit streams and shuffle data of the received first bit streams to generate second bit streams. The data shuffling of the first bit streams may adjust an error distribution of the second bit streams. An encoding method may include encoding an input bit stream to generate first bit streams of C-bits, and receiving the first bit streams and shuffling data of the received first bit streams to generate second bit streams. An error distribution of the second bit streams may be adjusted based on the data shuffling.

Abstract: An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code (“ECC”) generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells as a plurality of data bit strings in a first direction and as a plurality of data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC generator generates a respective correction code in the first direction for each data bit string in the first direction and also generates a respective correction code in the second direction for each data bit string in the second direction. The ECC controller is coupled to the memory cells and the ECC generator.

Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.

Abstract: A data processing circuit includes a receive circuit that receives data including a control bit for controlling a process of the data, a hold circuit that holds the received data, an error detection circuit that detects an error in the received data, a first correction circuit that corrects the received data when an error of the control bit in the received data is detected, and outputs the corrected data, and an output select circuit that outputs data held in the hold circuit when no error is detected in the control bit, and outputs the corrected data outputted from the first correction circuit when an error is detected in the control bit.

Abstract: Multiple cyclic redundancy check (CRC) engines for checking/appending CRCs during data transfers. Two distinctly implemented CRC engines are employed to enable the processing of different sized byte formats at two ends of a communication channel. These two distinctly implemented CRC engines can be employed to enable the processing of different sized byte formats in a host device at one end and an hard disk drive (HDD) at another end. For example, sometimes the size of blocks, frames, and/or sector sizes that are processed and employed within a first communication device at one end of a communication channel can differ from the size of blocks, frames, and/or sector sizes that are processed and employed within a second communication device at another end of the communication channel. Two distinctly implemented CRC engines allow the appropriate processing and translation of any desired different sized blocks, frames, and/or sector sizes of a communication channel.

Abstract: An enhanced mechanism for the allocation, organization and utilization of high performance block storage metadata provides a stream of data (e.g., in a server system, storage system, DASD, etc.) that includes a sequence of fixed-size blocks which together define a page. Each of the fixed-size blocks includes a data block and a footer. A high performance block storage metadata unit associated with the page is created from a confluence of the footers. Each footer in the confluence of footers has space available for application metadata, which are provided as one or more information units. At least one of the footers includes a Checksum field containing a checksum that covers at least the confluence of footers. This approach is advantageous in that it provides data integrity protection, protects against stale data, and significantly increases the amount of metadata space available for application use.

Abstract: There are provided a content data transmission method, device, and program that minimize serious disturbances in reproduced content on the reception side, caused by a transmission error of encoded data, without sending feedback information from the reception side to the transmission side. When an encoder creates encoded data to be distributed, the encoder creates plural items of encoded data at the same time or creates FEC data at the same time in advance and, when storing the data in a file, stores the data as if the data were one item of encoded data. When a distribution server distributes the data using the file, the plurality of items of encoded data are automatically distributed at the same time and the FEC data is distributed. A client receives the plurality of items of encoded data or the FEC data to reduce the probability of data shortage due to a packet loss and, as a result, the deterioration in the image quality and the audio quality is reduced.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: Provided are systems, methods and techniques that use an embedded error-detection code within a received communication signal to determine when to stop iterative decoding of the communication signal.

Abstract: Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code is applied to configuration data. Thus, the higher overhead required for a Hamming code applies to only a few words in the bitstream. The instructions are corrected on receipt of the word that includes the Hamming code, so the instructions are executed correctly even if a transmission error has occurred. However, configuration data can be stored in the configuration memory without correction. With a product code, the exact location of an erroneous bit is not known until the end of the transmission, when a parity word is received. At this time, the PLD can go back and correct erroneous bits in the configuration data prior to enabling the newly loaded design.

Abstract: A receiver that receives a digital signal transmitted on the basis of an orthogonal frequency division multiplexing (OFDM) method. This receiver comprises a demodulation unit for demodulating the digital signal, a demapping unit for demapping demodulated data output from the demodulation unit, a frequency deinterleave unit for executing a frequency deinterleaving process on data output from the demapping unit, a delay unit for delaying control information superposed on the digital signal by a prescribed time period, and a time deinterleave unit for executing, on the basis of the interleave length specified by the control information delayed by the delay unit, a time deinterleaving process on data on which the frequency deinterleaving process has been executed.

Abstract: There are provided a content data transmission method, device, and program that minimize serious disturbances in reproduced content on the reception side, caused by a transmission error of encoded data, without sending feedback information from the reception side to the transmission side. When an encoder 103 creates encoded data to be distributed, the encoder creates plural items of encoded data at the same time or creates FEC data at the same time in advance and, when storing the data in a file 104, stores the data as if the data were one item of encoded data. When a distribution server 105 distributes the data using the file 104, the plurality of items of encoded data are automatically distributed at the same time and the FEC data is distributed. A client 106 receives the plurality of items of encoded data or the FEC data to reduce the probability of data shortage due to a packet loss and, as a result, the deterioration in the image quality and the audio quality is reduced.

Abstract: Time-space encoding and/or decoding may employ time variant linear transformations. Turbo coding and/or decoding may be used in conjunction with the use of time variant linear transformations. Such time variant linear transformations may be unitary in nature.

Abstract: A high density high reliability memory module with power gating and a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length. The memory module also includes a first plurality of connector locations on the first side extending along a first edge of said board that extends the length of the board and a second plurality of connector locations on the second side extending on said first edge of said board. The memory module further includes a buffer device in communication with the circuit board for accessing up to four ranks of memory devices mounted on the first side and second side of the circuit board. In addition, a power savings means is included for causing all or a portion of the buffer device to be in an inactive mode in response to current activity at the memory module.

Abstract: Systems and methods are provided for encoding a stream of datawords based on a tensor product code to provide a stream of codewords, and detecting and decoding a stream of received data based on a tensor product code to provide a decoded stream of data. In one aspect, the tensor product code is based on two codes including an inner code and an outer parity hiding code, where the outer parity hiding code is an iterative code. In certain embodiments, the outer parity hiding code is a Turbo code or a low density parity check (LDPC) code.

Abstract: There are provided a content data transmission method, device, and program that minimize serious disturbances in reproduced content on the reception side, caused by a transmission error of encoded data, without sending feedback information from the reception side to the transmission side. When an encoder creates encoded data to be distributed, the encoder creates plural items of encoded data at the same time or creates FEC data at the same time in advance and, when storing the data in a file, stores the data as if the data were one item of encoded data. When a distribution server distributes the data using the file, the plurality of items of encoded data are automatically distributed at the same time and the FEC data is distributed. A client receives the plurality of items of encoded data or the FEC data to reduce the probability of data shortage due to a packet loss and, as a result, the deterioration in the image quality and the audio quality is reduced.

Abstract: An apparatus includes a source for a command and an associated data. An error code generator generates an error code for the combined command and associated data, which is distributed among the command and the associated data. A transmitter then transmits the command and the associated data separately.

Abstract: In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.

Abstract: An enhanced four rank enabled buffer device that includes input ports for receiving input data that includes address and command data directed to one or more of up to four ranks of memory devices. The buffer device also includes one or more buffer circuits for driving one or more of the address and command data, a plurality of chip select input lines for selecting between the up to four ranks of memory devices, and a plurality of chip select output lines for accessing the up to four ranks of memory devices. The buffer device further includes a power savings means for causing one or more of the buffer circuits to be in an inactive mode when corresponding chip select input lines are not active. The buffer device is operable to access the up to four ranks of memory devices.

Abstract: A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item.

Abstract: An encoder for encoding data from a communication channel, comprises a first address generator to generate a first address in accordance with the user data. A linear block encoder encodes the user data in response to the first address from the first generator. A transmitter transmits an output of the linear block encoder to the communication channel.

Abstract: A method and apparatus for transmitting/receiving a Voice over Internet Protocol (VoIP) packet on a radio link in a mobile communication system which provides a voice service over a packet network connected to the Internet. To transmit a VoIP packet, a VoIP packet comprising a user datagram protocol (UDP) checksum field is received, the UDP checksum field is eliminated from the received VoIP packet, a cyclic redundancy check (CRC) is added to the UDP checksum field-free VoIP packet, for error detection in the radio link, and the VoIP packet having the CRC is transmitted on the radio link.

Abstract: A system for conveying information includes a signal transport device. The signal transport device includes a set of links operable to convey a first set of information signals from a first computer module to a second computer module and a link operable to convey a transaction request credit signal associated with the first set of information signals, the signal indicating whether at least a portion of a transaction request message may be sent using the first set of information signals. The device also includes a set of links operable to convey a second set of information signals in the opposite direction of the first set of information signals and a link operable to convey a transaction request credit signal associated with the second set of information signals, the signal indicating whether at least a portion of a transaction request message may be sent using the second set of information signals.

Abstract: A method of error correction includes retrieving raw data from a memory device during a first operational phase of the error correction device. The raw data is retrieved by a bus interface device that interfaces with a variety of memory devices. During a second operational phase, the raw data is outputted from the bus interface device to the bus master. In addition, error correction data is calculated, and error correction is performed on the raw data during the second operational phase. By retrieving the raw data before performing error correction, and by outputting the raw data during the same operational phase, data may be retrieved from the memory more rapidly.

Abstract: Described are an iterative decoder and method for implementing an iterative decoder which can be used for error correction in data communications. In one implementation, the method includes implementing a first function including a first plurality of Gilbert cells, and implementing a second function including a second plurality of Gilbert cells, where examples of the first and second functions include an equality constraint function and a parity check function. Each of the first plurality of Gilbert cells and the second plurality of Gilbert cells includes n m-input Gilbert multipliers, in which n is an integer greater than (3) and m=(n?1).

Abstract: A data processing apparatus and method for a flash memory, which make it easy to determine whether data stored in the flash memory is valid, are provided. The data processing apparatus includes a user request unit which issues a request for performing a data operation on a flash memory using a predetermined logical address, a conversion unit which converts the logical address into a physical address, and a control unit which performs the data operation on the physical address and writes inverted data obtained by inverting error correction code (ECC) corresponding to data used in the data operation to a region indicating whether the ECC is erroneous.

Abstract: A multimedia distribution system is disclosed. The distribution system includes a transmitter unit that distributes content from a content provider to one or more wireless subscriber units. The transmitter unit includes a decoder configured to determine whether a plurality of incoming packets include one or more erasures, a transmitter configured to transmit the packets to a receiving unit, and an error detection code generator configured to generate an error detection code for each of the packets transmitted to the receiver unit, the error detection code being modified for each of the erased packets so that the receiver unit will be able to identify the erased packets.