Double Encoding Codes (e.g., Product, Concatenated) Patents (Class 714/755)
  • Patent number: 10972127
    Abstract: The present disclosure provides a decoding system and method. The decoding system comprises a first decoder and a second decoder. The first decoder is configured to generate an intermediate decoding data by decoding a code data. The second decoder, coupled to the first decoder, wherein the second decoder is configured to generate a plain data by decoding the intermediate decoding data.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 6, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Huang, Hsi-Chia Chang
  • Patent number: 10969969
    Abstract: An approach to identifying problematic data storage devices, such as hard disk drives (HDDs), in a data storage system involves retrieving and evaluating a respective recovery log, such as a media error section of a device status log, from each of multiple HDDs. Based on each recovery log, a value for a Full Recoveries Per Hour (FRPH) metric is determined for each read-write head of each respective HDD. Generally, the FRPH metric characterizes the amount of time a head has spent performing recovery operations. In response to a particular head FRPH reaching a pre-determined threshold value, an in-situ repair can be determined for the HDD in which the head operates. Similarly, in the context of solid-state drives (SSDs), a latency metric is determinable based on time spent waiting on resolving input/output (IO) request collisions, on which an in-situ repair can be based.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert Lester, Timothy Lieber, Austin Striegel, Evan Richardson, Donald Penza
  • Patent number: 10972218
    Abstract: An electronic device and a method of operating the electronic device in a wireless communication system are provided. The method includes determining whether to perform a partial decoding or a normal decoding based on a channel quality; if partial decoding is performed, decoding partial data received by a transceiver from a second electronic device during a part one TTI; when the decoding of the partial data succeeds, performing at least one complementary decoding until a decoding success count reaches a decoding threshold; and when the decoding success count reaches the decoding threshold, outputting a decoding result for the at least one complementary decoding; and if normal decoding is performed, decoding all data of the one TTI and outputting a result. One of the at least one complementary decoding comprises decoding previous data, and additional data received by the transceiver during an additional part of the one TTI, after the previous data.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 6, 2021
    Inventors: Shinwoo Kang, Soobok Yeo, Mingoo Kim, Chaehag Yi, Juhyuk Im
  • Patent number: 10963178
    Abstract: A repetitive data processing method for a solid state drive is provided. The solid state drive includes a non-volatile memory. The repetitive data processing method includes the following steps. Firstly, a write data is received. The write data contains plural codewords. Then, an encoding operation is performed on the plural codewords sequentially, thereby generating plural error correction codes sequentially. If at least two consecutive error correction codes of the plural error correction codes are identical to a first error correction code, the solid state drive confirms that the write data contains a repetitive data and enabling a repetitive data management mechanism.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: March 30, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventor: Chih-Ming Huang
  • Patent number: 10965318
    Abstract: Systems and methods are described for performing Layered Belief LDPC decoding on received Standard Belief LDPC encoded data bursts. In on implementation, a receiver: demodulates a signal, the demodulated signal including a noise corrupted signal derived from a codeword encoded using standard belief LDPC encoding; converts the noise corrupted signal derived from the standard belief LDPC encoded codeword to a noise corrupted signal derived from a layered belief LDPC encoded codeword; and decodes the noise corrupted signal derived from the layered belief LDPC encoded codeword using a layered belief LDPC decoder. In further implementations, systems are described for reducing collisions in Layered Belief LDPC decoders that occur when multiple parity checks need the same soft decision at the same time. In these implementations, elements in an original LBD decoder table are rearranged to increase the distance between elements specifying the same location in a RAM where soft decisions are stored.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 30, 2021
    Assignee: HUGHES NETWORK SYSTEMS, LLC
    Inventors: Gaurav Bhatia, Qiujun Huang, Mustafa Eroz
  • Patent number: 10958294
    Abstract: The present disclosure provides a decoding device. The decoding device includes an iteration number computing unit and a recursive decoder. The iteration number computing unit receives multiple packet parameters corresponding to a packet and computes a codeword-number-per-symbol according to packet parameters, in which the packet includes multiple symbols. The iteration number computing unit computes an iteration number according to the codeword-number-per-symbol. The recursive decoder is coupled to the iteration number computing unit, and performs a decoding operation on a codeword within a data field of the packet according to the iteration number.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 23, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wei-Chieh Huang, Chung-Yen Liu, Yi-Syun Yang, Chung-Yao Chang
  • Patent number: 10958430
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device receives (e.g., via the DSN and from a first other computing device) a storage request that is based on data object. The computing device extracts a remote address (associated with the first other computing device) from the storage request. The computing device processes the storage request to determine whether any principals are associated with the storage request, wherein the principals include DSN system entities.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 23, 2021
    Assignee: PURE STORAGE, INC.
    Inventors: Jason K. Resch, Wesley B. Leggette
  • Patent number: 10951239
    Abstract: A set of bits of a data block that is associated with an unsuccessful first decoding operation may be identified. A second decoding operation to simulate switching at least one bit of the set of bits may be performed. At least one bit of the set of bits switched during the performance of the second decoding operation may be determined to correspond to an error. The error from the at least one bit of the set of bits may be corrected by changing a value of the at least one bit.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: March 16, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Yingquan Wu, Eyal En Gad
  • Patent number: 10951237
    Abstract: A computer-implemented method according to one embodiment includes identifying a block size used by an application, where the block size is a power of two, constructing, utilizing a plurality of instances of a first array code, a single instance of a second array code having a symbol size that matches the block size used by the application, where the symbol size of the second array code is always a power of two, and implementing the second array code within the application.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventor: Henry E. Butterworth
  • Patent number: 10951238
    Abstract: A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller generates an error correction code including a first and second symbol groups. The first symbol group is a set of symbols shared between a first component code and a third component code and/or a fourth component code. The second symbol group is a set of symbols shared between a second component code and the third component code and/or the fourth component code. The first and third component codes have a lower correction capability than the second and fourth component codes, respectively. The ratio of symbols protected by the third component code is smaller in the second symbol group than in the first symbol group. The ratio of symbols protected by the fourth component code is larger in the second symbol group than in the first symbol group.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: March 16, 2021
    Assignee: Kioxia Corporation
    Inventor: Daiki Watanabe
  • Patent number: 10945010
    Abstract: Provided is a method for transmitting a broadcasting content and a line content, the broadcasting content and the line content being synchronously displayed, the method including: generating a line parity packet from a plurality of line data packets in each of which the line content is stored; transmitting the line data packet and the line parity packet through a communication line; and transmitting a plurality of broadcasting data packets in each of which the broadcasting content is stored, from a base station using a broadcasting wave, a transfer clock time of the broadcasting content being delayed by a predetermined time compared with a transfer clock time of the line content. At this point, video quality can be improved when the real-time broadcasting program content and the real-time line content are simultaneously displayed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: March 9, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yutaka Murakami, Tomohiro Kimura
  • Patent number: 10944505
    Abstract: A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 9, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Dong Wook Roh, Joon Kui Ahn, Nam Yul Yu, Jung Hyun Cho, Yu Jin Noh, Ki Jun Kim, Dae Won Lee
  • Patent number: 10938735
    Abstract: A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 2, 2021
    Assignee: PANASONIC CORPORATION
    Inventor: Peter Klenner
  • Patent number: 10917114
    Abstract: This application discloses a data transmission method, a sending device, a receiving device, and a communications system. The sending device is configured to send a first transport block. The sending device obtains a coded bit segment from a first encoded code block. The first encoded code block is obtained after LDPC encoding is performed on a first code block in the first transport block based on a processing capability of the receiving device. The sending device sends the coded bit segment to the receiving device. Because the processing capability of the receiving device is considered, storage overheads of the sending device or the receiving device can be reduced, encoding or decoding complexity can be reduced, and a decoding success rate can be improved.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: February 9, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Liang Ma, Chen Zheng, Jie Xiong, Xin Zeng, Xiaojian Liu, Yuejun Wei
  • Patent number: 10917118
    Abstract: According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. The controller generates a second error correcting code using data stored in the first volatile memory. The second error correcting code is a code for correcting data which cannot be corrected included in a first data group using a first error correcting code. The controller releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes in a codeword of the second error correcting code to the nonvolatile memory.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Erika Kaku, Yoshihisa Kojima
  • Patent number: 10917111
    Abstract: An error correction code (ECC) unit includes an error correction code (ECC) encoder configured to perform error correction code (ECC) encoding for each of a first data group and a second data group sharing at least one data with the first data group; and an error correction code (ECC) decoder configured to perform error correction code (ECC) decoding for each of the first data group and the second data group. The ECC decoder performs the ECC decoding for the second data group when the ECC decoding for the first data group fails, and does not perform the ECC decoding for the second data group when the ECC decoding for the first data group succeeds.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Nack Hyun Kim, Dong Wook Kim, Min Kyu Lee
  • Patent number: 10911062
    Abstract: A method includes receiving multiple bits to be transmitted. The method also includes applying a first binary alphabet polar code to a first subset of the multiple bits to generate first encoded bits. The first encoded bits are associated with a first bit level of a multilevel coding scheme. The method further includes generating one or more symbols using the first encoded bits and bits associated with a second bit level of the multilevel coding scheme. The first binary alphabet polar code is associated with a first coding rate. In addition, the method could include applying a second binary alphabet polar code to a second subset of the multiple bits to generate second encoded bits. The second encoded bits are associated with the second bit level. The second binary alphabet polar code is associated with a second coding rate such that the bit levels have substantially equal error rates.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 2, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Corina Ioana Ionita, Jun Chul Roh, Mohamed F. Mansour, Srinath Hosur
  • Patent number: 10892851
    Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 12, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Rong Li, Gongzheng Zhang, Ying Chen, Xiaocheng Liu, Jun Wang
  • Patent number: 10892783
    Abstract: The present disclosure relates to a method and an apparatus for decoding polar codes and the polar code decoding method according to an exemplary embodiment of the present disclosure is a polar code decoding method performed by a polar code decoding apparatus which includes receiving a code word vector generated by polar encoding; and decoding the code word vector based on a soft cancellation (SCAN) decoding method and a round-trip belief propagation (BP) decoding method, in the decoding, an inner code of the code word vector may be decoded by the round-trip belief propagation method and an outer code may be decoded by the SCAN decoding method.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 12, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jun Heo, Sung Hoon Lee
  • Patent number: 10891191
    Abstract: An example method for determining likelihood of erroneous data bits stored in memory cells may include sensing a first plurality of memory cells based on a first sense thresholds. Responsive to sensing the first plurality of cells, a first set of probabilistic information may be associated with the first plurality of memory cells. A second plurality of memory cells may be sensed based on a second sense threshold. Responsive to sensing the second plurality of memory cells, a second set of probabilistic information may be associated with the second plurality of memory cells. An error correction operation may be performed on the first and second pluralities of memory cells based, at least in part, on the first and second values.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • Patent number: 10891186
    Abstract: According to one embodiment, a semiconductor device includes an ECC decoder which performs diagnosis on data using an error detection code for the data, an ECC encoder which generates an error detection code for a first data piece equivalent to a bit range accounting for a part of plural bits configuring the data and generates an error detection code for a second data piece equivalent to a bit range accounting for a remaining part of the bits, and a diagnosis circuit which, when no error in the data has been detected by the ECC decoder, compares a part of the data corresponding to the first data piece with the first data piece used in generating the first error detection code and compares a part of the data corresponding to the second data piece with the second data piece used in generating the second error detection code.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: January 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toru Kawanishi, Tadashi Teranuma, Masaaki Hirano
  • Patent number: 10886950
    Abstract: Embodiments of the present application provide a method and an apparatus for generating a code word using a Polar code encoding manner. A sequence has N bits, in which K bits are information bits. A matrix of N rows×N columns is used for encoding the sequence. Each row of the matrix has a weight that equals to total number of non-zero elements in the row, and ith row of the matrix corresponds to ith bit position of the sequence, i=1, 2, . . . , N. Each bit position of the N-bit sequence has a reliability. The K bit positions of the sequence that are occupied by the K information bits are selected according to reliabilities of the bit positions of the sequence and weights of the rows of the matrix. The code word is generated by multiplying the sequence with the matrix.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: January 5, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bin Li, Hui Shen
  • Patent number: 10879938
    Abstract: An embodiment of a semiconductor apparatus may include technology to store a first portion of a code for a tile in a first die of the two or more nonvolatile memory die, store a second portion of the code for the tile in a second die of the two or more nonvolatile memory die, and perform an exclusive-or operation to correct a data error in the tile based on the stored first and second portions of the code. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventor: Ravi Motwani
  • Patent number: 10853892
    Abstract: A social networking relationships processing method includes: accessing a first forward-relationships set corresponding to a user identification of a first user in multiple data centers; obtaining an inverted-reverse-relationships set corresponding to the user identification of the first user; determining whether a difference between the first forward-relationships set of the first user and the inverted-reverse-relationship set corresponding to the user identification exists; in response to determining that the difference between the forward-relationships set and the inverted-reverse-relationships set exits, identifying a second user that causes the difference; respectively accessing first relationship information of the first user and second relationship information of the second user stored in associated data centers; and updating at least one of the first forward-relationships set of the first user or a second reverse-relationships set of the second user according to the relationship information of the fir
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 1, 2020
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Gang Liu
  • Patent number: 10847246
    Abstract: A memory system includes a memory medium and a memory controller. The memory medium includes data symbols and parity symbols which are respectively disposed at cross points of a plurality rows and a plurality of columns. The memory controller includes an error correction code (ECC) engine that is designed to execute an error correction operation at a fixed error correction level while the memory controller accesses the memory medium. The memory controller performs the error correction operation at the fixed error correction level using the ECC engine in a first error correction mode. The memory controller performs the error correction operation at an error correction level higher than the fixed error correction level using the ECC engine in a second error correction mode.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Wongyu Shin, Jung Hyun Kwon, Seunggyu Jeong, Do Sun Hong
  • Patent number: 10824507
    Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Kyu Lee, Jun Jin Kong, Ki Jun Lee, Sung Hye Cho, Dae Hyun Kim, Yong Gyu Chu
  • Patent number: 10819998
    Abstract: A method to be performed by a receiving apparatus for decoding an encoded bitstream representing a sequence of pictures of a video stream is provided. In the method, capabilities relating to level of decoding parallelism for the decoder are identified, a parameter indicative of the decoder's capabilities relating to level of decoding parallelism is kept, and for a set of levels of decoding parallelism, information relating to HEVC profile and HEVC level that the decoder is capable of decoding is kept. A method for encoding a bitstream representing a sequence of pictures of a video stream is also provided. In the method, a parameter is received from a transmitting apparatus that should decode the encoded bitstream.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 27, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Jonatan Samuelsson, Bo Burman, Rickard Sjöberg, Magnus Westerlund
  • Patent number: 10812112
    Abstract: The invention relates to a soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, the present invention provides a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.
    Type: Grant
    Filed: January 19, 2019
    Date of Patent: October 20, 2020
    Assignee: HYPERSTONE GMBH
    Inventors: Juergen Freudenberger, Jens Spinner, Christoph Baumhof
  • Patent number: 10805058
    Abstract: An optical network includes a transmitter portion configured to transmit a digitized stream of symbols over a digital optical link, a mapping unit disposed within the transmitter portion and configured to code the transmitted digitized stream of symbols with a mapping code prior to transmission over the digital optical link, a receiver portion configured to recover the coded stream of symbols from the digital optical link, and a demapping unit disposed within the receiver portion and configured to map the recovered coded stream of symbols into an uncoded digitized signal corresponding to the digitized stream of symbols at the transmitter portion prior to coding by the mapping unit.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 13, 2020
    Assignee: Cable Television Laboratories, Inc.
    Inventors: Zhensheng Jia, Luis Alberto Campos, Curtis Dean Knittle, Jing Wang
  • Patent number: 10797726
    Abstract: This invention discloses a network data prediction method, a network data processing device, and a network data processing method. The network data processing method is applied to a device that implements an open systems interconnection model (OSI model) and includes the following steps: generating a first data block and a second data block according to the OSI model; processing the first data block based on an error detection method to generate a first check code; encoding the first data block and the first check code to generate a first network data; transmitting the first network data; and receiving a second network data that includes a second check code; generating a target data according to a portion of the second data block and a portion of the second network data; and checking the target data according to the second check code.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: October 6, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chao-Yuan Hsu
  • Patent number: 10749549
    Abstract: A method and device in user equipment and a base station for wireless communication is disclosed. The base station equipment sequentially generates a first information block including bits in a first sub-information-block and a second sub-information-block, performs first channel coding and transmits a first radio signal. The first bit block includes bits in the first information block, the first bit block is used as an input of the first channel coding, the value of the first sub-information-block is related to the number of padding bits, and the relative position of the first sub-information-block and the second sub-information-block in the first information block is related to the number of bits included in the first information block. The present disclosure utilizes the characteristics of serial decoding of a Polar code, and improves the decoding performance using padding bits as frozen bits through the internal indication of the code block.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: August 18, 2020
    Assignee: SHANGHAI LANGBO COMMUNICATION TECHNOLOGY COMPANY LIMITED
    Inventors: Jin-Hui Chen, Xiaobo Zhang
  • Patent number: 10735140
    Abstract: There is provided mechanisms for encoding an information sequence into an encoded sequence. A method is performed by an information encoder. The method comprises obtaining the information sequence. The method comprises inserting at least one checkpoint sequence in the information sequence. The method comprises encoding the information sequence comprising the at least one checkpoint sequence into the encoded sequence using a polar code. There is also provided a method for decoding such an encoded sequence.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 4, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Mirsad Cirkic, Jonas Fröberg Olsson, Martin Hessler
  • Patent number: 10735138
    Abstract: A method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed. In an embodiment, a method for lifting a child code from a base code for encoding and decoding data includes determining a single combination of a circulant size, a lifting function, and a labelled base matrix PCM according to an information length and a code rate using data stored in a lifting table. The lifting table was defined at a code generation stage. The method also includes calculating a plurality of shifts for the child code. Each shift is calculated by applying the lifting function to the labelled base matrix PCM with a defined index using the circulant size and using the derived child PCM to encode or decode data.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 4, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Gleb Vyacheslavovich Kalachev, Ivan Leonidovich Mazurenko, Pavel Anatolyevich Panteleev, Elyar Eldarovich Gasanov, Aleksey Alexandrovich Letunovskiy, Wen Tong, Carmela Cozzo
  • Patent number: 10725841
    Abstract: An integrated circuit (IC) includes an encoder circuit configured to receive input data including a plurality of data bits. A plurality of parity computation equations for a single error correct double error detect adjacent double error correct adjacent triple error detect (SECDEDADECADTED) Hamming code is received. A plurality of parity bits are computed using the plurality of parity computation equations. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 28, 2020
    Assignee: XILINX, INC.
    Inventors: Kumar Rahul, Santosh Yachareni
  • Patent number: 10705743
    Abstract: A method for generating a security feature of a flash memory includes determining a memory block from a plurality of memory blocks in the flash memory; erasing data of the determined memory block of the flash memory; providing a predetermined voltage to the determined memory block to obtain a plurality of corresponding threshold voltages of a plurality of cells in the determined memory block, wherein each of the corresponding threshold voltages corresponds to a characteristic of each cell in the determined memory block; and establishing a security feature based on the plurality of corresponding threshold voltages.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 7, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Shih-Fu Huang, Cheng-Yu Chen, Yi-Lin Hsieh, Jing-Long Xiao
  • Patent number: 10700713
    Abstract: A method and system are provided for error correction. After row encoding and column encoding, additional codeword data (ACD) and modified parity (P?) may be concurrently created, for each of a plurality of modified column codewords (CCW?), by multiplying initial calculated parity P by a generator matrix G. Each CCW? may include an ACD portion and a P? portion such that each bit in the P? portion of a selected CCW? is present in the ACD portion for one of the other CCW?. In contrast to known approaches, the method and system may provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords, each bit in the modified parity in one modified codeword is present in another codeword.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 30, 2020
    Assignee: MICROSEMI STORAGE SOLUTIONS, INC.
    Inventors: Peter Graumann, Saeed Fouladi Fard
  • Patent number: 10686557
    Abstract: Methods and systems adapted for providing forward error correction for data packets containing a relationship between the data in each data packet. Data packets encoded in one error correction coding scheme are received and a second error correction coding scheme is identified based on the relationship between the data in each data packet. The data packets are then decoded using the second error correction coding scheme.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 16, 2020
    Assignee: L3 Technologies Inc.
    Inventors: Brian G. Yoho, Ryan W. Hinton, Richard Ross, Carl Christensen
  • Patent number: 10673466
    Abstract: This application provides a polar encoding and decoding method, a sending device, and a receiving device, to help overcome disadvantages in transmission of medium and small packets, a code rate, reliability, and complexity in the prior art.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 2, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ying Chen, Gongzheng Zhang, Yunfei Qiao, Rong Li, Huazi Zhang, Hejia Luo
  • Patent number: 10659082
    Abstract: There is provided a decoding device including a decoding determination unit that determines a procedure of recovering and decoding missing packets in consideration of a packet missing pattern in data including a set of media packets and redundant packets generated by a two-dimensional XOR-based forward error correction FEC encoding method, and a decoding unit that executes the recovery of the missing packets according to the procedure determined by the decoding determination unit.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: May 19, 2020
    Assignee: SONY CORPORATION
    Inventor: Vijitha Ranatunga
  • Patent number: 10656996
    Abstract: One embodiment provides a system that facilitates integrated security and high availability. During operation, the system obtains a number of data elements from a data stream based on a number of coded fragments that a code word includes. The system determines one or more bit-level operations for the data elements in such a way that at least one of the one or more bit-level operations becomes eliminated from a process of erasure encoding. The system then obfuscates the data elements based on one or more bit-level operations. Subsequently, the system generates a code word of the erasure encoding from the obfuscated data elements based on the generator matrix. The code word comprises a plurality of coded fragments.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 19, 2020
    Assignee: PhazrIO Inc.
    Inventors: Donald C. D. Chang, Chi-Kwan Jim Cheung, Lara Dolecek, Gary N. Jin, Rocky Chi-Ray Lin
  • Patent number: 10644726
    Abstract: A method for reconstructing a data block of size N is proposed. The data block was encoded using an erasure code to generate a set of Ns systematic symbol vectors and a set of Np parity projection vectors from a mapping of the data block onto a two-dimensional convex support. The method comprises: for each input vector that contains at least an erasure, updating the value of each erased symbol to a predetermined value; mapping the Ns input vectors with updated values onto the two-dimensional convex support, generating a reconstruction projection vector from the mapping of the Ns input vectors with updated values onto the two-dimensional convex support using an encoding projection direction; and generating an updated parity projection vector from the reconstruction projection vector and the parity projection vector generated using said encoding projection direction.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: May 5, 2020
    Assignees: Universite de Nantes, Centre National de la Recherce Scientifique—CNRS
    Inventors: Sylvain David, Pierre Evenou, Jean-Pierre Guedon, Nicolas Normand, Benoît Parrein
  • Patent number: 10637609
    Abstract: Embodiments of this application provide an information processing method and a coding apparatus. An information bit sequence includes a K-bit information block. The information bit sequence is to be processed into an encoded bit sequence with a target code length M, M>1024. For a given code rate R, when the length K of the information block is greater than a preset threshold, the information bit sequence is segmented into two or more segments. Each segment is polar encoded into an encoded subsequence. The encoded subsequence has a length that equals to a mother code length Ni, and i=1, 2, . . . , p. Each of the p encoded subsequences is rate matched to obtain a rate-matched encoded subsequence. A rate-matched encoded subsequence i of the p rate-matched encoded subsequences has a code length Mi. The p rate-matched encoded subsequences are concatenated into an encoded bit sequence which has a code length M.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: April 28, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chen Xu, Rong Li, Gongzheng Zhang, Yue Zhou, Lingchen Huang
  • Patent number: 10623136
    Abstract: Systems and methods for ACM trajectory include receiving data at a communications receiver; decoding the received data based on a selected MODCOD; monitoring a number of iterations used to decode the data using the selected MODCOD; comparing the number of iterations used to decode the data using the first selected MODCOD to a reference number of iterations; and adjusting a SNR threshold value for the selected MODCOD where the number of iterations used to decode the data using the first selected MODCOD is greater than the reference number of iterations.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 14, 2020
    Assignee: HUGHES NETWORK SYSTEMS, LLC
    Inventors: Bala Subramaniam, Yanlai Liu
  • Patent number: 10621041
    Abstract: Methods and apparatus to dynamically assign and relocate object fragments in distributed storage systems are disclosed. In some examples, the methods and apparatus encode an object with error correction coding to separate the object into fragments, create a first index indicative of storage nodes where the fragments of the object are to be stored, encode a second index into identifiers of the fragments of the object, the second index based on the first index, and store the fragments of the object and the corresponding second index encoded identifiers in the storage nodes based on the first index.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: Paul E. Luse, John Dickinson, Samuel Merritt, Clay Gerrard
  • Patent number: 10623019
    Abstract: A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung-Kyu Lee, Jae-Hong Kim, Ki-Jun Lee, Jun-Jin Kong, Hong-Rak Son, Se-Jin Lim, Young-Jun Hwang
  • Patent number: 10614853
    Abstract: A storage device includes a recording medium, a first memory storing first data read from the recording medium, and a controller. The controller searches for read target data in the first data by executing a parity check on second data that is in the first data and starts at a first position, while executing the parity check, determining whether or not an interruption condition is satisfied, storing the second data in a second memory when the parity check completes without the interruption condition being satisfied and a result of a completed parity check satisfies a first condition, and executing a parity check on third data that is in the first data and starts at a second position, responsive to the interruption condition being satisfied and responsive to the result of the completed parity check not satisfying the first condition.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: April 7, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Keiichi Kishino
  • Patent number: 10606699
    Abstract: A data storage device is disclosed wherein a first plurality of codewords are generated each comprising a plurality of symbols, and a first parity sector is generated over the first plurality of codewords. A second plurality of codewords are generated each comprising a plurality of symbols, and a second parity sector is generated over the second plurality of codewords. A third parity sector is generated over a first subset of the first plurality of codewords and a first subset of the second plurality of codewords, and a fourth parity sector is generated over a second subset of the first plurality of codewords and a second subset of the second plurality of codewords. When processing of a first codeword fails, the first codeword and the first parity sector are processed using a LDPC type decoder, and the first codeword and the third parity sector are processed using the LDPC type decoder.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 31, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Weldon M. Hanson, Niranjay Ravindran, David T. Flynn
  • Patent number: 10606697
    Abstract: A method and apparatus for improved data recovery in data storage systems is described. When errors occur while retrieving a plurality of codewords from a plurality of storage devices, a long vector may be formed from the plurality of codewords and decoded by a special, long parity check matrix to re-create data stored on the plurality of storage devices when normal decoding efforts fail.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 31, 2020
    Assignee: Goke US Research Laboratory
    Inventors: Chandra Varanasi, Engling Yeo
  • Patent number: 10594436
    Abstract: Embodiments of this application provide an information processing method and a coding apparatus. An information bit sequence includes a K-bit information block. The information bit sequence is to be processed into an encoded bit sequence with a target code length M, M>1024. For a given code rate R, when the length K of the information block is greater than a preset threshold, the information bit sequence is segmented into two or more segments. Each segment is polar encoded into an encoded subsequence. The encoded subsequence has a length that equals to a mother code length Ni, and i=1, 2, . . . , p. Each of the p encoded subsequences is rate matched to obtain a rate-matched encoded subsequence. A rate-matched encoded subsequence i of the p rate-matched encoded subsequences has a code length Mi. The p rate-matched encoded subsequences are concatenated into an encoded bit sequence which has a code length M.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 17, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chen Xu, Rong Li, Gongzheng Zhang, Yue Zhou, Lingchen Huang
  • Patent number: 10594435
    Abstract: Provided are a signaling coding and modulation method and a demodulation and decoding method and device, characterized in that the method comprises the steps of: extending signaling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; conducting parity bit permutation on a parity bit portion in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword; according to the length of the signaling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the tuple sequence, which is used for mapping, into a signaling symbol according
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 17, 2020
    Inventors: Wenjun Zhang, Yijun Shi, Dazhi He, Ge Huang, Hongliang Xu, Yao Wang