Double Encoding Codes (e.g., Product, Concatenated) Patents (Class 714/755)
  • Patent number: 11929829
    Abstract: A communication method is configured to increase speed of messages reception over a bandwidth limited channel such as high frequency (HF) radio. User data arriving from a high-speed network is transformed into a format suitable for transmission over the radio channel. Message packets that will take longer to reach a destination via the radio channel as compared to alternative channels, such as a fiber optic network, are rejected for radio transmission. When the packet is received, the receiver deduces message length by using information from various error handling techniques, such as forward error correction (FEC) and cyclic redundancy check (CRC) techniques. Fill data is transmitted between message packets when no data is available. The FEC and CRC information for the fill data is modified so that the fill data will fail FEC and CRC checks at the receiving station.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 12, 2024
    Assignee: Skywave Networks LLC
    Inventors: Kevin J. Babich, Terry Lee Vishloff, Danie J. van Wyk
  • Patent number: 11916669
    Abstract: Provided is a coding control method in a passive optical network (PON). The method includes acquiring data of a service to be coded and a preset codeword length N corresponding to the service to be coded; acquiring a coding mode corresponding to the preset codeword length N in a preset table describing a correspondence between codeword length ranges and coding modes; and coding data of the service by using the coding mode corresponding to the preset codeword length N. Further provided are a coding control apparatus in a PON, a communication device and a storage medium.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: February 27, 2024
    Assignee: ZTE CORPORATION
    Inventors: Zheng Liu, Liuming Lu, Yong Guo, Xingang Huang, Weiliang Zhang, Liquan Yuan
  • Patent number: 11916679
    Abstract: A bitstream modifier is operative on a packet which uses repetition coding. The bitstream modifier increases randomness of the data in a deterministic manner such that spectral spurs from repetition coding are greatly reduced, thereby providing greater available transmit power. In another example of the invention, baseband samples of a header and/or payload for a Bluetooth packet are modified by a canonical sequence with a low slew rate for data such that the variations in frequency may be tracked by a receiver and the transmitted spectral spurs reduced.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: February 27, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Sriram Mudulodu, Divyaxi Rudani, Manoj Medam, Partha Sarathy Murali, Ajay Mantha, Suchin Gupta
  • Patent number: 11894859
    Abstract: A team polar decoder (TPD) includes polar decoders (PPDs) connected to a channel, and a team decision maker (TDM) connected to the PPDs and a destination. Component polar decoders (CPDs) decode a polar code in accordance with a polar code. Each CPD receives a noisy code block (NCB) from the channel, and decodes the NCB in consecutive steps to obtain a decoded transform input block (DTIB). Each CPD is generates, at an end of the decoding step, a candidate decoded data block from the DTIB by a data-demapping operation that is an inverse of a data-mapping operation applied at a polar encoder, then sends the CDDB to the TDM, which receives the CDDBs from the PPDs, generates a decoded data block (DDB), and sends the DDB to the destination.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 6, 2024
    Assignee: Polaran Haberlesme Teknolojileri Anonim Sirketi
    Inventor: Erdal Arikan
  • Patent number: 11874734
    Abstract: A method for operating a memory includes: performing an error check operation on first memory cells; performing an error check operation on second memory cells; detecting an error which is equal to or greater than a threshold value in a region including the first memory cells and the second memory cells; classifying the region as a bad region in response to the detection of an error which is equal to or greater than the threshold value; and performing an error check operation on the first memory cells and the second memory cells again in response to the classification of the bad region.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: January 16, 2024
    Assignee: SK hynix Inc.
    Inventors: Dae Suk Kim, Eung Bo Shim
  • Patent number: 11876535
    Abstract: A memory controller, for use in a data storage device, is provided. A low-density parity-check (LDPC) decoding procedure performed by the memory controller includes an initial phase, a decoding phase, and an output phase in sequence. The memory controller includes a memory-index control circuit and a decoder. The decoder includes a decoding pipeline to perform the decoding phase of the LDPC decoding procedure. After the data storage device is booted up, the decoder reads a plurality of first codewords from a variable-node memory using a first order via the memory-index control circuit for LDPC decoding. In response to the decoder determining that a specific codeword among the first codewords has decoding failure, the decoder is reset to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding. The first order is different from the second order.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: January 16, 2024
    Assignee: SILICON MOTION, INC.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 11874900
    Abstract: Novel and useful system and methods of functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The NN processor incorporates functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 16, 2024
    Inventors: Guy Kaminitz, Ori Katz, Or Danon, Daniel Chibotero, Roi Seznayov, Nir Engelberg, Avi Baum, Itai Resh
  • Patent number: 11870573
    Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: January 9, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Rong Li, Gongzheng Zhang, Ying Chen, Xiaocheng Liu, Jun Wang
  • Patent number: 11868210
    Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first group of sets of parity data that each protect data stored in a row of memory cells of an array is generated. Further, a second group of sets of parity data that each protect data stored in a column of memory cells of an array is generated. The first set of parity data and the second set of parity data is sent to a host for further ECC processing. The host provides ECC data to the memory device based on the first set of parity data and the second set of parity data. The memory device repairs memory cells or retires memory cells based on the provided ECC data.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Bueb, Kishore K. Muchherla
  • Patent number: 11861195
    Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: January 2, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Liam Parker, Yuval Shohet, Michelle Martin
  • Patent number: 11863204
    Abstract: A decoder circuit includes first and second decoders. The first decoder is a first type of decoder configured to receive data encoded with an error correction code and decode and eliminate errors from a first subset of codewords of the data. The second decoder is a second type of decoder configured receive the data encoded with the error correction code and decode and eliminate errors from a second subset of codewords of the data, different from the first subset of the codewords, without attempting to decode and eliminate errors from the first subset of the codewords.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: January 2, 2024
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Mario A. Castrillon, Damián A. Morero, Genaro Bergero, Cristian Cavenio, Teodoro Goette, Martin Asinari, Ramiro R. Lopez, Mario R. Hueda
  • Patent number: 11863201
    Abstract: Methods, systems, and devices for wireless communications are described. A wireless communication system may support techniques for correlation-based hardware sequences for layered decoding. In some cases, a user equipment (UE) may partition layers of a submatrix associated with a parity check decoding procedure into a first set of layers and a second set of layers. The UE may sort each set of layers into a respective set of layer orders (e.g., a first set of layer orders and a second set of layer orders) based on an associated set of correlation values. The UE may combine the first set of layer orders and the second set of layer orders to obtain a set of combined layer orders and may select a decoding schedule from a set of decoding schedules used for decoding each of the combined layer orders based on respective schedule lengths for the set of decoding schedules.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: January 2, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Nian Guo, Yuksel Ozan Basciftci, Carsten Aagaard Pedersen, Murali Menon
  • Patent number: 11853591
    Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on a first sub-data to generate a second encoded data, and transmit a second data to a memory die in the writing phase; where the second data includes the first sub-data, a second sub-data, the first encoded data, and the second encoded data; the base die is further configured to: receive the second data from the memory die in a reading phase, perform first error checking and correction processing on the first sub-data and the second encoded data, and transmit a third data in the reading phase.
    Type: Grant
    Filed: May 1, 2022
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Patent number: 11847025
    Abstract: Providing for increased flexibility for large scale parity, the including: writing data to a storage system, including utilizing a first data protection scheme; identifying, for storage media in the storage system, characteristics of the storage media; identifying, in dependence up the characteristics for the storage media, a second data protection scheme to use for the data; and writing the data to the to the storage system utilizing the second data protection scheme.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: December 19, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Ethan Miller, Robert Lee, Par Botes, Ronald Karr
  • Patent number: 11831338
    Abstract: Communication terminals, systems and methods are disclosed herein. In an embodiment, a method for improving communication throughput when experiencing periodic blockages includes reading a plurality of data elements into an interleaver in one of a quasi-reverse order and a consecutive order, reading the plurality of data elements out of the interleaver in the other of the quasi-reverse order and the consecutive order, and. transmitting the plurality of data elements via a communication channel that experiences periodic blockages.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: November 28, 2023
    Assignee: HUGHES NETWORK SYSTEMS, LLC
    Inventors: Mustafa Eroz, Lin-nan Lee, Victor Liau, Glenn Robins
  • Patent number: 11829199
    Abstract: A timing generator as master clock for an electronic circuit includes a coarse code and a plurality of fine codes, has a ring oscillator with an uneven number n of delay elements, each of which has a delay output at which clock signal is present; clock dividers which are connected to the delay outputs and at whose output a clock divider output signal is output; start circuit for generating initialization signal to trigger clock dividers, and clock generator that further processes clock signal and generates a coarse code, and an output at which generated timestamp is output, wherein the fine codes of timestamp are formed from clock divider output signals of the clock dividers, and the coarse code and the fine codes contain redundant information that a time shift of the fine codes relative to the coarse code by at most (n?1)/2 time differences results in a correct timestamp.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: November 28, 2023
    Assignee: ELMOS SEMICONDUCTOR SE
    Inventors: André Srowig, Fabian Finkeldey
  • Patent number: 11811422
    Abstract: Provided is an information processing method. The method includes that: first data to be decoded and one or more decoding parameters of the first data are obtained; a basis matrix is determined based on the one or more decoding parameters; a decoding instruction set including a plurality of decoding instructions is determined based on the basis matrix, wherein the plurality of decoding instructions include elements in the basis matrix; and the first data is decoded based on the decoding instruction set. Further provided are an information processing device and a computer storage medium.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 7, 2023
    Assignee: SANECHIPS TECHNOLOGY CO., LTD.
    Inventor: Huayong Wang
  • Patent number: 11797386
    Abstract: A system, method, and product for flexible RAID layouts in a storage system, including: determining a reliability of an individual storage device of a plurality of storage devices, the individual storage device containing a plurality of portions of a Redundant Array of Independent Disks (RAID) stripe in a storage system, wherein the RAID stripe includes user data and inter-device parity data; detecting a change in the reliability of the individual storage device that contains the portion corresponding to the RAID stripe; and changing an amount of intra-device protection corresponding to the RAID stripe by decreasing, in the RAID stripe, an amount of space used to store the inter-device protection data.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: October 24, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: John Colgrove, John Hayes, Bo Hong, Ethan Miller
  • Patent number: 11799499
    Abstract: Methods, apparatus, systems, architectures and interfaces for encoding/decoding a QD-DTS-PrCC are provided. The decoding method includes determining a number kTS of input bits included in a transmission of a data stream and a first bit of the input bits included in the transmission in the data stream; determining a number of Encoded Bit Blocks (EBBs), each of the EBBs including any number of data blocks that are previously transmitted Transmit Segments (TS) of the data stream, each of the data blocks having a bit length of kTS bits; selecting that number of EBBs for encoding a QD-DTS-PrCC component codeword (QDCC) of the transmission according to a DTS indexing method for indexing a plurality of EBBs; generating the QDCC including a TS, Virtual Segments (VSs), and rc parity bits, a dimensionality of the QD-DTS-PrCC being at least 2; and extracting the calculated TS of the QDCC to an output EBB.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 24, 2023
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Oleksandr Evald Geyer, Onur Sahin
  • Patent number: 11799498
    Abstract: A data processing method and apparatus. The data process method includes: determining, by a transmitting node, a code block length N0 for encoding an information bit sequence to be transmitted according to a data characteristic for representing the information bit sequence to be transmitted and a preset parameter corresponding to the data characteristic; performing, by the transmitting node, polar encoding on the information bit sequence to be transmitted according to the code block length N0; and transmitting, by the transmitting node, a code block obtained through the polar encoding to a receiving node.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: October 24, 2023
    Assignee: ZTE CORPORATION
    Inventors: Saijin Xie, Jun Xu, Jin Xu, Mengzhu Chen
  • Patent number: 11789811
    Abstract: Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: October 17, 2023
    Assignee: NVIDIA Corporation
    Inventors: Peter Mills, Michael Sullivan, Nirmal Saxena, John Brooks
  • Patent number: 11791935
    Abstract: A disclosure of the present specification provides a method for transmitting data by a transmitter. The method may comprise the steps of: when a transport block (TB) is divided into n data blocks, adding additional information after each of the n data blocks; and adding a cyclic redundancy check (CRC) after the last additional information. Here, the CRC may be generated on the basis of the n data blocks, and the n pieces of additional information added after each of data blocks.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: October 17, 2023
    Assignee: LG Electronics Inc.
    Inventors: Seunggye Hwang, Kijun Kim, Soocheol Kyeong, Bonghoe Kim, Jinwoo Kim, Kwangseok Noh, Jongwoong Shin, Joonkui Ahn, Hyangsun You
  • Patent number: 11785596
    Abstract: A transmission method for uplink control information (UCI) is provided. The method includes the following. The method includes obtaining target UCI, and multiplexing the target UCI to a configured grant (CG)-physical uplink shared channel (PUSCH) for transmission. The target UCI includes at least two types of UCI, the target UCI includes CG-UCI and first UCI, and the first UCI includes hybrid automatic repeat-request acknowledgement (HARQ-ACK), where the CG-UCI and the HARQ-ACK are encoded using joint encoding and subject to rate matching to obtain a first bit sequence. Multiplexing the target UCI to a CG-PUSCH for transmission includes multiplexing the first bit sequence to the CG-PUSCH from a first data symbol after a first demodulation reference signal (DMRS) symbol of the CG-PUSCH.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: October 10, 2023
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Zuomin Wu
  • Patent number: 11784665
    Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: October 10, 2023
    Assignee: Kioxia Corporation
    Inventors: Yasuyuki Imaizumi, Satoshi Shoji, Mitsunori Tadokoro, Takashi Ishiguro, Yifan Tang
  • Patent number: 11777521
    Abstract: This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z?K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: October 3, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chen Zheng, Liang Ma, Xiaojian Liu, Yuejun Wei, Xin Zeng
  • Patent number: 11770289
    Abstract: A communication device that generates a modulated signal with 32 QAM includes a modulator, a first encoder and a second encoder. The modulator generates a modulated signal by mapping each symbol in a data frame that includes transmission data, a first code, and a second code to a signal point among 32 QAM signal points. The first encoder encodes the data by using a first coding scheme to generate the first code. The second encoder encodes, by using a second coding scheme, a bit string formed from one specified bit in five bits allocated to each symbol in the data frame to generate the second code. The modulator performs mapping such that each pair of signal points adjacent to each other are arranged are different from each other in terms of a value of the one specified bit among the five bits.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 26, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Konno, Junichi Sugiyama, Yohei Koganei
  • Patent number: 11770134
    Abstract: Certain aspects of the present disclosure generally relate to techniques for encoding and decoding bits of information using cyclic redundancy check (CRC) concatenated polar encoding and decoding. A method generally includes obtaining the bits of information to be transmitted. The method includes performing CRC outer encoding of the bits of information using an even-weighted generator polynomial to produce CRC encoded bits. The method includes performing polar inner encoding of the CRC encoded bits to generate a codeword. The method includes discarding a first code bit at a beginning of the codeword. The shortened codeword is transmitted over a wireless medium. In another method, bit-level scrambling is performed on the CRC encoded bits before the polar encoding to. In another method, only odd-weighted generator polynomials are selected.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: September 26, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Kai Chen, Liangming Wu, Changlong Xu, Jing Jiang, Hao Xu
  • Patent number: 11764810
    Abstract: A decoding system, a decoding controller, and a decoding control method are provided. In the decoding system, a decoding controller is disposed between two adjacent decoders. The decoding controller determines whether to perform turn-off based on a non-turn-off indication received by a previous-stage decoder, a turn-off indication output by the previous-stage decoder, and historical turn-off probability statistics. This is equivalent to adding a buffer zone between the two adjacent decoders.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: September 19, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Qing Lu, Hong Chen, Jun Chen
  • Patent number: 11764813
    Abstract: Example channel circuits, data storage devices, and methods for using an extendable parity code matrix are described. A data unit may be read from a storage medium. Multiple sets of parity bits may be available for the data unit, each set of parity bits having a different number of parity bits corresponding to different parity matrices, including a primary parity matrix and at least one extended parity matrix. The extended parity matrix includes the primary parity matrix and additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data unit based on the data unit from the read signal.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: September 19, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Derrick Burton, Weldon M. Hanson, Richard Galbraith, Niranjay Ravindran
  • Patent number: 11764902
    Abstract: Various example embodiments for supporting forward error correction (FEC) in a communication system are presented. Various example embodiments for supporting FEC in a communication system may include the selection of a FEC setting for a communication channel from a transmitter to a receiver, e.g., the selection of a FEC setting for a communication channel, the selection of a FEC setting for a data burst sent over a communication channel, the selection of a FEC setting for a portion of a data burst sent over a communication channel, switching between FEC settings for different portions of a data burst over a communication channel, or the like, as well as various combinations thereof.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: September 19, 2023
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Yannick Lefevre, Adriaan de Lind van Wijngaarden, Jochen Maes, Vincent Houtsma, Doutje Van Veen, Amitkumar Mahadevan, Michaël Fivez
  • Patent number: 11757569
    Abstract: One coding method of a plurality of coding methods including at least a first coding method and a second coding method is selected, an information sequence is encoded by using the selected coding method, and an encoded sequence obtained by performing predetermined processing on the information sequence is modulated and transmitted. The first coding method is a coding method having a first coding rate, for generating a first encoded sequence by performing puncturing processing on a generated first codeword by using a first parity check matrix. The second coding method is a coding method having a second coding rate, for generating a second encoded sequence by performing puncturing processing on a generated second codeword by using a second parity check matrix that is different from the first parity check matrix, the second coding rate after the puncturing process being different from the first coding rate.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: September 12, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
  • Patent number: 11747985
    Abstract: A memory includes: a memory core; an error correction circuit suitable for correcting, when a number of one or more errors detected in data read from the memory core is equal to or greater than a threshold value, the detected errors based on an error correction code read from the memory core to produce an error-corrected data; and a data transferring circuit suitable for: outputting, when the detected errors are corrected, the error-corrected data according to a long read latency, and outputting, when the number of the detected errors is less than the threshold value or no error is detected in the read data, the read data according to a short read latency.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: September 5, 2023
    Assignee: SK hynix Inc.
    Inventors: Munseon Jang, Hoiju Chung
  • Patent number: 11750219
    Abstract: This application discloses example decoding methods, example decoders, and example decoding apparatuses. One example decoding method includes performing soft decision decoding on a first sub-codeword in a plurality of sub-codewords to obtain a hard decision result. It is determined whether to skip a decoding iteration. In response to determining not to skip the decoding iteration, a first turn-off identifier corresponding to the first sub-codeword is set to a first value based on the hard decision result. The first turn-off identifier indicates whether to perform soft decision decoding on the first sub-codeword in a next decoding iteration. The soft decision decoding is not performed on the first sub-codeword in the next decoding iteration when a value indicated by the first turn-off identifier is the first value. The hard decision result is stored.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: September 5, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mo Li, Dori Gidron, Michael Zarubinsky, Dudi Levy
  • Patent number: 11740965
    Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: August 29, 2023
    Assignee: Kioxia Corporation
    Inventors: Shunichi Igahara, Yoshihisa Kojima, Takehiko Amaki, Suguru Nishikawa
  • Patent number: 11734114
    Abstract: A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: August 22, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ross V. La Fetra
  • Patent number: 11726866
    Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Joseph Thomas Pawlowski
  • Patent number: 11728828
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: August 15, 2023
    Assignee: The Texas A&M University System
    Inventors: Kiran Kumar Gunnam, Gwan S. Choi
  • Patent number: 11728830
    Abstract: Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: August 15, 2023
    Assignee: ZTE CORPORATION
    Inventors: Liguang Li, Jun Xu, Jin Xu
  • Patent number: 11720879
    Abstract: A method and system for transferring encrypted data from a first electronic device to a second electronic device. The method includes the steps of displaying a first encrypted two-dimensional code at the output interface of the first electronic device, reading the first encrypted two-dimensional code with the input interface of the second electronic device, and decrypting the first two-dimensional code with the second electronic device, generating a second encrypted two-dimensional code with the second electronic device, and displaying the second encrypted two-dimensional code on the output interface of the second electronic device, reading the second two-dimensional code encrypted with the input interface of the first electronic device and decrypting the second two-dimensional code with the first electronic device and generating an action on the first electronic device based on the second decrypted two-dimensional code. The second two-dimensional code is a plurality of two-dimensional codes.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: August 8, 2023
    Assignee: MYCASHLESS SAPI DE CV
    Inventors: Enrico Becerra Morales, Yong De Piao
  • Patent number: 11722243
    Abstract: Provided are a signaling coding and modulation method and a demodulation and decoding method and device, characterized in that the method comprises the steps of: extending signaling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; conducting parity bit permutation on a parity bit portion in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword; according to the length of the signaling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the tuple sequence.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: August 8, 2023
    Assignee: Shanghai National Engineering Research Center of Digital Television Co., Ltd.
    Inventors: Wenjun Zhang, Yijun Shi, Dazhi He, Ge Huang, Hongliang Xu, Yao Wang
  • Patent number: 11722152
    Abstract: A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: August 8, 2023
    Assignee: Astera Labs, Inc.
    Inventors: Enrique Musoll, Anh T. Tran, Subbarao Arumilli, Chi Feng
  • Patent number: 11716096
    Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Stephen D. Hanna
  • Patent number: 11714711
    Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11714716
    Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a current value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 1, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Pi-Feng Chiu, Dejan Vucinic
  • Patent number: 11716237
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a mobile station may obtain a multi-level coding (MLC) configuration to be applied to a quadrature amplitude modulation (QAM) constellation set comprising a plurality of constellation symbols and having a non-linearity that is based at least in part on a phase noise or a power amplification associated with the plurality of constellation symbols. The mobile station may process the QAM constellation set, using MLC set partitioning in accordance with the MLC configuration, based at least in part on the phase noise or the power amplification associated with the plurality of constellation symbols of the QAM constellation set. Numerous other aspects are described.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: August 1, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Shay Landis, Idan Michael Horn, Yehonatan Dallal
  • Patent number: 11711101
    Abstract: A communication device that applies an error in an upper layer in addition to error correction in a physical layer is provided. The communication device includes an acquisition unit that acquires control information regarding forward error correction (FEC) of an upper layer and control information regarding FEC of a lower layer, an encoding-decoding unit that performs error correction encoding or decoding of an information sequence in the upper layer according to control information regarding the FEC of the upper layer, and a puncturing processing unit that performs puncturing or depuncturing in the upper layer. The information sequence after FEC encoding of the upper layer is divided into blocks, and puncturing and interleaving are performed in units of blocks.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: July 25, 2023
    Assignee: SONY GROUP CORPORATION
    Inventor: Ryota Kimura
  • Patent number: 11700081
    Abstract: Methods, systems, and devices for wireless communications are described. A first device may receive one or more signals from a second device. The first device may estimate one or more metrics associated with noise of the one or more signals. The first device may transmit, to the second device and based on the estimating, a report indicating the one or more metrics. The first device may receive a message indicating a multi-level coding scheme from the second device. The multi-level coding scheme may be based on the one or more metrics and may indicate a partitioning configuration of the multi-level coding scheme for communications between the first device and the second device. The first device may communicate with the second device using the partitioning configuration of the multi-level coding scheme.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: July 11, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yaniv Eistein, Ronen Shaked
  • Patent number: 11695505
    Abstract: Methods, systems, and devices for wireless communications are described. An encoder of a wireless device may receive a transport block (TB) for transmission and segment the transport block into a set of multiple, smaller data segments that respectively correspond to a plurality of code blocks of the TB. The encoder may generate a code block level (CB-level) error detection code (EDC) for a subset of the data segments. The encoder may generate a transport block-level (TB-level) EDC for the TB using the data segments. Each of the code blocks (CBs) may be of the same size and may include one of the data segments. A subset of the CBs may include a data segment from the subset of the data segments and one of the CB-level EDCs. The remaining CBs that are not part of the subset may include a remaining data segments and the TB-level EDC.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: July 4, 2023
    Assignee: Qualcomm Incorporated
    Inventors: Changlong Xu, Liangming Wu, Jian Li, Kai Chen, Jing Jiang, Gabi Sarkis, Hao Xu
  • Patent number: 11687408
    Abstract: Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller and a memory component operably coupled to the controller. The controller can include a memory manager, a quality metrics first in first out (FIFO) circuit, and an error correction code (ECC) decoder. In some embodiments, the ECC decoder can generate quality metrics relating to one or more codewords saved in the memory component and read into the controller. In these and other embodiments, the ECC decoder can stream the quality metrics to the quality metrics FIFO circuit, and the quality metrics FIFO circuit can stream the quality metrics to the memory manager. In some embodiments, the memory manager can save all or a subset of the quality metrics in the memory component and/or can use the quality metrics in post-processing, such as in error avoidance operations of the memory device.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Gerald L. Cadloni
  • Patent number: 11689220
    Abstract: Embodiments of this application provide a method for processing information bits in a wireless communication network. A device obtains a Polar encoded bit sequence, then divide the Polar encoded bit sequence into g groups that are of equal length N/g, wherein g is 32. The device block interleaves the g groups to obtain an interleaved bit sequence according to a sequence S, wherein the sequence S comprises: group numbers of the g groups, wherein a group whose number is 0 is the first element in the sequence S, wherein a group whose number is 12 is the 17th element in the sequence S, wherein a group whose number is 31 is the 32nd element in the sequence S, wherein the S is an integer and output the interleaved bit sequence.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: June 27, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Gongzheng Zhang, Ying Chen, Yunfei Qiao, Yourui Huangfu, Rong Li