Abstract: A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device. A method for network recording is disclosed.

Abstract: Methods, systems, and devices for generating preamble sequences where several Zadoff-Chu (ZC) sequences are generated based on multiple roots and multiple cyclic shifts per root and combined to generate the preamble sequences. Some embodiments may be used in wireless communication embodiments in which large propagation delays and/or Doppler movement are expected.

Abstract: A storage device is disclosed. The storage device may include storage for data. A controller may manage writing the data to the storage and reading the data from the storage. A data quality metric table may map a first number of errors to a first data quality metric and map a second number of errors to a second data quality metric. A transmitter may return the data quality metric table to a host.

Abstract: A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.

Abstract: Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.

Abstract: A method for data access control among multiple nodes and a data access system are provided. The data access system includes a data interconnect controller circuit that allocates resources of one or more slaves by one or more masters according to operating parameters of an interleaver, and includes an intelligent control module that collects use efficiency data of the one or more slaves and obtains a current setting of the data interconnect controller circuit via a monitor. The monitor calculates scores of use efficiency data. The scores and the setting are inputted to a neural network model. Parameters of the neural network model are adjusted according to the scores, and a new setting generated by the neural network model is applied to the interleaver of the data interconnect controller circuit, so that the data interconnect controller circuit performs access control among the multiple nodes with the new setting.

Abstract: According to one or more embodiments, a network node for communicating with at least one radio unit is provided. The network node including processing circuitry configured to: determine at least one code frame characteristic of a non-linear grid, map in-phase and quadrature, I/Q, data to non-linear grid having a plurality of regions that correspond to a plurality of code words where a plurality of bit sizes of the plurality of code words is a function of a radial distance from an origin of the non-linear grid, select a subset of the plurality of code words based at least in part on a target data rate for transmission, and cause transmission of the I/Q data based at least in part on the selected subset of the plurality of code words.

Abstract: Mirrored pairs in a RAID-1 are distributed in a balanced and deterministic way that increases data access parallelism. For a group of k+1 disks that can be represented as a matrix of disk rows indexed 0 through k, where each disk is organized into k same-size subdivisions, in columns indexed 1 through k, corresponding mirrors of data members on the first disk (row index 0) are distributed across all other disks along a matrix diagonal such that the row index is the same as the column index for each mirror. Additional mirror pairs are created and symmetrically distributed in two submatrix triangles that are defined and separated by the diagonal. The two triangles are populated with symmetrically distributed mirrors that are flipped around the matrix diagonal such that for any mirror data in one triangle, its corresponding mirror data can be found in the other triangle by swapping the row and column indices.

Abstract: Disclosed are a partitioning method, an encoder, a decoder and a computer storage medium. The method includes: determining location information of a point of a point cloud to be partitioned; when i is less than or equal to M?1, determining right-shift number Ni of ith LOD layer in the point cloud, M representing a preset maximum quantity of layers for LOD partitioning; for the ith LOD layer, shifting location information of the point rightwards by Ni-digit, performing storing in a preset storage area based on right-shifted location information; determining location information of a parent point corresponding to a current point in the ith LOD layer; according to determined location information of the parent point, searching the preset storage area for a neighbor point of the parent point; partitioning the current point into an (i+1)th LOD layer, or the neighbor point into the ith LOD layer.

Abstract: A data storage device in accordance with an embodiment may include a controller and a memory device. The controller is configured to output a read control signal including an option number related to a read condition. The memory device is configured to perform a read operation based on a read condition corresponding to the option number in response to the read control signal. The read condition for the option number is configured to be stored in a read condition table storage circuit included in the memory device.

Abstract: Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.

Abstract: An apparatus having memory cells, an error correction module with a predetermined code rate, a processing device configured to arrange data storage in the memory cells for improved capability in recovering from random bit errors in raw data retrieved from the memory cells. For example, user data and redundant data are stored in the memory cells. The redundant data is generated according to the predetermined code rate from not only the user data but also known data. The known data is not stored in the memory cells. As a result, the error correction module has increased capability in recovering from random bit errors in raw data retrieved from the memory cells. The increased capability can be used to extend the useful life of the memory cells and/or improve the reliability of retrieving error free data from the memory cells.

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction

Abstract: A deployment of radiologic beacons detect radiation levels for emitted radiation around a particular geographic area such as a town, city or campus environment. In a deployment of beacons for detecting and gathering radiological gamma-ray spectral data, each beacon periodically generates a set of values indicative of radiation at a particular energy level, and assembles a vector of the set of values ordered according to increasing energy levels. Each of the beacons transmits the vector as a stream or periodic sequence of data to a common aggregation location. Each beacon encodes the data according to a compression mechanism based on a Poisson distribution of the spectral data. A running average of the values for each energy level is maintained for the sequence of vectors, and encoding/decoding mechanisms are selected based on the average value to be encoded.

Abstract: a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.

Abstract: A system, method, and product for flexible RAID layouts in a storage system, including: determining a reliability of an individual storage device of a plurality of storage devices, the individual storage device containing a plurality of portions of a Redundant Array of Independent Disks (RAID) stripe in a storage system, wherein the RAID stripe includes user data and inter-device parity data; detecting a change in the reliability of the individual storage device that contains the portion corresponding to the RAID stripe; and changing an amount of intra-device protection corresponding to the RAID stripe by decreasing, in the RAID stripe, an amount of space used to store the inter-device protection data.

Abstract: In some examples, a computer system may receive a plurality of chunks of data of a data object. The system may compress the plurality of chunks of data to obtain a plurality of compressed chunks, and may determine whether the plurality of compressed chunks together are less than a threshold size. Based on determining that the plurality of compressed chunks together are less than the threshold size, the system may add, to respective entries in a map data structure, respective sizes of the plurality of compressed chunks. In addition, the system may compact the map data structure by combining values in at least two of the respective entries, and may store the plurality of compressed chunks and the compacted map data structure.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a network entity may transmit, to a user equipment (UE), an indication of a multi-level coding scheme that specifies a first encoding algorithm associated with level 1 coding and a second encoding algorithm associated with level 2 coding based at least in part on power management. The network entity may communicate with the UE based at least in part on the multi-level coding scheme. Numerous other aspects are described.

Abstract: Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.

Abstract: A method and apparatus for transmitting a streaming media with Forward Error Correction (FEC). Upon receiving the streaming media, the technique includes: encoding, segmenting and packeting frames comprised therein to generate a packetized elementary stream of media packets with variable sizes; for each L sequential media packets, calculating a “random loss” (RL) FEC parity and generating a respective RL FEC packet associated therewith; calculating “burst loss” (BL) FEC parities in accordance with a predefined FEC scheme and generating respective BL FEC structures bearing FEC headers and usable for generating BL FEC packets; calculating size-related parameters of a group of sequential media packets, the group being selected in accordance with the FEC scheme; and, transmitting the packetized elementary stream with interleaved FEC packets. The BL FEC packets are transmitted merely when the calculated size-related parameters meet a size-related burst loss (SRB) criterion defined by the FEC scheme.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.

Abstract: An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.

Abstract: Disclosed is an electronic device, which includes an ECC decoder that performs ECC decoding on a flit including a plurality of PAM-4 symbols for each of a plurality of ECC groups, a CRC decoder that performs CRC decoding on the ECC decoded flit to obtain data, and an erasure decoding unit that calculates an LLR for each of the PAM-4 symbols when the CRC decoding fails, extracts an error symbol candidate from among the plurality of PAM-4 symbols for each of the plurality of ECC groups based on the LLR, and performs the ECC decoding again after erasing the error symbol candidate.

Abstract: In the present invention, there is provided a data integration method executed by a data integration system that corrects inconsistency in type or quality between first data and second data stored in a data lake. The method includes a feature value calculation step of calculating feature values of the first data and the second data, an inconsistency detection step of detecting the inconsistency between the first data and the second data based on the feature values, and a data adjustment step of correcting the inconsistency by using an integrated view according to a request to acquire the first data and the second data from a user.

Abstract: Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.

Abstract: Methods, systems, and devices for wireless communications are described. In some examples, a transmitting device may generate a parity check matrix based on performing a lifting operation on a base matrix. Each column of the base matrix may correspond to a different variable node and each row may correspond to a different check node. The transmitting device may then generate a set of coded bits based on the parity check matrix and each coded bit of the set of coded bits may be associated with a respective variable node. Further, the transmitting device may interleave the set of coded bits such that subsets of the set of coded bits associated with a same variable node are mapped to a same channel reliability level and transmit the set of coded bits according to the interleaving.

Abstract: Systems, apparatuses, and methods related to memory bank protection are described. A quantity of errors within a single memory bank is determined and the determined quantity is used to further determine whether to access other memory banks to correct the determined quantity. The memory bank protection described herein avoids a single memory bank of a memory die being a single point of failure (SPOF).

Abstract: Disclosed are a decoding method and a decoding device. The decoding method includes: performing a permutation processing on a receiving sequence and a generator matrix to obtain a permuted receiving sequence and an intermediate generator matrix according to a reliability of each bit of the receiving sequence; performing a Gaussian elimination processing on the intermediate generator matrix to obtain a systematic generator matrix generator matrix; performing a hard-decision decoding on the permuted receiving sequence to obtain a hard-decision decoding sequence; in response to determining a preset decoding end condition is not achieved, selecting a target error pattern from an error pattern set; and generating a decoding result based on the target error pattern, the hard-decision decoding sequence, and the systematic generator matrix. The decoding method can ensure the decoding performance and reduce the decoding complexity.

Abstract: Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.

Abstract: Methods, systems, and devices for wireless communications are described. In some examples, a transmitting device may generate a parity check matrix based on performing a lifting operation on a base matrix. Each column of the base matrix may correspond to a different variable node and each row may correspond to a different check node. The transmitting device may then generate a set of coded bits based on the parity check matrix and each coded bit of the set of coded bits may be associated with a respective variable node. Further, the transmitting device may interleave the set of coded bits such that subsets of the set of coded bits associated with a same variable node are mapped to a same channel reliability level and transmit the set of coded bits according to the interleaving.

Abstract: An FEC coder in a transmission device according to an exemplary embodiment of the present disclosure performs BCH coding and LDPC coding based on whether a code length of the LDPC coding is a 16 k mode or a 64 k mode. A mapper performs mapping in an I-Q coordinate to perform conversion into an FEC block, and outputs pieces of mapping data (cells). The mapper defines different non-uniform mapping patterns with respect to different code lengths even an identical coding rate is used by the FEC coder. This configuration improves a shaping gain for different error correction code lengths in a transmission technology in which modulation of the non-uniform mapping pattern is used.

Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

Abstract: Mechanisms are provided to receive encoded header information stored on a tape of a tape drive, wherein the encoded header information has been generated by: generating, for a plurality of tracks of the tape of the tape drive, a header information in a plurality of symbols, wherein the plurality of symbols is comprised of a first set of symbols and a second set of symbols, wherein the first set of symbols include identical information across all tracks of the plurality of tracks, and wherein the second set of symbols are configurable to include different information across all tracks of the plurality of tracks; and modifying, for writing to the tape of the tape drive, the first set of symbols of the plurality of tracks to include parity information corresponding to information included in the second set of symbols of the plurality of tracks. The received encoded header information is decoded.

Abstract: A modified version of the min-sum algorithm (“MSA”) which can lower the error floor performance of quantized LDPC decoders. A threshold attenuated min-sum algorithm (“TAMSA”) and/or threshold offset min-sum algorithm (“TOMSA”), which selectively attenuates or offsets a check node log-likelihood ratio (“LLR”) if the check node receives any variable node LLR with magnitude below a predetermined threshold, while allowing a check node LLR to reach the maximum quantizer level if all the variable node LLRs received by the check node have magnitude greater than the threshold. Embodiments of the present invention can provide desirable results even without knowledge of the location, type, or multiplicity of such objects and can be implemented with only a minor modification to existing decoder hardware.

Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

Abstract: Various illustrative aspects are directed to a data storage device, comprising: one or more disks; a write mechanism configured to write data to disk surfaces of the one or more disks; and one or more processing devices, which are configured to: encode, based on a distributed sector encoding scheme, data into a plurality of logic blocks of data, wherein the logic blocks of data comprise the data to be written being interleaved across a plurality of sectors; assign at least some of the logic blocks to a plurality of containers of two or more container sizes, the container sizes comprising a relatively larger container size and a relatively smaller container size; and output a write signal to the write mechanism to write the logic blocks in accordance with the assigning of the at least some of the logic blocks to the plurality of containers.

Abstract: A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

Abstract: A communication method is configured to increase speed of messages reception over a bandwidth limited channel such as high frequency (HF) radio. User data arriving from a high-speed network is transformed into a format suitable for transmission over the radio channel. Message packets that will take longer to reach a destination via the radio channel as compared to alternative channels, such as a fiber optic network, are rejected for radio transmission. When the packet is received, the receiver deduces message length by using information from various error handling techniques, such as forward error correction (FEC) and cyclic redundancy check (CRC) techniques. Fill data is transmitted between message packets when no data is available. The FEC and CRC information for the fill data is modified so that the fill data will fail FEC and CRC checks at the receiving station.

Abstract: A bitstream modifier is operative on a packet which uses repetition coding. The bitstream modifier increases randomness of the data in a deterministic manner such that spectral spurs from repetition coding are greatly reduced, thereby providing greater available transmit power. In another example of the invention, baseband samples of a header and/or payload for a Bluetooth packet are modified by a canonical sequence with a low slew rate for data such that the variations in frequency may be tracked by a receiver and the transmitted spectral spurs reduced.

Abstract: Provided is a coding control method in a passive optical network (PON). The method includes acquiring data of a service to be coded and a preset codeword length N corresponding to the service to be coded; acquiring a coding mode corresponding to the preset codeword length N in a preset table describing a correspondence between codeword length ranges and coding modes; and coding data of the service by using the coding mode corresponding to the preset codeword length N. Further provided are a coding control apparatus in a PON, a communication device and a storage medium.

Abstract: A team polar decoder (TPD) includes polar decoders (PPDs) connected to a channel, and a team decision maker (TDM) connected to the PPDs and a destination. Component polar decoders (CPDs) decode a polar code in accordance with a polar code. Each CPD receives a noisy code block (NCB) from the channel, and decodes the NCB in consecutive steps to obtain a decoded transform input block (DTIB). Each CPD is generates, at an end of the decoding step, a candidate decoded data block from the DTIB by a data-demapping operation that is an inverse of a data-mapping operation applied at a polar encoder, then sends the CDDB to the TDM, which receives the CDDBs from the PPDs, generates a decoded data block (DDB), and sends the DDB to the destination.

Abstract: A memory controller, for use in a data storage device, is provided. A low-density parity-check (LDPC) decoding procedure performed by the memory controller includes an initial phase, a decoding phase, and an output phase in sequence. The memory controller includes a memory-index control circuit and a decoder. The decoder includes a decoding pipeline to perform the decoding phase of the LDPC decoding procedure. After the data storage device is booted up, the decoder reads a plurality of first codewords from a variable-node memory using a first order via the memory-index control circuit for LDPC decoding. In response to the decoder determining that a specific codeword among the first codewords has decoding failure, the decoder is reset to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding. The first order is different from the second order.

Abstract: Novel and useful system and methods of functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The NN processor incorporates functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.

Abstract: A method for operating a memory includes: performing an error check operation on first memory cells; performing an error check operation on second memory cells; detecting an error which is equal to or greater than a threshold value in a region including the first memory cells and the second memory cells; classifying the region as a bad region in response to the detection of an error which is equal to or greater than the threshold value; and performing an error check operation on the first memory cells and the second memory cells again in response to the classification of the bad region.

Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.

Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first group of sets of parity data that each protect data stored in a row of memory cells of an array is generated. Further, a second group of sets of parity data that each protect data stored in a column of memory cells of an array is generated. The first set of parity data and the second set of parity data is sent to a host for further ECC processing. The host provides ECC data to the memory device based on the first set of parity data and the second set of parity data. The memory device repairs memory cells or retires memory cells based on the provided ECC data.

Abstract: A decoder circuit includes first and second decoders. The first decoder is a first type of decoder configured to receive data encoded with an error correction code and decode and eliminate errors from a first subset of codewords of the data. The second decoder is a second type of decoder configured receive the data encoded with the error correction code and decode and eliminate errors from a second subset of codewords of the data, different from the first subset of the codewords, without attempting to decode and eliminate errors from the first subset of the codewords.

Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.

Abstract: Methods, systems, and devices for wireless communications are described. A wireless communication system may support techniques for correlation-based hardware sequences for layered decoding. In some cases, a user equipment (UE) may partition layers of a submatrix associated with a parity check decoding procedure into a first set of layers and a second set of layers. The UE may sort each set of layers into a respective set of layer orders (e.g., a first set of layer orders and a second set of layer orders) based on an associated set of correlation values. The UE may combine the first set of layer orders and the second set of layer orders to obtain a set of combined layer orders and may select a decoding schedule from a set of decoding schedules used for decoding each of the combined layer orders based on respective schedule lengths for the set of decoding schedules.