Double Encoding Codes (e.g., Product, Concatenated) Patents (Class 714/755)
  • Patent number: 11368249
    Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 21, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Rong Li, Gongzheng Zhang, Ying Chen, Xiaocheng Liu, Jun Wang
  • Patent number: 11347580
    Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Huimin Chen, Andrew Martwick, Howard Heck, Robert Dunstan, Dennis Bell, Abdul Ismail
  • Patent number: 11340986
    Abstract: Systems and methods for host-assisted storage device error correction are described. A host may first encode host data with a forward error correction code (ECC) and send the encoded host data to the storage device. The storage device may further encode the host data using its own ECC. The host may also provide the forward ECC parity information to be stored on the storage device in a different location than the host data. When the host data is read by the storage device, the storage device will decode with its ECC. If the storage device ECC decode is incomplete and the bit error rate is below the recoverable error threshold of the forward error correction, the partially-recovered host data will be sent to the host. The host will complete decode using the forward ECC and parity data. Forward ECC may be selectively applied to important host data.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: May 24, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Akhilesh Yadav, Ramanathan Muthiah
  • Patent number: 11334425
    Abstract: A method begins by a processing module of a storage network receiving a first plurality of pairs of coded values corresponding to first data segments of a first data stream and a second data stream. The method continues with the processing module generating a received coded matrix to include a plurality of groups of selected coded values and when the received coded matrix includes a decode threshold number of pairs of coded values, generating a data matrix from the received coded matrix and an encoding matrix. The method continues with the processing module reproducing the first data segment of the first and second data streams, while maintaining the time alignment of the first and second data streams.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 17, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 11336429
    Abstract: The present invention relates to a method for a secure execution of a whitebox cryptographic algorithm applied to a message (m) and protected by countermeasures based on pseudo-random values, comprising the steps of: executing a pseudo-random function (PRP) generating pseudo-random output values and an encrypted main output value based on an encrypted input value (*Xi*) derived from said message, securing said cryptographic algorithm by applying to the cryptographic algorithm said countermeasures based on said generated pseudo-random output values retrieving, from said generated encrypted main output value, the input value or part of the input value, under an encrypted form (*Xi*), executing said secured cryptographic algorithm on said encrypted retrieved value.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 17, 2022
    Assignee: THALES DIS FRANCE SA
    Inventors: Aline Gouget, Jan Vacek
  • Patent number: 11329672
    Abstract: A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: May 10, 2022
    Assignee: PANASONIC CORPORATION
    Inventor: Mihail Petrov
  • Patent number: 11329673
    Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Stephen D. Hanna
  • Patent number: 11321171
    Abstract: Techniques of memory operations management are disclosed herein. One example technique includes retrieving, from a first memory, data from a data portion and metadata from a metadata portion of the first memory upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first memory currently contains data corresponding to the system memory section in the received request. In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 3, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
  • Patent number: 11322219
    Abstract: A memory system may include a memory controller suitable for transmitting write data and a first write ECC corresponding to the write data during a write operation, a first error correction circuit suitable for detecting whether the write data received from the memory controller has an error, using the first write ECC received from the memory controller, and correcting the error when the error is detected, a second ECC generation circuit suitable for generating a second write ECC using the write data received from the memory controller, and generating the second write ECC using the write data whose error has been corrected by the first error correction circuit, when the detection of the error is noticed from the first error correction circuit, and one or more memories suitable for storing the second write ECC and write data corresponding to the second write ECC.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Hoiju Chung, Paul Fahey
  • Patent number: 11316585
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for channel bonding in an adaptive coding and modulation mode. In some implementations, a system receives packets of a data stream for transmission in a satellite communications system. The system determines a modulation and coding arrangement for the received packets. The system generates code blocks that include data from the packets of the data stream. The system assigns the generated code blocks for transmission on different carriers. One or more of the different carriers is operated in an adaptive coding and modulation mode to support multiple modulation and coding arrangements within a single carrier. The system transmits the code blocks on the different carriers using the determined one or more modulation and coding arrangements.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 26, 2022
    Assignee: Hughes Network Systems, LLC
    Inventors: Liming Qin, Bala Subramaniam, Sri Bhat, Brandon Lasher
  • Patent number: 11314425
    Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure. The error recovery can include determining if each CW of the set of CWs is correctable by an EH step, storing indications of CWs determined correctable by the EH step in the error recovery data structure, determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Harish Reddy Singidi, Ting Luo, Kishore Kumar Muchherla
  • Patent number: 11308041
    Abstract: N storage nodes that are coupled via a network are selected to store a file of size |F| and redundancy of size |Fred|. A value Z<N is selected such that an attacker having access to Z storage nodes is unable to decode any partial information of the file. The file is divided into d partitions of size |PsN|, wherein |PsN| is a maximum factor of |F| subject to |PsN|?|sN|. Independent linear combinations hi's of the d partitions are created and random keys are generated and stored in the first Z of the N storage nodes. Independent linear combinations gi's of the random keys are created and combinations of the hi's and gi's are stored in the Z+1 to Nth storage nodes.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: April 19, 2022
    Assignee: Seagate Technology LLC
    Inventors: Yasaman Keshtkarjahromi, Mehmet Fatih Erden
  • Patent number: 11296723
    Abstract: Embodiments of the present disclosure provide methods and apparatuses for data processing in a communication system. For example, the method comprises: generating, based on an intended performance, an error detection code to be used; distributing bits of the error detection code in information bits to be coded; and perform polar encoding on the information bits together with the error detection code distributed in the information bits. The embodiments of the present disclosure also provide a communication device capable of implementing the method.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 5, 2022
    Assignee: Alcatel Lucent
    Inventor: Yu Chen
  • Patent number: 11296820
    Abstract: Provided are a signaling coding and modulation method and a demodulation and decoding method and device, characterized in that the method comprises the steps of: extending signaling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; conducting parity bit permutation on a parity bit portion in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword; according to the length of the signaling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the tuple sequence.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: April 5, 2022
    Assignee: Shanghai National Engineering Research Center of Digital Television Co., Ltd.
    Inventors: Wenjun Zhang, Yijun Shi, Dazhi He, Ge Huang, Hongliang Xu, Yao Wang
  • Patent number: 11288139
    Abstract: Recovery of chunk segments stored via hierarchical erasure coding in a geographically diverse data storage system is disclosed. Chunks can be stored according to a first-level erasure coding scheme in zones of a geographically diverse data storage system. The chunks can then be further protected via one or more second-level erasure coding schema within a corresponding zone of the geographically diverse data storage system. In response to determining a segment of a chunk has become less accessible, recovering at least the segment to enable intra-zone recovery of the compromised chunk can be performed according to the hierarchical erasure coding scheme of relevant chunks at relevant zones of the geographically diverse data storage system.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 29, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Yohannes Altaye
  • Patent number: 11290247
    Abstract: In various embodiments, the disclosed systems, methods, and apparatuses describe the application of non-orthogonal multiple access (NOMA) over networks (e.g., cable networks). In particular, the disclosure describes: determining a signal for transmission to a receiving device; determining, by a processing component of the device, parameters associated with the transmission of the signal, the parameters comprising at least one of a power level, a modulation scheme, a frequency band, and a power spectral density; and transmitting, by a transmitting component of the device, the signal over a medium based on the parameters and using a NOMA technique.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 29, 2022
    Assignee: Cox Communications, Inc.
    Inventor: Jeffrey L. Finkelstein
  • Patent number: 11281526
    Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 22, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Alain Artieri, Deepti Vijayalakshmi Sriramagiri, Dexter Tamio Chun, Jungwon Suh
  • Patent number: 11277221
    Abstract: Systems and methods for ACM trajectory include receiving data at a communications receiver; decoding the received data based on a selected MODCOD; monitoring a number of iterations used to decode the data using the selected MODCOD; comparing the number of iterations used to decode the data using the first selected MODCOD to a reference number of iterations; and adjusting a SNR threshold value for the selected MODCOD where the number of iterations used to decode the data using the first selected MODCOD is greater than the reference number of iterations.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: March 15, 2022
    Assignee: HUGHES NETWORK SYSTEMS, LLC
    Inventors: Bala Subramaniam, Yanlai Liu
  • Patent number: 11272190
    Abstract: An integrated circuit is provided. The integrated circuit includes a first volatile memory, a second volatile memory, and a video decoder. In response to the video decoder starting video decoding on a current frame of a video stream, the video decoder reads an initial probability table for the current frame from a memory unit external to the integrated circuit, and stores the initial probability table in the first volatile memory. When a decoding phase of the current tile is completed, the video decoder complements the probability table corresponding to each row of the second volatile memory according to control flags corresponding to the rows of the first volatile memory and the second volatile memory to obtain a complete probability table, and writes the complete probability table to the memory unit.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: March 8, 2022
    Assignee: GLENFLY TECHNOLOGY CO., LTD.
    Inventors: Shuoshuo Liu, Wei Wang, Ruiyang Chen
  • Patent number: 11265107
    Abstract: Channel encoding is provided that includes applying turbo coding with a coding rate of 1/5 to an input bit sequence, applying a subblock interleaver to each of first to fifth code bit sequences to which the turbo coding is applied, applying bit collection to the first to fifth code bit sequences output from the subblock interleaver, the bit collection outputting the first code bit sequence in order, outputting the second code bit sequence and the fourth code bit sequence alternately on a bit-by-bit basis after the first code bit sequence, and outputting the second code bit sequence and the fifth code bit sequence alternately on a bit-by-bit basis.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: March 1, 2022
    Assignees: SHARP KABUSHIKI KAISHA, FG Innovation Company Limited
    Inventors: Kazunari Yokomakura, Shohei Yamada, Hidekazu Tsuboi, Hiroki Takahashi, Tatsushi Aiba
  • Patent number: 11256569
    Abstract: A data processing apparatus is provided, which includes storage circuitry comprising a plurality of lines, each of the plurality of lines comprising a data value. Access circuitry accesses a pair of the plurality of lines at a time, the pair of the plurality of lines comprising a further data value, distinct from the data value, and a plurality of error bits to detect or correct errors in the data value in each line in the pair of the plurality of lines.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: February 22, 2022
    Assignee: Arm Limited
    Inventors: Mark Gerald LaVine, Simon John Craske
  • Patent number: 11245425
    Abstract: A communication system includes a transmitter having an encoder configured to encode input data using FEC codewords and a receiver including a decoder configured to decode the FEC codewords using a parity check matrix. The decoder includes check node processing units each configured to perform a check node computation on an FEC codeword using a different row of the parity check matrix. Each of the check node processing units includes an input computation stage configured to compute initial computation values, a pipelined message memory configured to shift the initial computation values at a predefined clock interval, an output computation stage configured to generate a plurality of check node output messages, a plurality of variable node processing units each configured to perform variable node update computations to generate the variable node messages, and an output circuit configured to generate a decoded codeword based on the variable node messages.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: February 8, 2022
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Damian Alfonso Morero, Mario Alejandro Castrillon, Matias German Schnidrig, Mario Rafael Hueda
  • Patent number: 11223448
    Abstract: An operation method of a first communication node in a communication system includes receiving a signal from a second communication node; demodulating the signal to obtain LLR values; calculating a first codeword based on the LLR values; selecting error patterns from among all error patterns based on Hamming weights; generating second codewords by applying the first codeword to each of the selected error patterns; and determining a codeword having a highest similarity to the first codeword among the second codewords as an optimal codeword.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: January 11, 2022
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ok Sun Park, Gi Yoon Park, Seok Ki Kim, Woo Ram Shin, Tae Joong Kim, Jae Sheung Shin, Young Ha Lee
  • Patent number: 11218168
    Abstract: A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 4, 2022
    Assignee: SILICON MOTION, INC.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 11211094
    Abstract: A data storage device configured to access a magnetic tape is disclosed, wherein the data storage device comprises at least one head configured to access the magnetic tape. A first plurality of data blocks are encoded into a first plurality of ECC sub-blocks including a first ECC sub-block, and the first plurality of ECC sub-blocks are encoded into a first ECC super-block. The first ECC sub-block is written to the magnetic tape, and a write-verify of the first ECC sub-block is executed by reading the first ECC sub-block. When the write-verify passes, a second plurality of data blocks are encoded into a second ECC super-block, and when the write-verify fails, a third plurality of data blocks and the first ECC sub-block are encoded into the second ECC super-block, wherein the second ECC super-block is written to the magnetic tape.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: December 28, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Robert L. Horn, Derrick E. Burton
  • Patent number: 11211950
    Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: December 28, 2021
    Assignee: Kioxia Corporation
    Inventors: Kuminori Hyodo, Kenji Sakurada, Yasuhiko Kurosawa, Takashi Nakagawa
  • Patent number: 11210163
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: December 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
  • Patent number: 11205498
    Abstract: A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: December 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Amit Berman, Evgeny Blaichman, Ron Golan, Sergey Gendel
  • Patent number: 11204839
    Abstract: Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Haobo Wang, Xuanxuan Lu, Meysam Asadi
  • Patent number: 11206043
    Abstract: Devices, systems and methods for reducing complexity of a bit-flipping decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Meysam Asadi, Fan Zhang, Aman Bhatia, Xuanxuan Lu, Haobo Wang
  • Patent number: 11206048
    Abstract: This application provides a polar encoding and decoding method, a sending device, and a receiving device, to help overcome disadvantages in transmission of medium and small packets, a code rate, reliability, and complexity in the prior art.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: December 21, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ying Chen, Gongzheng Zhang, Yunfei Qiao, Rong Li, Huazi Zhang, Hejia Luo
  • Patent number: 11196444
    Abstract: Certain aspects of the present disclosure generally relate to techniques for encoding and decoding bits of information using cyclic redundancy check (CRC) concatenated polar encoding and decoding. The CRC concatenated polar encoding techniques may avoid transmission of dummy bits. A method generally includes obtaining the bits of information to be transmitted. The method includes performing CRC outer encoding of the bits of information using an even-weighted generator polynomial to produce CRC encoded bits. The method includes performing polar inner encoding of the CRC encoded bits to generate a codeword. The method includes discarding a first code bit at a beginning of the codeword. The shortened codeword is transmitted over a wireless medium. In another method, bit-level scrambling is performed on the CRC encoded bits before the polar encoding to avoid generating a dummy bit. In another method, only odd-weighted generator polynomials are selected to avoid generating the dummy bit.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 7, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Kai Chen, Liangming Wu, Changlong Xu, Jing Jiang, Hao Xu
  • Patent number: 11182248
    Abstract: Methods and apparatus to dynamically assign and relocate object fragments in distributed storage systems are disclosed.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Paul E. Luse, John Dickinson, Samuel Merritt, Clay Gerrard
  • Patent number: 11184035
    Abstract: A decoder decodes a soft information input vector represented by an input vector that is binary and that is constructed from the soft information input vector. The decoder stores even parity error vectors that are binary and odd parity error vectors that are binary for L least reliable bits (LRBs) of the input vector. The decoder computes a parity check of the input vector, and selects as error vectors either the even parity error vectors or the odd parity error vectors based at least in part on the parity check. The decoder hard decodes test vectors, representing respective sums of the input vector and respective ones of the error vectors, based on the L LRBs, to produce codewords that are binary for corresponding ones of the test vectors, and metrics associated with the codewords. The decoder updates the soft information input vector based on the codewords and the metrics.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 23, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Mohammad Ali Sedaghat, Andreas Bernhard Bisplinghoff, Glenn Elliot Cooper
  • Patent number: 11184112
    Abstract: Systems and methods include receiving blocks of data that has been Forward Error Correction (FEC) encoded via Open Forward Error Correction (OFEC) adaptation; decoding the blocks of data; processing Cyclic Redundancy Check (CRC) data that is included in padding data required in the OFEC adaptation, wherein the padding data is distributed across N rows of payload data; and determining a location of any errors in the payload data based on the processed CRC data. The OFEC adaptation is for mapping the blocks of data into any of a FlexO-x frame structure, a ZR frame structure, and variants thereof, and the location of any errors can be used for error marking.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: November 23, 2021
    Assignee: Ciena Corporation
    Inventors: Sebastien Gareau, Jeffery Thomas Nichols
  • Patent number: 11177832
    Abstract: The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 16, 2021
    Assignee: Saturn Licensing LLC
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 11169873
    Abstract: One embodiment facilitates data placement in a storage device. During operation, the system receives a request indicating first data to be written to a non-volatile memory which includes a plurality of dies, wherein a plurality of error correction code (ECC) codec modules reside on the non-volatile memory. The system receives, by a first codec module residing on a first die, the first data. The system encodes, by the first codec module operating on the first die, the first data based on an error correction code (ECC) to obtain first ECC-encoded data which includes a first set of ECC parity bits. The system writes the first ECC-encoded data to the first die.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: November 9, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11165447
    Abstract: There is provided a method of sequential list decoding of an error correction code (ECC) utilizing a decoder comprising a plurality of processors. The method comprises: a) obtaining an ordered sequence of constituent codes usable for the sequential decoding of the ECC; b) executing, by a first processor, a task of decoding a first constituent code, the executing comprising: a. generating decoding candidate words (DCWs) usable to be selected for decoding a subsequent constituent code, each DCW associated with a ranking; b. for the first constituent code, upon occurrence of a sufficiency criterion, and prior to completion of the generating all DCWs and rankings, selecting, in accordance with a selection criterion, at least one DCW; c) executing, by a second processor, a task of decoding a subsequent constituent code, the executing comprising processing data derived from the selected DCWs to generate data usable for decoding a next subsequent constituent code.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: November 2, 2021
    Assignee: TSOFUN ALGORITHMS LTD.
    Inventors: Eldad Meller, Noam Presman, Alexander Smekhov, Nissim Halabi
  • Patent number: 11159175
    Abstract: Systems, apparatuses and methods may provide for technology to receive a codeword containing an SC-LDPC code and conduct a min-sum decode of the SC-LDPC code based on a plurality of scaling factors. In an embodiment, the scaling factors are non-uniform across check nodes and multiple iterations of the min-sum decode.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Santhosh K. Vanaparthy, Ravi H. Motwani
  • Patent number: 11152955
    Abstract: Disclosed are a method and an apparatus for fast decoding a linear code based on soft decision. The method may comprise sorting received signals in a magnitude order to obtain sorted signals; obtaining hard decision signals by performing hard decision on the sorted signals; obtaining upper signals corresponding to MRBs from the hard decision signals; obtaining a permuted and corrected codeword candidate using the upper signals and an error vector according to a current order; calculating a cost for the current order using a cost function; determining the permuted and corrected codeword candidate as a permuted and corrected codeword according to a result of comparing the calculated cost with a minimum cost; and determining a predefined speeding condition.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: October 19, 2021
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Chang Ryoul Choi, Je Chang Jeong
  • Patent number: 11153044
    Abstract: The present invention relates to a method and a device for a terminal transmitting/receiving data in a wireless communication system. According to the present invention, a method and a device may be provided by which a first message comprising first control information is received from a base station, wherein the first control information comprises a logical path identifier (ID) indicating a logical path for transmitting/receiving first data and second data, which is the same as the first data; as a response to the first message, a reply message is transmitted to the base station; and the first data and the second data are transmitted, to the base station, on multiple component carriers (CC) associated with the logical path corresponding to the logical path ID.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 19, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Hyunjin Shim, Heejeong Cho, Jiwon Kang, Ilmu Byun, Heejin Kim, Genebeck Hahn
  • Patent number: 11150983
    Abstract: A sensor apparatus includes a sensing means having one or more sensors. A processor unit processes data received from the one or more sensors. The processor unit has a processor, a memory which stores data used by the processor, and a memory controller that receives instructions from the processor and in response writes data output from the processor to the memory or retrieves data from the memory to the processor. The memory controller is configured to read and write data to one or more areas of the memory with ECC protection of the data and arranged to read and write data to one or more areas of the memory without applying any ECC protection. The sensor apparatus may be configured to process data captured from an antenna to identify the position and/or the range of at least one target in the line of sight of the antenna.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: October 19, 2021
    Assignee: TRW LIMITED
    Inventor: Martin Thompson
  • Patent number: 11153040
    Abstract: An origination device (e.g., a base station) dual encodes a first set of data (1) according to a first set of encoding parameters corresponding to channel conditions associated with a first communication link, and (2) according to a second set of encoding parameters corresponding to channel conditions associated with a second communication link. The dual-encoded first set of data is transmitted to a signal forwarding device. The signal forwarding device decodes the dual-encoded first set of data, using decoding parameters that correspond to the second set of encoding parameters, to generate a single-encoded first set of data that is encoded according to the first set of encoding parameters. The signal forwarding device transmits a “single-encoded forwarded signal” to the destination device. The destination device decodes the single-encoded forwarded signal using decoding parameters that correspond to the first set of encoding parameters, which yields the first set of data.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 19, 2021
    Assignee: Kyocera Corporation
    Inventors: Amit Kalhan, Henry Chang
  • Patent number: 11133832
    Abstract: Embodiments of this application disclose a data processing method and a data processing device. The method includes: obtaining a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a transport block or a code block generated by performing code block segmentation on a transport block; encoding the first to-be-processed bit sequence to obtain a first encoded bit sequence; storing all or at least some bits of the first encoded bit sequence into a circular buffer; and outputting a first output bit sequence from the bits stored in the circular buffer. According to the method and the device that are provided in this application, rate matching can be implemented for a sequence generated through LDPC encoding.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: September 28, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Liang Ma, Chen Zheng, Xin Zeng, Yuejun Wei
  • Patent number: 11128740
    Abstract: An embodiment may involve executing a set of instructions, where the set of instructions define how to generate outputs that represent one or more data packets, and where segments of the outputs are copied from first parts of respective instructions in the set of instructions. The embodiment may further involve: retrieving, from a plurality of registers, a data packet header; retrieving, from the plurality of registers, a first part of a data packet payload and an increment value; applying the increment value to the first part of the data packet payload to generate a second part of the data packet payload; storing, in the plurality of registers, the first part of the data packet payload with the increment value applied; and providing, as additional segments of the outputs, the data packet header, the first part of the data packet payload, and the second part of the data packet payload.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: September 21, 2021
    Assignee: fmad engineering kabushiki gaisha
    Inventor: Aaron Foo
  • Patent number: 11121809
    Abstract: This application provides a channel encoding method and apparatus in wireless communications. The method includes: performing CRC encoding on A to-be-encoded information bits, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and A information bits; performing a interleaving operation on the first bit sequence, to obtain a second bit sequence, where a first interleaving sequence used for the interleaving operation is obtained based on a system-supported maximum-length interleaving sequence with the length of Kmax+L, and Kmax is a maximum information bit quantity corresponding to the maximum-length interleaving sequence ad a preset rule, and a length of the first interleaving sequence is equal to A+L. Therefore, during distributed CRC encoding, when an information bit quantity is less than the maximum information bit quantity, an interleaving sequence required for completing an interleaving process is obtained based on the system-supported maximum-length interleaving sequence.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 14, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Lingchen Huang, Shengchen Dai, Chen Xu, Yunfei Qiao, Rong Li
  • Patent number: 11115058
    Abstract: In a coding device (20), a first coding unit (21) generates a parity of an RS code by coding, based on the RS code, each first data sequence existing in a direction different from a row direction of input data, and generates coded data by attaching the parity of the RS code to each first data sequence, thereby consequently expanding a matrix. A second coding unit (22) generates a parity of a BCH code and a parity of an LDPC code by coding, based on the BCH code and the LDPC code, each second data sequence existing in a row direction of the coded data, and generates a plurality of DVB-S2 frames (13) including, per DVB-S2 frame (13), one data sequence existing in the row direction of the coded data, the corresponding parity of the BCH code, and the corresponding parity of the LDPC code.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 7, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideo Yoshida, Shinya Hirakuri, Toshiyuki Kuze
  • Patent number: 11108407
    Abstract: Techniques are described for improving the decoding latency and throughput of an error correction system that includes a bit flipping (BF) decoder, where the BF decoder uses a bit flipping procedure. In an example, different decoding parameters are determined including any of a decoding number of a decoding iteration, a checksum of a codeword, a degree of a variable node, and a bit flipping threshold defined for the bit flipping procedure. Based on one or more of these decoding parameters, a decision can be generated to skip the bit flipping decoding procedure, thereby decreasing the decoding latency and increasing the decoding throughput. Otherwise, the bit flipping decoding procedure can be performed to compute a bit flipping energy and determine whether particular bits are to be flipped or not. Hence, the overall performance (e.g., bit error rate) is not significantly impacted.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventors: Xuanxuan Lu, Fan Zhang, Aman Bhatia, Meysam Asadi, Haobo Wang
  • Patent number: 11106534
    Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a currant value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 31, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Pi-Feng Chiu, Dejan Vucinic
  • Patent number: 11101823
    Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuyuki Imaizumi, Satoshi Shoji, Mitsunori Tadokoro, Takashi Ishiguro, Yifan Tang