Abstract: A device for decoding a generalized concatenated code (GCC) codeword includes: a buffer; and at least one processor configured to: obtain the GCC codeword, calculate a plurality of inner syndromes based on a plurality of frames; calculate a plurality of sets of delta syndromes based on the frames; determine a plurality of outer syndromes based on the sets of delta syndromes; store the inner syndromes and the outer syndromes in a buffer; perform inner decoding on the frames based on the inner syndromes stored in the buffer; update at least one outer syndrome stored in the buffer based on a result of the inner decoding; perform outer decoding on the frames based on the updated at least one outer syndrome; and obtain decoded information bits corresponding to the GCC codeword based on a result of the inner decoding and the result of the outer decoding.

Abstract: Embodiments of this application provide a method for processing information bits in a wireless communication network. A device obtains a Polar encoded bit sequence, then divide the Polar encoded bit sequence into g groups that are of equal length N/g, wherein g is 32. The device block interleaves the g groups to obtain an interleaved bit sequence according to a sequence S, wherein the sequence S comprises: group numbers of the g groups, wherein a group whose number is 0 is the first element in the sequence S, wherein a group whose number is 12 is the 17th element in the sequence S, wherein a group whose number is 31 is the 32nd element in the sequence S, wherein the S is an integer and output the interleaved bit sequence.

Abstract: Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller and a memory component operably coupled to the controller. The controller can include a memory manager, a quality metrics first in first out (FIFO) circuit, and an error correction code (ECC) decoder. In some embodiments, the ECC decoder can generate quality metrics relating to one or more codewords saved in the memory component and read into the controller. In these and other embodiments, the ECC decoder can stream the quality metrics to the quality metrics FIFO circuit, and the quality metrics FIFO circuit can stream the quality metrics to the memory manager. In some embodiments, the memory manager can save all or a subset of the quality metrics in the memory component and/or can use the quality metrics in post-processing, such as in error avoidance operations of the memory device.

Abstract: A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.

Abstract: Examples in this application provide a wireless communication method and device. One example method includes obtaining downlink control information and a scrambled sequence from a network device, where bits corresponding to the scrambled sequence are scrambled with each piece of configuration information of a plurality of pieces of configuration information used for configuring a terminal device by the network device, each piece of the configuration information corresponds to at least one bit in the scrambled sequence, and at least one bit of the bits that correspond to each piece of the configuration information does not correspond to another piece of configuration information of the plurality of pieces of the configuration information, descrambling, based on a possible value of each piece of the configuration information, the bits corresponding to each piece of the configuration information, to obtain a descrambled sequence, and performing a check operation using the descrambled sequence and the DCI.

Abstract: A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.

Abstract: Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more error correction procedures that may be performed by the host device, the memory device, or both to correct transmission- or storage-related errors within the system. The error detection procedure may be configured to detect up to a quantity of errors within the data, where the quantity of errors may be greater than a quantity of errors reliably corrected by the one or more error correction procedures. For example, the error detection procedure may be configured to detect a sufficient quantity of errors so as to protect against possible aliasing errors associated with the one or more error correction procedures.

Abstract: A memory system may include a memory controller suitable for transmitting write data and a first write ECC corresponding to the write data during a write operation, a first error correction circuit suitable for detecting whether the write data received from the memory controller has an error, using the first write ECC received from the memory controller, and correcting the error when the error is detected, a second ECC generation circuit suitable for generating a second write ECC using the write data received from the memory controller, and generating the second write ECC using the write data whose error has been corrected by the first error correction circuit, when the detection of the error is noticed from the first error correction circuit, and one or more memories suitable for storing the second write ECC and write data corresponding to the second write ECC.

Abstract: A frame error concealment method is provided that includes predicting a parameter by performing a regression analysis on a group basis for a plurality of groups formed from a first plurality of bands forming an error frame and concealing an error in the error frame by using the parameter predicted on a group basis.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for channel bonding in an adaptive coding and modulation mode. In some implementations, a system receives packets of a data stream for transmission in a satellite communications system. The system determines a modulation and coding arrangement for the received packets. The system generates code blocks that include data from the packets of the data stream. The system assigns the generated code blocks for transmission on different carriers. One or more of the different carriers is operated in an adaptive coding and modulation mode to support multiple modulation and coding arrangements within a single carrier. The system transmits the code blocks on the different carriers using the determined one or more modulation and coding arrangements.

Abstract: Provided is a method for transmitting a broadcasting content and a line content, the broadcasting content and the line content being synchronously displayed, the method including: generating a line parity packet from a plurality of line data packets in each of which the line content is stored; transmitting the line data packet and the line parity packet through a communication line; and transmitting a plurality of broadcasting data packets in each of which the broadcasting content is stored, from a base station using a broadcasting wave, a transfer clock time of the broadcasting content being delayed by a predetermined time compared with a transfer clock time of the line content. At this point, video quality can be improved when the real-time broadcasting program content and the real-time line content are simultaneously displayed.

Abstract: Consistent with a further aspect of the present disclosure, previously encoded data is stored in a memory, and an encoder accesses both input data and previously encoded data to generate new encoded data or a new codeword. Each codeword is stored in a row of the memory, and with each newly generated codeword, each previously stored code word is shifted to an adjacent row of the memory. In one example, the memory is delineated as a plurality of blocks including rows and columns of bits. When generating a new code word, randomly selected columns of bits in the memory are read from randomly selected blocks of the memory and supplied to the encoder. In this manner the number of times the memory is access is reduced and power consumption is reduced.

Abstract: In one aspect, the present disclosure relates to a method of de-duplicating data in a solid state storage device. The method can include receiving a block of data to be written to a solid state storage device, wherein the block of data comprises header portion and a payload, wherein the header portion comprises context information; and determining whether the payload should be de-duplicated prior to storage, based on the context information stored within the header portion; if the payload is determined to be de-duplicated, de-duplicating the payload; and storing the de-duplicated payload to the solid state storage device.

Abstract: An instance of an event associated with error correcting code operations performed on a data block of the non-volatile memory is identified. An entry for a record is generated. The entry is indicative of the instance of the event. Whether a frequency of the event satisfies a threshold condition based on the record is determined. Responsive to determining that the frequency of the event satisfies the threshold condition, a remix operation on the data block is performed to change a logical to physical association of the data block from a first logical association to a second logical association.

Abstract: According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.

Abstract: Systems and devices can include a port for transmitting data; and a link coupled to the port. The port, in preparation to transmit a data block across the link, to determine a size of a burst of data to be transmitted across the link; determine a plurality of error correcting code words for forward error correction based on the size of the burst of data; interleave each of the plurality of error correcting code words to correspond with consecutive symbols of the burst of data; and transmit the burst of data comprising the interleaved plurality of error correcting code across the link.

Abstract: A transmission device that performs multiple-input multiple-output (MIMO) transmission of transmit data using a plurality of fundamental bands. The transmission device includes an error correction coding unit, a mapping unit, and a MIMO coding unit. The error correction coding unit, for each data block of predefined length, performs error correction coding and thereby generates an error correction coded frame. The mapping unit maps each predefined number of bits in the error correction coded frame to a corresponding symbol and thereby generates an error correction coded block. The MIMO coding unit performs MIMO coding with respect to the error correction coded block. Components of data included in the error correction coded block are allocated to at least two of the fundamental bands and transmitted.

Abstract: A method and system for providing secure aerial or space communications. A general payload and a hosted payload are provided on a vehicle. The hosted payload encrypts a data packet that contains restricted data using a secure key to create an encrypted packet. The general payload encrypts the encrypted packet using a general key to create a multilayer-encrypted packet. The multilayer-encrypted packet is transmitted from the vehicle to a destination.

Abstract: Methods and transceivers transmit communication frames that comprise a sequence of N symbols, ensuing payload header symbols, and ensuing payload message symbols. The sequence of N symbols encodes information according to signal-to-noise ratio associated with the communication frame.

Abstract: A storage device is disclosed. The storage device may include storage for data. A controller may manage writing the data to the storage and reading the data from the reading storage. A data quality metric table may map a first number of errors to a first data quality metric and map a second number of errors to a second data quality metric. A transmitter may return the data quality metric table to a host.

Abstract: A method for decoding a low-density parity-check (LDPC) code, performed by a communication apparatus, includes: updating a variable node; determining n minimum values based on a min-sum algorithm (MSA); determining n indices based on the n minimum values; updating a check node using the n indices; calculating a log-likelihood ratio (LLR) value when the update of the check node is completed; and determining an information bit based on the LLR value.

Abstract: A technique provides preferential treatment to metadata over user data when protecting data in a mapped-RAID system. The technique involves generating metadata based on user data, storing the metadata in mirrored storage of the mapped-RAID system (e.g., 2-way mirrored storage), and storing the user data in non-mirrored storage of the mapped-RAID system (e.g., writing user data with parity in accordance with RAID 6). The mapped-RAID system provides reliability preference toward maintaining the metadata over maintaining the user data while the metadata and the user data are stored within the mapped-RAID system. Accordingly, the technique is able to concurrently provide high reliability and high storage efficiency.

Abstract: This application provides a data transmission method, a base station, and a terminal device. The method includes: determining, by a base station, a target base graph in N Raptor-like LDPC base graphs; and sending, by the base station, indication information to a terminal device, where the indication information is used to indicate the terminal device to use the target base graph to perform LDPC encoding and decoding. Based on the foregoing technical solution, the base station may determine a target base graph in a plurality of Raptor-like LDPC base graphs that may be used to perform LDPC encoding and decoding, and indicate the target base graph to the terminal device. Further, for one code rate or one code length, the base station may select different base graphs as required.

Abstract: A security platform architecture is described herein. The security platform architecture includes multiple layers and utilizes a combination of encryption and other security features to generate a secure environment. A method, system and apparatus include/are configured for maintaining a secure vault, accessing building block modules and implementing an orchestrator. The vault stores code. The building block modules are formed using the code stored in the secure vault. The orchestrator controls access to the building block modules.

Abstract: In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.

Abstract: Devices, systems and methods for improving reliability and security of a memory system are described. An example method includes receiving a seed value and a data stream, generating, based on the seed and using a physical unclonable function (PUF) generator, a PUF data pattern, generating, based on the seed, a pseudo-random data pattern, performing a first logic operation on the PUF data pattern and the data stream to generate a result of the first logic operation as a first data sequence, and performing a second logic operation on the pseudo-random data pattern and a second data sequence that is based on the first data sequence to generate a result of the second logic operation as a third data sequence for storage on the memory system, wherein the PUF generator is selected at least in-part based on one or more physical characteristics of the memory system.

Abstract: Methods and apparatus for training a Neural Network to recover a codeword of a Forward Error Correction (FEC) code are provided. Trainable parameters of the Neural Network are optimised to minimise a loss function. The loss function is calculated by representing an estimated value of the message bit output from the Neural Network as a probability of the value of the bit in a predetermined real number domain and multiplying the representation of the estimated value of the message bit by a representation of a target value of the message bit. Training a neural network may be implemented via a loss function.

Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.

Abstract: A method for providing ciphertext data by a first computing device having memory includes obtaining, from the memory, plaintext data having a structure; providing the plaintext data to a structure preserving encryption network (SPEN) to generate the ciphertext data, where the structure of the plaintext data corresponds to a structure of the ciphertext data; and communicating, from the first computing device to a second computing device, the ciphertext data to permit analysis on the ciphertext data.

Abstract: Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.

Abstract: A donor communication station transmits a unicast transmission comprising a plurality of device data sets where each device data set directed to each of a plurality of user equipment (UE) devices. A relay node receives the unicast transmission and retransmits the data sets in a broadcast transmission over a broadcast communication channel to the plurality of UE devices. In one example, the donor communication station encodes data for multiple user equipment (UE) devices by applying broadcast encoding to the data for each device before applying outer encoding to the data. The dual encoded data is transmitted to the relay node over a dedicated channel. The relay node applies outer decoding to the dual encoded data to retrieve the broadcast encoded data. The relay node then transmits the broadcast encoded device data in a broadcast transmission without outer encoding.

Abstract: A multi-chip module includes a first Integrated Circuit (IC) die a second IC die. The first IC die includes an array of first bond pads, a plurality of first code group circuits, and first interleaved interconnections between the plurality of first code group circuits and the array of first bond pads, the first interleaved interconnections including a first interleaving pattern causing data from different code group circuits to be coupled to adjacent first bond pads. The second IC die includes a second array of bond pads that electrically couple to the array of first bond pads, a plurality of second code group circuits, and second interleaved interconnections between the plurality of second code group circuits and the array of second bond pads, the second interleaved interconnections including a second interleaving pattern causing data from different code groups to be coupled to adjacent second bond pads.

Abstract: Disclosed are a high-voltage pulse generator and a communication method therefor. The high-voltage pulse generator comprises a master controller and a sub-controller. Data transmitted between the master controller and the sub-controller at least comprise a first class of data and a second class of data, and, the second class of data at least comprise two types. The communication method comprises the following steps: during the present instance of transmitting a first class of data, transmitting partial types of a second class of data; during the next instance of transmitting the first class of data, transmitting other types of second class of data; and repeatedly executing the step until the transmission of all types of second class of data is completed. The present application ensures an increased real time performance in the transmission of the first class of data; moreover, controller pin resources occupied are reduced, costs are reduced, and the problem of data conflict is avoided.

Abstract: A method and apparatus for content aware decoding utilizes a pool of decoders shared data statistics. Each decoder generates statistical data of content it decodes and provides these statistics to a joint statistics pool. As codewords arrive at the decoder pool, the joint statistics are utilized to estimate or predict any corrupted or missing bit values. Codewords may be assigned to a specific decoder, such as a tier 1 decoder, a tier 2 decoder, or a tier 3 decoder, based on a syndrome weight or a bit error rate. The assigned decoder updates the joint statistics pool after processing the codeword. In some embodiments, each decoder may additionally maintain local statistics regarding codewords, and use the local statistics when there is a statistically significant mismatch between the local statistics and the joint statistics pool.

Abstract: Methods and apparatus for training a neural network to recover a codeword and for decoding a received signal using a neural network are disclosed. According to examples of the disclosed methods, a syndrome check is introduced at even layers of the neural network during the training, testing and online phases. During training, optimisation of trainable parameters of the neural network is ceased after optimisation at the layer at which the syndrome check is satisfied. Examples of the method for training a neural network may be implemented via a proposed loss function. During testing and online phases, propagation through the neural network is ceased at the layer at which the syndrome check is satisfied.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may map hybrid automatic repeat request acknowledgement (HARQ-ACK) feedback that includes a first HARQ-ACK bit associated with a high priority and a second HARQ-ACK bit associated with a low priority to a sequence cyclic shift value that provides an unequal reliability between the first HARQ-ACK bit and the second HARQ-ACK bit. The UE may transmit, to a base station, the HARQ-ACK feedback via a physical uplink control channel (PUCCH) format 0. Numerous other aspects are provided.

Abstract: Methods, systems, and devices for wireless communications are described. The following relates more specifically to hierarchical hybrid automatic repeat request (HARM) for multi-level coding with multi-level sequential demodulation and decoding and code block grouping per decoding level. A user equipment (UE) may receive, during a first time period, a transmission from a base station including a first and second code block group (CBG) with codeblocks associated with a first and second decoding level. The UE may fail to decode the first CBG, may not decode the second CBG, may store post processing samples for the second CBG, and may transmit a feedback message to the base station. The base station may retransmit the first CBG and new data on the second CBG in a second time period. The UE may decode the first CBG and use the post processing samples to decode the second CBG from the first time period.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Abstract: A data storage device including a memory device and a memory controller is disclosed. The memory controller including a super block includes a parity controller in communication with a memory device including a plurality of pages and configured to generate a first parity using data to be written to a first group of pages among the plurality of pages, and generate a second parity using data to be written to a second group of pages among the plurality of pages, a write operation controller configured to control the memory device to store the first parity and the second parity, and an error correction circuitry coupled to apply the first parity and the second parity to correct at least one of the plurality of pages arranged to belong to the first group of pages and the second group of pages.

Abstract: Systems and methods for correcting corrupted network packets are provided. An example method includes receiving a network packet via a communication channel. The network packet includes a payload and a Cyclic Redundancy Check (CRC) associated with the payload. The method continues with calculating a reference CRC based on the received payload and determining, based on the reference CRC and the received CRC, whether the network packet is corrupted. Based on the determination that the network packet is corrupted, the method continues with selecting a predetermined number of positions of bits in the payload of the network packet, precalculating a set of additional CRCs, and determining, based on the reference CRC and the set of additional CRCs, a combination of bit flips at the predetermined number of positions. The method also includes modifying the payload according to the combination of bit flips at the predetermined number of positions.

Abstract: A storage system includes: a control processor, configured to: read user data with a read threshold, determine which threshold adjustment range has been activated by reading a 1 and 0 counter, select an adjusted read threshold, based on the threshold adjustment range, to reread the user data in a physical block using the adjusted read threshold to correct the user data; and reading the user data in the physical block using the adjusted read threshold selected from the threshold adjustment range.

Abstract: The present disclosure generally relates to applying LDPC coding to memory cells with an arbitrary number of levels. Modulation code is applied to a first portion of user bits. The coded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block different from the first modulation block. Modulation code is then applied to a second portion of user bits which are stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a separate modulation block from the modulation block where the user data is stored.

Abstract: A method for decoding a signal encoded with polar codes by a decoding system is provided. The method comprises receiving, from a transmission system, a signal in which a plurality of cyclic redundancy checks (CRCs) are encoded by the polar codes, the plurality of CRCs being inserted into positions determined based on a plurality of information bits, a number of the plurality of information bits and a total code length, and decoding a code section including bits ranging from a first bit of the signal to a position where a last bit of a first CRC is inserted. The method further comprises re-performing successive cancellation flip decoding for the decoded code section, or determining whether to decode a next code section adjacent to the decoded code section, based on whether a CRC is detected in the decoded code section.

Abstract: Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Abstract: Provided is a coding control method in a passive optical network (PON). The method includes acquiring a codeword length N corresponding to a service to be coded; acquiring a matched coding mode corresponding to the codeword length N in a preset table describing a correspondence between codeword length ranges and coding modes; and coding data of the service by using the matched coding mode. Further provided are a coding control apparatus in a PON, a communication device and a storage medium.

Abstract: A memory device and a read method thereof are provided. The read method of the memory cell array includes: reading a memory cell array to obtain page data; dividing the page data into a plurality of chunk data; performing a first error correction operation on each of the chunk data in sequence to respectively generate a plurality of first corrected chunk data; performing a second error correction operation on the page data to generate corrected page data; and outputting the corrected chunk data by referring to an indicating signal.

Abstract: Systems and techniques described herein include jointly decoding coded data of different codes, including different coding algorithms, finite fields, and/or source blocks sizes. The techniques described herein can be used to improve existing distributed storage systems by allowing gradual data migration. The techniques can further be used within existing storage clients to allow application data to be stored within diverse different distributed storage systems.

Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.

Abstract: A method and system for transferring encrypted data from a first electronic device to a second electronic device. The method includes the steps of displaying a first encrypted two-dimensional code at the output interface of the first electronic device, reading the first encrypted two-dimensional code with the input interface of the second electronic device, and decrypting the first two-dimensional code with the second electronic device, generating a second encrypted two-dimensional code with the second electronic device, and displaying the second encrypted two-dimensional code on the output interface of the second electronic device, reading the second two-dimensional code encrypted with the input interface of the first electronic device and decrypting the second two-dimensional code with the first electronic device and generating an action on the first electronic device based on the second decrypted two-dimensional code. The second two-dimensional code is a plurality of two-dimensional codes.

Abstract: A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.