Double Encoding Codes (e.g., Product, Concatenated) Patents (Class 714/755)
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Patent number: 12374365Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. Mutual information metrics may be calculated based on a multi-bit symbol size to compensate for inter-symbol interference and compared to mutual information thresholds to determine the configuration settings, such as bit and track densities, error correction codes, and modulation codes. Mutual information metrics may be used to characterize heads and media independent of the configuration settings.Type: GrantFiled: December 6, 2023Date of Patent: July 29, 2025Assignee: Western Digital Technologies, Inc.Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Niranjay Ravindran, Jihoon Park
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Patent number: 12375105Abstract: A device is configured for encoding an input sequence comprising message bits into a codeword using a polar code. The device is configured to sequentially encode each of a plurality of blocks of the input sequence by applying a sliding window to the input sequence, wherein each block of the input sequence is encoded based on an XOR operation of the block and a previous block of the input sequence to obtain a codeword block of the codeword, and sequentially output each obtained codeword block of the codeword.Type: GrantFiled: July 27, 2022Date of Patent: July 29, 2025Assignee: Huawei Technologies Co., Ltd.Inventors: Valerio Bioglio, Carlo Condo
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Patent number: 12368456Abstract: The present disclosure may provide a method for operating a terminal in a wireless communication system. Herein, the method for operating the terminal may include determining a first polar code through an artificial intelligence (AI), transmitting data encoded in the first polar code and an information subchannel index set for the first polar code to a base station, receiving reward information based on decoding of the data from the base station, determining a second polar code by performing learning through the AI based on the reward information, and transmitting data encoded in the determined second polar code and an information subchannel index set for the second polar code to the base station.Type: GrantFiled: April 21, 2021Date of Patent: July 22, 2025Assignee: LG ELECTRONICS INC.Inventors: Jaeky Oh, Sungjin Kim, Jae Yong Park
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Patent number: 12362837Abstract: According to an aspect of the present invention, there is provided an optical signal demodulator including an optical reception unit, an AD conversion unit, a digital signal processing unit, and a signal determination unit, in which the signal determination unit includes: a spectrum shaping filter processing unit that receives a reception signal sequence of the digital signal from the digital signal processing unit and outputs a value obtained by performing a convolution operation on the reception signal sequence which is received; a transmission line simulation filter processing unit that outputs a value obtained by performing a convolution operation on a candidate signal sequence which is determined based on a symbol transition of the reception signal; an error information acquisition unit that acquires error information between the value output from the spectrum shaping filter processing unit and the value output from the transmission line simulation filter processing unit; and a bit determination unit thaType: GrantFiled: August 3, 2020Date of Patent: July 15, 2025Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Shuto Yamamoto, Masanori Nakamura, Hiroki Taniguchi, Yoshiaki Kisaka
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Patent number: 12355564Abstract: A communication device performs radio communication by using a plurality of channels, and includes: a generation unit that generates a plurality of bit sequences having different contents by applying predetermined coding processing based on a predetermined error correction coding method to a transmission data sequence; and a distribution unit that distributes the plurality of bit sequences to the plurality of channels.Type: GrantFiled: February 2, 2022Date of Patent: July 8, 2025Assignee: SONY GROUP CORPORATIONInventors: Mitsuki Takahashi, Hiroki Matsuda, Ryota Kimura
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Patent number: 12355565Abstract: Systems and devices can include a port for transmitting data; and a link coupled to the port. The port, in preparation to transmit a data block across the link, to determine a size of a burst of data to be transmitted across the link; determine a plurality of error correcting code words for forward error correction based on the size of the burst of data; interleave each of the plurality of error correcting code words to correspond with consecutive symbols of the burst of data; and transmit the burst of data comprising the interleaved plurality of error correcting code across the link.Type: GrantFiled: November 1, 2022Date of Patent: July 8, 2025Assignee: Intel CorporationInventor: Debendra Das Sharma
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Patent number: 12340090Abstract: Methods based on polyhedron models using computational operations for distributing data and parities among different data storage media. Devices, systems, and methods that split data into data strips, wherein the number of data strips equals the number of vertices of a polyhedron and respective ones of the number of the data strips correspond to respective ones of the number of vertices of the polyhedron; construct a number of parities, wherein the number of parities equals the number of faces of the polyhedron and respective ones of the number of parities correspond to respective ones of the number of parities of the polyhedron, wherein respective ones of the number of parities are constructed by computationally operating the data strips corresponding to vertices respectively associated with a face of the polyhedron corresponding to the respective parity; and distribute subsets of data strips and subsets of parities to subsets of storage media.Type: GrantFiled: December 22, 2023Date of Patent: June 24, 2025Assignee: Microchip Technology IncorporatedInventor: Anand Nagarajan
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Patent number: 12339738Abstract: A method for cyclic code encoding includes: generating, based on a first symbol sequence related to a first part of symbols in the K payload symbols, a first parity sequence corresponding to the first symbol sequence; generating, based on a second symbol sequence related to a second part of symbols in the K payload symbols, a second parity sequence corresponding to the second symbol sequence, where the first part of symbols are different from the second part of symbols; and generating the (N?K) parity symbols based on the first parity sequence and the second parity sequence.Type: GrantFiled: October 18, 2023Date of Patent: June 24, 2025Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Liang Li, Chun Yuan, Yuchun Lu, Lin Ma, Yongzhi Liu
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Patent number: 12341530Abstract: This application is directed to error correction for data stored in a memory device. In response to a request to validate a block of data, the memory device identifies a set of check nodes corresponding to a set of variable nodes that represent the block of data. First check node values of the check nodes are determined based on the block of data, and stored in first registers. The memory device implements a plurality of iterations of error correction by flipping a subset of variable nodes successively during each iteration; determining second check node values of the check nodes; and updating the first check node values stored in the first registers based on the second check node values once in each of a first set of iterations and successively with flipping of each variable node in a second set of iterations following the first set of iterations.Type: GrantFiled: December 20, 2023Date of Patent: June 24, 2025Assignee: SK Hynix NAND Product Solutions Corp.Inventors: Zion Kwok, Young Joon Ji
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Patent number: 12334151Abstract: An integrated circuit includes a memory storage having bit cells, a write path switch configured to have a connection state determined by a reliability indicator, and a write driver having an input configured to receive an input data from a write terminal through either a first write path or a second write path. The input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal. The reliability indicator is configured to be set based on a majority bit value in the data or based on a minority bit value in the data.Type: GrantFiled: July 12, 2024Date of Patent: June 17, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Win-San Khwa, Jui Jen Wu, Jen-Chieh Liu, Meng-Fan Chang
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Patent number: 12334954Abstract: A modified version of the min-sum algorithm (“MSA”) which can lower the error floor performance of quantized LDPC decoders. A threshold attenuated min-sum algorithm (“TAMSA”) and/or threshold offset min-sum algorithm (“TOMSA”), which selectively attenuates or offsets a check node log-likelihood ratio (“LLR”) if the check node receives any variable node LLR with magnitude below a predetermined threshold, while allowing a check node LLR to reach the maximum quantizer level if all the variable node LLRs received by the check node have magnitude greater than the threshold. Embodiments of the present invention can provide desirable results even without knowledge of the location, type, or multiplicity of such objects and can be implemented with only a minor modification to existing decoder hardware.Type: GrantFiled: March 21, 2024Date of Patent: June 17, 2025Assignees: Arrowhead Center, Inc., University of Notre Dame du LacInventors: Homayoon Hatami, David G. Mitchell, Daniel Costello, Thomas Fuja
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Patent number: 12321232Abstract: A requestor of a data processing system provides read access requests, full write access requests with corresponding full write data each having a full-width data size, and partial write access requests with corresponding partial write data each having a partial-width data size onto a system interconnect. A memory array stores write data and corresponding error correction code (ECC) check bits in response to write access requests and provides read data and corresponding ECC check bits for the read data in response to read access requests. A memory controller executes a read-modify-write (RMW) sequence between a store buffer and the memory array to implement a partial write transaction in response to a partial write access request, in which the memory controller stores the partial write data into the store buffer upon receiving the partial write access request and suppresses signaling of ECC errors to the requestor during the RMW sequence.Type: GrantFiled: October 4, 2023Date of Patent: June 3, 2025Assignee: NXP USA, Inc.Inventors: Martin Mienkina, Quyen Pho, Avni Arora
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Patent number: 12323164Abstract: A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.Type: GrantFiled: July 31, 2023Date of Patent: June 3, 2025Assignee: Astera Labs, Inc.Inventors: Enrique Musoll, Anh T. Tran, Subbarao Arumilli, Chi Feng
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Patent number: 12316454Abstract: A retransmission method in a communication system, wherein the communication system comprises at least one transmitter and at least one receiver with a communication channel between the transmitter and the receiver, the method comprising: utilising in the transmitter a transmitter algorithm with trainable weights and in the receiver a receiver algorithm with trainable weights; generating (302) by the transmitter symbols to be transmitted based on a message to be sent and feedback received from the receiver and transmitting the symbols; generating (304) by the receiver a predicted message based on the received symbols, evaluating (306) the predicted message based on a criterion and providing (312), utilising an algorithm with trainable weights, feedback symbols as a response to the transmitter if the evaluation indicates the predicted message is not acceptable.Type: GrantFiled: October 31, 2019Date of Patent: May 27, 2025Assignee: Nokia Technologies OyInventors: Mathieu Goutay, Faycal Ait Aoudia, Jakob Hoydis
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Patent number: 12316342Abstract: A processing circuit implements: an encoder configured to: supply k symbols of original data to a neural product encoder including M neural encoder stages, a j-th neural encoder stage including a j-th neural network configured by j-th parameters to implement an (nj,kj) error correction code (ECC), where nj is a factor of n and kj is a factor of k; and output n symbols representing the k symbols of original data encoded by an error correcting code; or a decoder configured to supply n symbols of a received message to a neural product decoder including neural decoder stages grouped into a l pipeline stages, an i-th pipeline stage of the neural product decoder including M neural decoder stages, a j-th neural decoder stage comprising a j-th neural network configured by j-th parameters to implement an (nj,kj) ECC; and output k symbols decoded from the n symbols of the received message.Type: GrantFiled: September 9, 2022Date of Patent: May 27, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Mohammad Vahid Jamali, Hamid Saber, Homayoon Hatami, Jung Hyun Bae
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Patent number: 12287706Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.Type: GrantFiled: June 23, 2023Date of Patent: April 29, 2025Inventors: Scott E. Schaefer, Aaron P. Boehm
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Patent number: 12283973Abstract: Methods and apparatus for constructing polar codes are provided. A transmitter determines at least one set of parameters corresponding to data to be transmitted, and a set of sorting indices corresponding to bits of the data to be transmitted based on the set of parameters, the set of sorting indices indicating a position set of the bits to be transmitted. The transmitter polar encodes the data based at least on the set of parameters and the set of sorting indices to generate a coded block of the data, and transmits the coded block of the data.Type: GrantFiled: September 6, 2023Date of Patent: April 22, 2025Assignee: QUALCOMM IncorporatedInventors: Changlong Xu, Jian Li, Jilei Hou, Chao Wei
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Patent number: 12283307Abstract: A storage device includes a memory including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, and a controller configured to control the memory and perform a read retry operation for the memory using a read retry table. The memory includes a special block that stores a read retry table in which a plurality of read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions.Type: GrantFiled: December 7, 2022Date of Patent: April 22, 2025Assignee: SK hynix Inc.Inventors: Jae Yong Son, Nam Kyeong Kim, Hoon Cho, Hyuk Min Kwon, Dae Sung Kim, Jang Seob Kim, Sang Ho Yun
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Patent number: 12277027Abstract: Provided is a memory access control unit that performs writing by dividing write data and an error correction code thereof into a plurality of memories, and acquires presence or absence of occurrence of a verify error in each of the plurality of memories related to the writing. In a case where the verify errors occur in at least any of the plurality of memories, an error bit length acquisition unit acquires bit lengths of the verify errors from the plurality of memories and a write control unit determines that the writing has succeeded if a total bit length of the verify errors falls within a range of a capability allocated to an error bit length tolerance of the error correction code, and determines that the writing has failed if the total bit length of the verify errors falls outside the range.Type: GrantFiled: August 23, 2021Date of Patent: April 15, 2025Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Ken Ishii, Haruhiko Terada, Riichi Nishino
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Patent number: 12271784Abstract: A quantum measurement circuit implements a hypergraph product code (HPG). A syndrome can be extracted from the circuit by preparing a readout qubit of the quantum measurement circuit in a known state, preparing a row-based measurement gadget, and preparing a column-based measurement gadget in the quantum measurement circuit. The row-based measurement gadget entangles the readout qubit with a first subset of the target set of data qubits in a same row of the quantum measurement circuit as the readout qubit, and the column based gadget entangles the readout qubit with a second subset of the target set of data qubits in a same column of the quantum measurement circuit as the readout qubit. The syndrome is extracted by measuring the readout qubit to extract the parity of the target set of data qubits.Type: GrantFiled: March 31, 2021Date of Patent: April 8, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Nicolas Guillaume Delfosse, Maxime Tremblay, Michael Edward Beverland
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Patent number: 12267165Abstract: Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.Type: GrantFiled: April 25, 2024Date of Patent: April 1, 2025Assignee: InterDigital Patent Holdings, Inc.Inventors: Chunxuan Ye, Fengjun Xi, Sungkwon Hong, Kyle Jung-Lin Pan, Robert L. Olesen
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Patent number: 12249376Abstract: A storage device, including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array including a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes, and a word-line cut region dividing the plurality of word-lines into a plurality of memory blocks. The storage controller groups a plurality of target memory cells into outer cells and inner cells. The storage controller includes an error correction code (ECC) decoder configured to perform an ECC decoding operation by obtaining outer cell bits and inner cell bits during a read operation on the plurality of target memory cells, and applying different log likelihood ratio (LLR) values to the outer cell bits and the inner cell bits.Type: GrantFiled: May 20, 2022Date of Patent: March 11, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun Chu Oh, Junyeong Seok, Younggul Song, Byungchul Jang
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Patent number: 12236992Abstract: A system includes a memory array having pattern cells and data cells. The pattern cells are configured to store only a first logic state. The data cells are configured to store the first logic state or a second logic state. Bias circuitry is configured to apply voltages to the pattern cells and data cells. Sensing circuitry is configured to read the pattern cells. A controller is configured to apply, using the bias circuitry, first voltages to the pattern cells; determine, using the sensing circuitry, that at least a portion of the pattern cells switch; determine, based on the portion of the pattern cells that switch, to refresh a codeword; and apply, using the bias circuitry, the refresh of the codeword.Type: GrantFiled: June 28, 2022Date of Patent: February 25, 2025Assignee: Micron Technology, Inc.Inventors: Umberto di Vincenzo, Ferdinando Bedeschi, Christian Marc Benoit Caillat
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Patent number: 12224768Abstract: An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.Type: GrantFiled: July 3, 2023Date of Patent: February 11, 2025Assignee: ETRON TECHNOLOGY, INC.Inventors: Ho-Yin Chen, Han-Hsien Wang, Han-Nung Yeh
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Patent number: 12222800Abstract: A technique for writing data to pages in a QLC block of a QLC NAND flash memory device, where the device comprises a plurality of SLC pages organized in SLC blocks and a plurality of QLC pages organized in QLC blocks. The technique comprises storing received data in SLC pages, dividing equally a QLC block in a predefined number of sub-blocks according to a corresponding QLC page health status of the pages of the QLC block. Upon determining that SLC pages are to be copied from SLC pages to QLC pages, copying device-internal the respective SLC pages to the sub-blocks of the QLC block using device-internal cache registers, where the copying is based on an error-count aware scheme.Type: GrantFiled: July 7, 2023Date of Patent: February 11, 2025Assignee: International Business Machines CorporationInventors: Nikolaos Papandreou, Timothy J. Fisher, Roman Alexander Pletka, Charalampos Pozidis, Radu Ioan Stoica, Aaron Daniel Fry, Andrew D. Walls
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Patent number: 12218684Abstract: The present invention relates to a layered semi-parallel LDPC decoder system having a single permutation network, and belongs to the field of decoder hardware design. The system comprises a layered decoding architecture of the single permutation network, a layered semi-parallel decoding architecture of the single permutation network, a pipeline design for layered semi-parallel decoding and a hardware framework of a layered semi-parallel LDPC decoder. The present invention removes a permutation network module between a check node and a variable node by modifying the cyclic shift value of each information block transferred from the variable node to the check node, i.e., the cyclic shift operation of the decoder can be completed through the single permutation network so as to reduce hardware resources of the decoder. A semi-parallel decoding structure is adopted, and meanwhile, a pipeline is added between half layers.Type: GrantFiled: November 15, 2021Date of Patent: February 4, 2025Assignee: Chongqing University Of Posts And TelecommunicationsInventors: Hongsheng Zhang, Taiyun Ding, Ting Liu, Hong Yang, Yi Huang, Weizhong Chen, Qi Wang, Xi Wang
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Patent number: 12216542Abstract: Providing for increased flexibility for large scale parity, the including: writing data to a storage system, including utilizing a first data protection scheme; identifying, for storage media in the storage system, characteristics of the storage media; identifying, in dependence up the characteristics for the storage media, a second data protection scheme to use for the data; and writing the data to the to the storage system utilizing the second data protection scheme.Type: GrantFiled: December 6, 2023Date of Patent: February 4, 2025Assignee: PURE STORAGE, INC.Inventors: Ethan Miller, Robert Lee, Par Botes, Ronald Karr
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Patent number: 12212339Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.Type: GrantFiled: November 10, 2022Date of Patent: January 28, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myungkyu Lee, Kijun Lee, Sunghye Cho, Sungrae Kim
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Patent number: 12206496Abstract: For example, an apparatus may include an encoder configured to encode data into a plurality of codewords according to a parity function for a transmission modulated according to a Differential Modulation (DM) scheme, and/or a decoder to decode received codewords of the transmission.Type: GrantFiled: June 23, 2021Date of Patent: January 21, 2025Assignee: INTEL CORPORATIONInventors: Elan Banin, Lior Menashe, Eytan Mann, Ofir Degani, Rotem Banin
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Patent number: 12206497Abstract: Methods and systems for two-dimensional (2D) coding are described for broadcast, multicast or groupcast applications. Two or more information code blocks (CBs) are transmitted to a plurality of intended receiving nodes. One or more cross-CB check blocks are generated, each cross-CB check block being generated based on a set of cross-CB bits, the set of cross-CB bits including at least one bit selected from each of at least two of the information CBs. At least one cross-CB check block is transmitted to at least one of the intended receiving nodes.Type: GrantFiled: July 6, 2021Date of Patent: January 21, 2025Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yu Cao, Ming Jia, Jianglei Ma
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Patent number: 12197372Abstract: A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device. A method for network recording is disclosed.Type: GrantFiled: January 26, 2022Date of Patent: January 14, 2025Assignee: Endace Technology LimitedInventors: Anthony Coddington, Stephen Frank Donnelly, David William Earl, Maxwell John Allen, Stuart Wilson, William Brier
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Patent number: 12191980Abstract: Methods, systems, and devices for generating preamble sequences where several Zadoff-Chu (ZC) sequences are generated based on multiple roots and multiple cyclic shifts per root and combined to generate the preamble sequences. Some embodiments may be used in wireless communication embodiments in which large propagation delays and/or Doppler movement are expected.Type: GrantFiled: August 16, 2021Date of Patent: January 7, 2025Assignee: ZTE CorporationInventors: Chenchen Zhang, Wei Cao, Zhen Yang, Kaibo Tian, Nan Zhang
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Patent number: 12175363Abstract: A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.Type: GrantFiled: November 5, 2020Date of Patent: December 24, 2024Assignee: Microchip Technology Inc.Inventors: Lorenzo Zuolo, Rino Micheloni
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Patent number: 12174696Abstract: A storage device is disclosed. The storage device may include storage for data. A controller may manage writing the data to the storage and reading the data from the storage. A data quality metric table may map a first number of errors to a first data quality metric and map a second number of errors to a second data quality metric. A transmitter may return the data quality metric table to a host.Type: GrantFiled: February 6, 2023Date of Patent: December 24, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Rekha Pitchumani, Zongwang Li
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Patent number: 12164376Abstract: Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.Type: GrantFiled: December 29, 2022Date of Patent: December 10, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Eunhye Oh, Taewook Park, Jisu Kang, Yongki Lee
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Patent number: 12158825Abstract: Mirrored pairs in a RAID-1 are distributed in a balanced and deterministic way that increases data access parallelism. For a group of k+1 disks that can be represented as a matrix of disk rows indexed 0 through k, where each disk is organized into k same-size subdivisions, in columns indexed 1 through k, corresponding mirrors of data members on the first disk (row index 0) are distributed across all other disks along a matrix diagonal such that the row index is the same as the column index for each mirror. Additional mirror pairs are created and symmetrically distributed in two submatrix triangles that are defined and separated by the diagonal. The two triangles are populated with symmetrically distributed mirrors that are flipped around the matrix diagonal such that for any mirror data in one triangle, its corresponding mirror data can be found in the other triangle by swapping the row and column indices.Type: GrantFiled: May 31, 2022Date of Patent: December 3, 2024Assignee: Dell Products L.P.Inventor: Kuolin Hua
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Patent number: 12159437Abstract: Disclosed are a partitioning method, an encoder, a decoder and a computer storage medium. The method includes: determining location information of a point of a point cloud to be partitioned; when i is less than or equal to M?1, determining right-shift number Ni of ith LOD layer in the point cloud, M representing a preset maximum quantity of layers for LOD partitioning; for the ith LOD layer, shifting location information of the point rightwards by Ni-digit, performing storing in a preset storage area based on right-shifted location information; determining location information of a parent point corresponding to a current point in the ith LOD layer; according to determined location information of the parent point, searching the preset storage area for a neighbor point of the parent point; partitioning the current point into an (i+1)th LOD layer, or the neighbor point into the ith LOD layer.Type: GrantFiled: July 1, 2022Date of Patent: December 3, 2024Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.Inventors: Fuzheng Yang, Zexing Sun, Lihui Yang, Shuai Wan
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Patent number: 12158853Abstract: A method for data access control among multiple nodes and a data access system are provided. The data access system includes a data interconnect controller circuit that allocates resources of one or more slaves by one or more masters according to operating parameters of an interleaver, and includes an intelligent control module that collects use efficiency data of the one or more slaves and obtains a current setting of the data interconnect controller circuit via a monitor. The monitor calculates scores of use efficiency data. The scores and the setting are inputted to a neural network model. Parameters of the neural network model are adjusted according to the scores, and a new setting generated by the neural network model is applied to the interleaver of the data interconnect controller circuit, so that the data interconnect controller circuit performs access control among the multiple nodes with the new setting.Type: GrantFiled: May 30, 2023Date of Patent: December 3, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Yu-Hsuan Hung, Wei-Hao Fang, Kai-Ting Shr
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Patent number: 12160311Abstract: According to one or more embodiments, a network node for communicating with at least one radio unit is provided. The network node including processing circuitry configured to: determine at least one code frame characteristic of a non-linear grid, map in-phase and quadrature, I/Q, data to non-linear grid having a plurality of regions that correspond to a plurality of code words where a plurality of bit sizes of the plurality of code words is a function of a radial distance from an origin of the non-linear grid, select a subset of the plurality of code words based at least in part on a target data rate for transmission, and cause transmission of the I/Q data based at least in part on the selected subset of the plurality of code words.Type: GrantFiled: October 9, 2019Date of Patent: December 3, 2024Assignee: Telefonaktiebolaget LM Ericsson (Publ)Inventors: Glen Rempel, Joleen Hind, Viktor Ackovik
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Patent number: 12142335Abstract: Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.Type: GrantFiled: December 13, 2022Date of Patent: November 12, 2024Assignee: Micron Technology, Inc.Inventors: Steffen Buch, Melissa I. Uribe
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Patent number: 12142333Abstract: An apparatus having memory cells, an error correction module with a predetermined code rate, a processing device configured to arrange data storage in the memory cells for improved capability in recovering from random bit errors in raw data retrieved from the memory cells. For example, user data and redundant data are stored in the memory cells. The redundant data is generated according to the predetermined code rate from not only the user data but also known data. The known data is not stored in the memory cells. As a result, the error correction module has increased capability in recovering from random bit errors in raw data retrieved from the memory cells. The increased capability can be used to extend the useful life of the memory cells and/or improve the reliability of retrieving error free data from the memory cells.Type: GrantFiled: April 4, 2022Date of Patent: November 12, 2024Assignee: Micron Technology, Inc.Inventors: Mustafa N. Kaynak, Kishore Kumar Muchherla
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Patent number: 12141441Abstract: A data storage device in accordance with an embodiment may include a controller and a memory device. The controller is configured to output a read control signal including an option number related to a read condition. The memory device is configured to perform a read operation based on a read condition corresponding to the option number in response to the read control signal. The read condition for the option number is configured to be stored in a read condition table storage circuit included in the memory device.Type: GrantFiled: December 20, 2022Date of Patent: November 12, 2024Assignee: SK hynix Inc.Inventor: Tae Kyu Ryu
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Patent number: 12135610Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correctionType: GrantFiled: September 23, 2021Date of Patent: November 5, 2024Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Christophe Laurent, Riccardo Muzzetto
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Patent number: 12132503Abstract: A deployment of radiologic beacons detect radiation levels for emitted radiation around a particular geographic area such as a town, city or campus environment. In a deployment of beacons for detecting and gathering radiological gamma-ray spectral data, each beacon periodically generates a set of values indicative of radiation at a particular energy level, and assembles a vector of the set of values ordered according to increasing energy levels. Each of the beacons transmits the vector as a stream or periodic sequence of data to a common aggregation location. Each beacon encodes the data according to a compression mechanism based on a Poisson distribution of the spectral data. A running average of the values for each energy level is maintained for the sequence of vectors, and encoding/decoding mechanisms are selected based on the average value to be encoded.Type: GrantFiled: February 1, 2021Date of Patent: October 29, 2024Assignee: Two Six Labs, LLCInventor: Jeremy W. Trimble
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Patent number: 12119841Abstract: a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.Type: GrantFiled: April 28, 2023Date of Patent: October 15, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Yeol Yang, Bohwan Jun, Hong Rak Son, Geunyeong Yu, Youngjun Hwang
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Patent number: 12111807Abstract: In some examples, a computer system may receive a plurality of chunks of data of a data object. The system may compress the plurality of chunks of data to obtain a plurality of compressed chunks, and may determine whether the plurality of compressed chunks together are less than a threshold size. Based on determining that the plurality of compressed chunks together are less than the threshold size, the system may add, to respective entries in a map data structure, respective sizes of the plurality of compressed chunks. In addition, the system may compact the map data structure by combining values in at least two of the respective entries, and may store the plurality of compressed chunks and the compacted map data structure.Type: GrantFiled: April 29, 2019Date of Patent: October 8, 2024Assignee: HITACHI VANTARA LLCInventor: Ronald Ray Trimble
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Patent number: 12111729Abstract: A system, method, and product for flexible RAID layouts in a storage system, including: determining a reliability of an individual storage device of a plurality of storage devices, the individual storage device containing a plurality of portions of a Redundant Array of Independent Disks (RAID) stripe in a storage system, wherein the RAID stripe includes user data and inter-device parity data; detecting a change in the reliability of the individual storage device that contains the portion corresponding to the RAID stripe; and changing an amount of intra-device protection corresponding to the RAID stripe by decreasing, in the RAID stripe, an amount of space used to store the inter-device protection data.Type: GrantFiled: October 18, 2023Date of Patent: October 8, 2024Assignee: PURE STORAGE, INC.Inventors: John Colgrove, John Hayes, Bo Hong, Ethan Miller
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Patent number: 12095599Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a network entity may transmit, to a user equipment (UE), an indication of a multi-level coding scheme that specifies a first encoding algorithm associated with level 1 coding and a second encoding algorithm associated with level 2 coding based at least in part on power management. The network entity may communicate with the UE based at least in part on the multi-level coding scheme. Numerous other aspects are described.Type: GrantFiled: May 17, 2022Date of Patent: September 17, 2024Assignee: QUALCOMM IncorporatedInventors: Ronen Shaked, Yaniv Eistein
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Patent number: 12081333Abstract: Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.Type: GrantFiled: December 2, 2022Date of Patent: September 3, 2024Assignee: QUALCOMM IncorporatedInventors: Jian Li, Changlong Xu, Chao Wei, Jilei Hou
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Patent number: 12081240Abstract: A method and apparatus for transmitting a streaming media with Forward Error Correction (FEC). Upon receiving the streaming media, the technique includes: encoding, segmenting and packeting frames comprised therein to generate a packetized elementary stream of media packets with variable sizes; for each L sequential media packets, calculating a “random loss” (RL) FEC parity and generating a respective RL FEC packet associated therewith; calculating “burst loss” (BL) FEC parities in accordance with a predefined FEC scheme and generating respective BL FEC structures bearing FEC headers and usable for generating BL FEC packets; calculating size-related parameters of a group of sequential media packets, the group being selected in accordance with the FEC scheme; and, transmitting the packetized elementary stream with interleaved FEC packets. The BL FEC packets are transmitted merely when the calculated size-related parameters meet a size-related burst loss (SRB) criterion defined by the FEC scheme.Type: GrantFiled: April 13, 2022Date of Patent: September 3, 2024Assignee: MARIS—TECH LTDInventor: Magenya Roshanski