Abstract: Systems and methods include receiving blocks of data that has been Forward Error Correction (FEC) encoded via Open Forward Error Correction (OFEC) adaptation; decoding the blocks of data; processing Cyclic Redundancy Check (CRC) data that is included in padding data required in the OFEC adaptation, wherein the padding data is distributed across N rows of payload data; and determining a location of any errors in the payload data based on the processed CRC data. The OFEC adaptation is for mapping the blocks of data into any of a FlexO-x frame structure, a ZR frame structure, and variants thereof, and the location of any errors can be used for error marking.

Abstract: A decoder decodes a soft information input vector represented by an input vector that is binary and that is constructed from the soft information input vector. The decoder stores even parity error vectors that are binary and odd parity error vectors that are binary for L least reliable bits (LRBs) of the input vector. The decoder computes a parity check of the input vector, and selects as error vectors either the even parity error vectors or the odd parity error vectors based at least in part on the parity check. The decoder hard decodes test vectors, representing respective sums of the input vector and respective ones of the error vectors, based on the L LRBs, to produce codewords that are binary for corresponding ones of the test vectors, and metrics associated with the codewords. The decoder updates the soft information input vector based on the codewords and the metrics.

Abstract: Methods and apparatus to dynamically assign and relocate object fragments in distributed storage systems are disclosed.

Abstract: The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.

Abstract: One embodiment facilitates data placement in a storage device. During operation, the system receives a request indicating first data to be written to a non-volatile memory which includes a plurality of dies, wherein a plurality of error correction code (ECC) codec modules reside on the non-volatile memory. The system receives, by a first codec module residing on a first die, the first data. The system encodes, by the first codec module operating on the first die, the first data based on an error correction code (ECC) to obtain first ECC-encoded data which includes a first set of ECC parity bits. The system writes the first ECC-encoded data to the first die.

Abstract: There is provided a method of sequential list decoding of an error correction code (ECC) utilizing a decoder comprising a plurality of processors. The method comprises: a) obtaining an ordered sequence of constituent codes usable for the sequential decoding of the ECC; b) executing, by a first processor, a task of decoding a first constituent code, the executing comprising: a. generating decoding candidate words (DCWs) usable to be selected for decoding a subsequent constituent code, each DCW associated with a ranking; b. for the first constituent code, upon occurrence of a sufficiency criterion, and prior to completion of the generating all DCWs and rankings, selecting, in accordance with a selection criterion, at least one DCW; c) executing, by a second processor, a task of decoding a subsequent constituent code, the executing comprising processing data derived from the selected DCWs to generate data usable for decoding a next subsequent constituent code.

Abstract: Systems, apparatuses and methods may provide for technology to receive a codeword containing an SC-LDPC code and conduct a min-sum decode of the SC-LDPC code based on a plurality of scaling factors. In an embodiment, the scaling factors are non-uniform across check nodes and multiple iterations of the min-sum decode.

Abstract: The present invention relates to a method and a device for a terminal transmitting/receiving data in a wireless communication system. According to the present invention, a method and a device may be provided by which a first message comprising first control information is received from a base station, wherein the first control information comprises a logical path identifier (ID) indicating a logical path for transmitting/receiving first data and second data, which is the same as the first data; as a response to the first message, a reply message is transmitted to the base station; and the first data and the second data are transmitted, to the base station, on multiple component carriers (CC) associated with the logical path corresponding to the logical path ID.

Abstract: An origination device (e.g., a base station) dual encodes a first set of data (1) according to a first set of encoding parameters corresponding to channel conditions associated with a first communication link, and (2) according to a second set of encoding parameters corresponding to channel conditions associated with a second communication link. The dual-encoded first set of data is transmitted to a signal forwarding device. The signal forwarding device decodes the dual-encoded first set of data, using decoding parameters that correspond to the second set of encoding parameters, to generate a single-encoded first set of data that is encoded according to the first set of encoding parameters. The signal forwarding device transmits a “single-encoded forwarded signal” to the destination device. The destination device decodes the single-encoded forwarded signal using decoding parameters that correspond to the first set of encoding parameters, which yields the first set of data.

Abstract: A sensor apparatus includes a sensing means having one or more sensors. A processor unit processes data received from the one or more sensors. The processor unit has a processor, a memory which stores data used by the processor, and a memory controller that receives instructions from the processor and in response writes data output from the processor to the memory or retrieves data from the memory to the processor. The memory controller is configured to read and write data to one or more areas of the memory with ECC protection of the data and arranged to read and write data to one or more areas of the memory without applying any ECC protection. The sensor apparatus may be configured to process data captured from an antenna to identify the position and/or the range of at least one target in the line of sight of the antenna.

Abstract: Disclosed are a method and an apparatus for fast decoding a linear code based on soft decision. The method may comprise sorting received signals in a magnitude order to obtain sorted signals; obtaining hard decision signals by performing hard decision on the sorted signals; obtaining upper signals corresponding to MRBs from the hard decision signals; obtaining a permuted and corrected codeword candidate using the upper signals and an error vector according to a current order; calculating a cost for the current order using a cost function; determining the permuted and corrected codeword candidate as a permuted and corrected codeword according to a result of comparing the calculated cost with a minimum cost; and determining a predefined speeding condition.

Abstract: Embodiments of this application disclose a data processing method and a data processing device. The method includes: obtaining a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a transport block or a code block generated by performing code block segmentation on a transport block; encoding the first to-be-processed bit sequence to obtain a first encoded bit sequence; storing all or at least some bits of the first encoded bit sequence into a circular buffer; and outputting a first output bit sequence from the bits stored in the circular buffer. According to the method and the device that are provided in this application, rate matching can be implemented for a sequence generated through LDPC encoding.

Abstract: An embodiment may involve executing a set of instructions, where the set of instructions define how to generate outputs that represent one or more data packets, and where segments of the outputs are copied from first parts of respective instructions in the set of instructions. The embodiment may further involve: retrieving, from a plurality of registers, a data packet header; retrieving, from the plurality of registers, a first part of a data packet payload and an increment value; applying the increment value to the first part of the data packet payload to generate a second part of the data packet payload; storing, in the plurality of registers, the first part of the data packet payload with the increment value applied; and providing, as additional segments of the outputs, the data packet header, the first part of the data packet payload, and the second part of the data packet payload.

Abstract: This application provides a channel encoding method and apparatus in wireless communications. The method includes: performing CRC encoding on A to-be-encoded information bits, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and A information bits; performing a interleaving operation on the first bit sequence, to obtain a second bit sequence, where a first interleaving sequence used for the interleaving operation is obtained based on a system-supported maximum-length interleaving sequence with the length of Kmax+L, and Kmax is a maximum information bit quantity corresponding to the maximum-length interleaving sequence ad a preset rule, and a length of the first interleaving sequence is equal to A+L. Therefore, during distributed CRC encoding, when an information bit quantity is less than the maximum information bit quantity, an interleaving sequence required for completing an interleaving process is obtained based on the system-supported maximum-length interleaving sequence.

Abstract: In a coding device (20), a first coding unit (21) generates a parity of an RS code by coding, based on the RS code, each first data sequence existing in a direction different from a row direction of input data, and generates coded data by attaching the parity of the RS code to each first data sequence, thereby consequently expanding a matrix. A second coding unit (22) generates a parity of a BCH code and a parity of an LDPC code by coding, based on the BCH code and the LDPC code, each second data sequence existing in a row direction of the coded data, and generates a plurality of DVB-S2 frames (13) including, per DVB-S2 frame (13), one data sequence existing in the row direction of the coded data, the corresponding parity of the BCH code, and the corresponding parity of the LDPC code.

Abstract: Techniques are described for improving the decoding latency and throughput of an error correction system that includes a bit flipping (BF) decoder, where the BF decoder uses a bit flipping procedure. In an example, different decoding parameters are determined including any of a decoding number of a decoding iteration, a checksum of a codeword, a degree of a variable node, and a bit flipping threshold defined for the bit flipping procedure. Based on one or more of these decoding parameters, a decision can be generated to skip the bit flipping decoding procedure, thereby decreasing the decoding latency and increasing the decoding throughput. Otherwise, the bit flipping decoding procedure can be performed to compute a bit flipping energy and determine whether particular bits are to be flipped or not. Hence, the overall performance (e.g., bit error rate) is not significantly impacted.

Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a currant value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Abstract: This application provides a data transmission method, a base station, and a terminal device. The method includes: determining, by a base station, a target base graph in N Raptor-like low-density parity-check (LDPC) base graphs; and sending, by the base station, indication information to a terminal device, where the indication information is used to indicate the terminal device to use the target base graph to perform LDPC encoding and decoding. Based on the foregoing technical solution, the base station may determine a target base graph in a plurality of Raptor-like LDPC base graphs that may be used to perform LDPC encoding and decoding, and indicate the target base graph to the terminal device. Further, for one code rate or one code length, the base station may select different base graphs as required.

Abstract: A polar code encoding method and apparatus are provided. The method includes: obtaining a basic sequence, where the basic sequence is a sequence obtained by sorting sequence numbers of polarized channels in descending order or ascending order of reliability, and a length of the basic sequence is L1; determining, based on a maximum encoding length L2 supported by a receiving device, a quantity M of segments of an information bit sequence whose length is N after encoding, where a quantity of bits in the information bit sequence before the encoding is K; and performing polar code encoding on the M segments based on the basic sequence. According to the polar code encoding method, during polar code construction, an encoding device needs to know only a reliability order of min(N/M, L1) polarized channels. In this way, storage overheads of a nested sequence can be effectively reduced, and online computing complexity can be reduced.

Abstract: The disclosure provides a data processing device and method. The data processing device may include: a task configuration information storage unit and a task queue configuration unit. The task configuration information storage unit is configured to store configuration information of tasks. The task queue configuration unit is configured to configure a task queue according to the configuration information stored in the task configuration information storage unit. According to the disclosure, a task queue may be configured according to the configuration information.

Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.

Abstract: This application discloses an encoding method, an apparatus, a communications device, and a communications system. The method includes: encoding an input bit sequence by using a low density parity check LDPC matrix, where the LDPC matrix is obtained based on a lifting factor Z and a base matrix, and the base matrix includes a row 0 to a row 4 and a column 0 to a column 26 in one of matrices shown in FIG. 3b-1A to FIG. 3b-8B, or the base matrix includes a row 0 to a row 4 and some of a column 0 to a column 26 in one of matrices shown in FIG. 3b-1A to FIG. 3b-8B. According to the encoding method, the apparatus, the communications device, and the communications system, channel coding requirements can be met.

Abstract: An error correction circuit using a BCH code may include a decoder performing at least one of a first error correction decoding using a first error correction capability or a second error correction decoding using a second error correction capability and an encoder generating a codeword based on a message and a generation matrix corresponding to the first error correction capability and generating an additional parity based on the codeword and one or more rows of a parity check matrix corresponding to the second error correction capability, wherein a syndrome vector generated based on a read vector corresponding to the codeword is used during the first error correction decoding and an additional syndrome generated based on the additional parity is used during the second error correction decoding, and wherein the one or more rows are extended from a parity check matrix corresponding to the first error correction capability.

Abstract: A method of operating a distributed storage system, the method includes identifying unhealthy chunks of a file. The file is divided into stripes that include data chunks and non-data chunks. The method also includes identifying healthy chunks available for reconstructing the unhealthy chunks and reconstructing unhealthy data chunks before reconstructing unhealthy non-data chunks using the available healthy chunks. When the unhealthy chunk is an unhealthy word-check chunk: reconstructing the unhealthy word-check chunk using healthy word-check chunks and healthy code-check-word-check chunks; determining whether reconstruction of the unhealthy word-check chunk is possible using only healthy word-check chunks and healthy code-check-word-check chunks; and when reconstruction of the unhealthy word-check chunk is not possible using only healthy word-check chunks and healthy code-check-word-check chunks, reconstructing the unhealthy word-check chunk using any healthy chunks.

Abstract: Memory controllers, decoders and methods to perform decoding of user bits and parity bits including those corresponding to low degree variable nodes. For each of the user bits, the decoder performs a variable node update operation and a check node update operation for connected check nodes. After all of the user bits are processed, the decoder performs a parity node update operation for the parity bits using results of the variable node and check node update operations performed on the user bits.

Abstract: This application provides a wireless communication method and device. The method includes: scrambling, with each piece of configuration information of a plurality of pieces of configuration information for configuring a terminal device, bits that are included in a cyclic redundancy check (CRC) of downlink control information (DCI) and that correspond to each piece of configuration information, to obtain a scrambled sequence, where at least one bit of bits that correspond to each piece of configuration information does not correspond to another piece of configuration information of the plurality of pieces of configuration information; and sending the DCI and the scrambled sequence to the terminal device.

Abstract: Technology for recovering data in memory dies is disclosed. A set of codewords may be stored across a set of memory dies. One of the memory dies stores redundancy information that is based on information from each codeword in the set of codewords. Each of the memory dies is bonded to control die through bond pads that allow communication between the control die and the memory die. If decoding of one of more codewords fails, the redundancy information may be used to recover data bits of all the codewords in the set. The redundancy information may be sent to a memory controller that is in communication with the control dies, which performs the data recovery.

Abstract: An information processing method, an apparatus, a communications device, and a communications system are provided. The communications device is configured to: obtain a starting position in a buffer sequence W for an output bit sequence, and determine the output bit sequence from the buffer sequence W based on the starting position, where a value of the starting position is one element in {p0, p1, p2, . . . , pkmax?1}, 0?k<kmax, 0?pk<NCB, pk is an integer, k is an integer, NCB is a length of the buffer sequence W, kmax is an integer greater than or equal to 4, and there are two or more different neighboring intervals in {p0, p1, p2, . . . , pkmax?1}. A bit sequence for initial transmission or retransmission is properly determined, so that decoding performance of a communications device on a receive end after receiving the bit sequence is improved, a decoding success rate is enhanced, and a quantity of retransmission times is further reduced.

Abstract: A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.

Abstract: Memory controllers, decoders and methods execute a hybrid decoding scheme with exchange of information between multiple decoders. A first type of decoder performs initial decoding of a codeword when an unsatisfied check (USC) count of the codeword is less than a threshold, and a second type of decoder performs decoding of a codeword when the USC count of the codeword is greater than or equal to the threshold. During decoding by one of the decoders, the controller generates information from an output of that decoder and send the information to the other decoder, which the other decoders uses in decoding. The codeword is routed and rerouted between the decoders, which may include a q-bit bit-flipping (q-BF) decoder and a min-sum (MS) decoder, based on conditions that occur during decoding.

Abstract: There are provided an error correction decoder and a memory system having the same. The error correction decoder includes a node processor for performing at least one iteration of an error correction decoding based on at least one parameter used for an iterative decoding, a reliability information generator for generating reliability information corresponding to a current iteration upon a determination that the error correction decoding corresponding to the current iteration has been unsuccessful, and a parameter adjuster for adjusting the at least one parameter upon a determination that the reliability information satisfies a predetermined condition, and controlling the node processor to perform a next iteration based on the adjusted.

Abstract: A system and method for implementing a distributed source coding quantization scheme is provided. In one example, two independent but statistically correlated data sources can be asymmetrically compressed so that one source is compressed at a higher ratio than the other. The resulting signals are transmitted and decoded by a receiver. The highly compressed source can utilize the non-highly compressed source as side information so as to minimize the compression loss associated with the higher compression ratio. A conditional codebook can be created that not only depends on the highly compressed quantizer, but also depends on the quantized symbol received from the non-highly compressed data source.

Abstract: A technique may include scheduling, by a base station, a block of data for transmission to a user device, transmitting, by a base station to a user device, a data packet that includes at least a portion of the block of data, estimating, by the base station, that a reception by the user device of the data packet will be subject to errors, and pro-actively retransmitting, by the base station based on the estimating, at least a portion of the block of data without waiting for feedback from the user device regarding the data packet.

Abstract: A method, system, and non-transitory computer-readable recording medium of decoding a signal are provided. The method includes receiving signal to be decoded, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining magnitudes of the LLRs; identifying K bits of the signal with smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords; and stopping after a first candidate codeword passes the CRC.

Abstract: The present disclosure provides an encoding method and an encoder for a (n, n(n?1), n?1) permutation group code in a communication modulation system, in which 2k k-length binary information sequences are mapped to 2k n-length permutation codeword signal points in a n-dimensional modulation constellation ?n. The constellation ?n with the coset characteristics is formed by selecting 2k n-length permutation codewords from n(n?1) permutation codewords of a code set Pn,xi of the (n, n(n?1), n?1) permutation group code based on coset partition. The constellation ?n is a coset code in which 2k1 cosets are included and each coset includes 2k2 permutation codewords, where k=k1+k2, and 2k?n(n?1). The present disclosure utilizes the coset characteristics to realize one-to-one correspondence mapping of the binary information sequence set to the permutation code constellation, so that the time complexity of executing the encoder is at most the linear complexity of the code length n.

Abstract: Disclosed herein is a denoising device including a deriving part configured to, when corrupted noise data corrupted due to noises is received from source data, derive an estimated loss which is estimated when each symbol within noise data is reconstructed to the source data based on a predefined noise occurrence probability, a processor to process training of a defined learning model by including parameters related with the reconstruction of the source data from the noise data based on context composed of a sequence of neighbored symbols based on each symbol within the noise data and pseudo-training data using the estimated loss corresponding to the context, and an output part to output reconstructed data in which each symbol within the noise data is reconstructed to a symbol of the source data through a denoiser formed based on a result of the training processing.

Abstract: A device for processing a broadcast signal, includes a tuner configured to receive the broadcast signal carrying a bootstrap prefixed to the beginning of a signal frame, the bootstrap including one or more bootstrap symbols, a last bootstrap symbol immediately followed by a preamble of the signal frame including bootstrap termination information, the bootstrap including first information for representing a structure of the preamble; a demodulator configured to demodulate the broadcast signal; a de-framer configured to de-frame the signal frame in the broadcast signal to output the preamble and PLP data, the preamble carrying Layer 1 (L1) signaling data for the signal frame; a signaling decoder configured to decode the L1 signaling data; and a decoder to decode the PLP data based on the L1 signaling data.

Abstract: A memory system includes a nonvolatile memory and a memory controller that encodes first XOR data generated by performing an exclusive OR operation on pieces of user data, wherein a value of each bit of the XOR data is generated by performing an exclusive OR operation on values of bits that are at one of a plurality of bit positions of a piece of user data, generates codewords by encoding the plurality of pieces of user data and the generated XOR data, respectively, and stores the codewords in the nonvolatile memory. The memory controller also performs a read operation by reading the codewords from the nonvolatile memory and decoding them. When the decoding of two or more of the codewords fails, the memory controller generates second XOR data, and corrects the value of one of the bits corresponding to a codeword whose decoding failed, based on the second XOR data.

Abstract: Systems and methods are disclosed herein for puncturing Polar-encoded bits. In some embodiments, a method of operation of a radio node that utilizes a Polar encoder comprising performing Polar encoding of a plurality of bits to provide a plurality of Polar-encoded code bits and puncturing the plurality of Polar-encoded code bits using a hybrid puncturing scheme to provide a plurality of rate-matched Polar-encoded code bits, wherein the hybrid puncturing scheme uses different puncturing patterns for different code rate regions.

Abstract: A technique for hybrid automatic repeat request (HARD) transmissions using low-density parity-check (LDPC) coding with self-decodable retransmissions is disclosed. Data is encoded using a low-density parity check code to obtain encoded data, where the encoded data includes core data and non-core data. The encoded data is then stored in a buffer for transmission. A plurality of redundancy versions of the encoded data is then transmitted, wherein all redundancy versions of encoded data include core data, and each of the transmitted redundancy versions of the encoded data includes at least a different subset of the core data. The core data may be reordered prior to obtaining at least one of the different subsets of core data. Each of the transmitted redundancy versions of the encoded data includes sufficient core data to permit self-decodability of the transmission at a receiver.

Abstract: A decoding method and device utilizing a flash channel characteristic and data storage system, wherein the method comprises: acquiring a probability density function curve diagram; determining a to-be-corrected data position according to the current situation of the probability density function curve diagram; transmitting the to-be-corrected data position to a low-density parity check module to perform an operation to correct the to-be-corrected value. The embodiment of the present invention considers the current situation of the probability density curve diagram when determining the to-be-corrected data position, namely, selects different solutions to determine the to-be-corrected data position on the basis of the current situation of the probability density function curve diagram, thus reducing the data transmitted to the low-density parity check module to perform an operation, and reducing operation workload and power consumption.

Abstract: Technology for a transmitter operable to perform data transmissions using low density parity check (LDPC) codes is disclosed. The transmitter can determine soft buffer information (Nsoft) for a receiver. The transmitter can determine a soft buffer partition per HARQ process (NIR) for the UE. The transmitter can obtain, for a transport block, a number of code block segments (C). The transmitter can select a shift size value (z). The transmitter can determine an amount of soft buffer available for the code block segments (Ncb) based on NIR, C, and z. The transmitter can encode the code block segments based on an LDPC coding scheme to obtain encoded parity bits. The transmitter can select a subset of the encoded parity bits based on the determined amount of soft buffer associated with the code block segments.

Abstract: A method for an ingress node to send packets to an egress node, the method comprising: sending a plurality of service packets over a first network path; and sending a supplemental packet comprising a plurality of hash values over a second network path, wherein the plurality of packet hash values are computed respectively from the plurality of service packets. A method for an egress node to receive packets from an ingress node, the method comprising: extracting a plurality of packet hashes from a supplemental packet received from a second network path; computing a plurality of packet hash values, each hash value computed from a corresponding service packet comprised in a plurality of service packets received over a first network path; and recovering a lost service packet that is identified by comparing the plurality of computed packet hash values with the plurality of extracted packet hash values.

Abstract: Embodiments of the present disclosure provide an encoding/decoding method, apparatus, and system. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present disclosure is applicable to various communication systems.

Abstract: A decoder can receive an indication that a portion of a codeword has been decoded during a decoding operation. The decoder can determine a group of candidate output values of the decoding operation for the portion of the codeword, and eliminate one or more candidate output values from the group of candidate output values based on a decoded check code for each of the group of candidate output values. In response to determining that all of the candidate output values have been eliminated from the group of candidate output values, the decoder can terminate the decoding operation.

Abstract: Systems and methods are provided for enabling H-ARQ communication between a base station and one or more wireless terminals. Methods for enabling incremental redundancy (IR) based H-ARQ, Chase based H-ARQ and Space-Time Code combining (STC) based H-ARQ between devices for down?link and up-link direction transmissions are provided in the form of an information element (IE) for use with a Normal MAP convention as currently accepted in the draft version standard of IEEE 802.16. In addition, embodiments of the invention provide a resource management scheme to protect a network from abuse of resources from a wireless terminal not registered with the network. Components of the down-link and up-link mapping components of a data frame transmitted from the base station to one or more wireless terminals included messages that are readable by all wireless terminals as well as some messages that are encrypted and only readable by wireless terminals that are authenticated as being registered with the network.

Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.

Abstract: A method includes: obtaining a first sequence corresponding to a basic code length N0; determining N to-be-encoded bits, where the N to-be-encoded bits include N2 fixed bits, and N is greater than the basic code length N0; extending the first sequence to obtain a second sequence; determining locations of the N2 fixed bits in the N to-be-encoded bits based on polar channel serial numbers indicated by first N2 elements in the second sequence; and performing polar encoding on the N to-be-encoded bits to obtain encoded bits. The locations of the fixed bits in the N to-be-encoded bits are determined based on the second sequence, and the second sequence is obtained by extending the first sequence corresponding to the basic code length N0.

Abstract: An electronic device and a method of operating the electronic device in a wireless communication system are provided. The method includes determining whether to perform a partial decoding or a normal decoding based on a channel quality; if partial decoding is performed, decoding partial data received by a transceiver from a second electronic device during a part one TTI; when the decoding of the partial data succeeds, performing at least one complementary decoding until a decoding success count reaches a decoding threshold; and when the decoding success count reaches the decoding threshold, outputting a decoding result for the at least one complementary decoding; and if normal decoding is performed, decoding all data of the one TTI and outputting a result. One of the at least one complementary decoding comprises decoding previous data, and additional data received by the transceiver during an additional part of the one TTI, after the previous data.