Abstract: Techniques for error detection involve injecting, to a switch of a storage system, information representing an error of at least one device to be tested of the system, such that the information representing the error is passed from an upstream port of the switch to a computing device connected with the switch, the switch being connected to the at least one device to be tested via a downstream port. The techniques further involve obtaining a handling result of the computing device on the information representing the error, and determining an error handling capability of the system at least partly by analyzing the handling result. Accordingly, slave storage devices of storage system nodes, connectors, the entire PCIe topology at the CPU level, and an NVMe bus can be tested, so that the entire logical path of the error handling can be tested, thereby improving performance and saving testing costs.

Abstract: A system-on-chip includes a memory, an error injection controller, an injection logic circuit, and an error detection circuit. The error injection controller is configured to generate and transmit error data, and at least one of read and write access requests associated with the memory to the injection logic circuit. The injection logic circuit is configured to access the memory based on at least one of the read and write access requests to execute at least one of read and write operations. The injection logic circuit is further configured to inject an error in at least one of first data and second data to generate at least one of erroneous first data and erroneous second data, respectively. The error detection circuit is configured to detect an error in at least one of the erroneous first data and the erroneous second data to generate an error signal.

Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.

Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

Abstract: The present disclosure relates to a memory device comprising a hybrid memory portion in turn comprising a main nonvolatile memory and an auxiliary nonvolatile memory, and a controller configured to store data information in the main nonvolatile memory. The controller of the present disclosure comprises a parity engine configured to accumulate temporary parity information in the auxiliary nonvolatile memory, the parity information being associated with the data information stored in the main nonvolatile memory; when the parity information accumulated in the auxiliary nonvolatile memory is complete, the parity engine is further configured to transfer the complete parity information from the auxiliary nonvolatile memory to the main nonvolatile memory. A related apparatus and a related method are also disclosed.

Abstract: Systems and methods for a wireless data protocol are disclosed. For example, a sending device may generate data packets to be sent to a receiving device. The sending device may also generate packet representations to append to the data packets. For example, for a given packet, a representation of two other packets may be generated, such as by utilizing an exclusive or logical operation, and added to the content portion of the given packet. These packets may be sent to the receiving device, which may utilize the packet representations to reconstruct lost packets.

Abstract: A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L<N, where L=N×Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.

Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.

Abstract: Techniques for decoding communications transmitted by a remote alarm panel over a communications network to a central monitoring station (CMS) are provided. A first signal from the remote alarm panel can be received by the CMS. The CMS can determine that the first signal cannot be decoded due to errors, missing data, or corrupted data in the first signal. The remote alarm panel can retransmit the signal. The CMS can analyze the first and second signals to determine if the first signal can be reconstructed based on information provided by the second signal. The first signal can subsequently be repaired and decoded, allowing the CMS to more quickly respond to the alarm condition provided in the first signal.

Abstract: A semiconductor device includes: a control signal generation unit configured to generate a second control signal having a cycle shorter than a first control signal in response to a clock signal and the first control signal; a cyclic redundancy check (CRC) control unit configured to perform a control to receive first and second data groups in response to the second control signal, and to output the first and second data groups with a time lag; and a CRC operation unit configured to perform a cyclic redundancy check on each of the first and second data groups sequentially output through the CRC control unit.

Abstract: An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.

Abstract: A terminal device is provided such that in a case that closed-loop UE transmit antenna selection is configured, a bit sequence is given by scrambling CRC parity bits with an RNTI and an antenna selection mask, in a case that the number of the CRC parity bits is a first value, a first transmit antenna port is given by a first antenna selection mask, and in a case that the number of the CRC parity bits is a second value, the first transmit antenna port is given by a second antenna selection mask that is different from the first antenna selection mask.

Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.

Abstract: Provided is a CRC calculation circuit capable of dealing with various types of generator polynomials with a simple configuration. A CRC calculation circuit (100) includes a generator polynomial register (110) configured to store polynomial data, and a plurality of CRC calculation units (120) connected in series and provided so as to correspond to the number of bits of input data. The CRC calculation units (120) each include a barrel shifter (121) configured to shift calculated data by one bit using the input data or output data from a pre-stage CRC calculation unit as the calculated data; an XOR circuit (122) configured to perform XOR calculation of the shifted data and the polynomial data; and a multiplexer (123) configured to select, based on the calculated data, the shifted data or calculation result data.

Abstract: In various embodiments, a method for determining an error vector in a data word is provided. The method includes determining the syndrome of the error vector, successively generating code words by cyclically interchanging one or more predefined code words, forming, for each code word generated, the sum of the syndrome supplemented with zeros to the data word length and the code word, and checking, for the code word, whether the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words, and determining the error vector as the sum of the syndrome and the code word for which the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words.

Abstract: An integrated circuit (IC) includes an encoder circuit. The encoder circuit includes an encoding input configured to receive an input message including one or more data symbols. Each data symbol has N bits and N is a positive integer. The encoder circuit includes an encoding unit configured to perform Reed-Solomon encoding to the one or more data symbols to generate one or more coding symbols. The Reed-Solomon encoding uses a Galois field having an order that is less than 2N. A coded message that includes the one or more data symbols and the one or more coding symbols is provided at an encoding output of the encoder circuit.

Abstract: A memory controller is a memory controller including an encoder that product-codes, with a linear code, data to be recorded in a memory section and a decoder that decodes product-coded data read out from the memory section. The encoder and the decoder share a parity generation circuit including a plurality of remainder calculating and retaining sections, each including a remainder calculation circuit by a generator polynomial and a retaining circuit that retains an output of the remainder calculation circuit.

Abstract: In a method for generating data units for transmission via a wireless network, a first signal field that includes formatting information for a data unit is generated, and a CRC field for the first signal field is generated according to a generator polynomial. Further, a second signal field that includes formatting information for the data unit is generated, and a CRC field for the second signal field is generated according to the generator polynomial. Further, the data unit is generated to include i) the CRC for the second signal field and ii) a preamble having a) the first signal field, b) the CRC for the first signal field, and c) the second signal field.

Abstract: Method for operating a network having a prescribable topology, wherein the topology contains a plurality of network devices which are connected to one another and interchange data via multiwire data lines connected to their data ports, wherein test messages are also sent to the data lines in order to check whether or not two data ports on two network devices have the connection between them via the interposed data line, characterized in that, in a prescribable time interval, the number of cyclic redundancy check (CRC) errors which have occurred and the number of data items transmitted in this time interval are ascertained on a data line between two data ports, and at least these two values are used to calculate an error rate which is a measure of the operability of the multiwire data line.

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

Abstract: Methods and apparatus, including computer program products, for scaling video delivery. A method includes, in a corporate network comprising at least a first server linked to a computing system having a video player, receiving an output of a chunked video protocol in the first server, sending the output from the first server via a multicast to a receiver and, in the receiver, processing the output to enable consumption by the video player.

Abstract: Circuitry for providing error check values for indicating errors in data portions within a data stream. The circuitry comprises error detecting code generation circuitry configured to apply an error detecting code algorithm to the data stream and to thereby generate and periodically update a multi-bit check value as the data stream is processed, each update of the multi-bit check value being indicative of the error detecting code generation circuitry receiving a further item of the data stream. An output for periodically outputting a fragment of the multi-bit check value from the error detecting code generation circuitry during the processing of the data stream, the fragments output each corresponding to a data portion of the data stream. Wherein each of the fragment of the multi-bit check value provides a value indicative of an error occurring either in the corresponding portion of the data stream or in an earlier portion of the data stream.

Abstract: An operating method of a data storage device includes performing an error correcting operation for first data and verifying the error correcting operation to determine whether one or more error decision bits determined as an error through the error correcting operation are actual error bits or normal bits, when a result of the error correcting operation is a pre-correction success.

Abstract: An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p?1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

Abstract: Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. In accordance with one aspect, embodiments are disclosed that facilitate assessing the probability of error bursts in receivers that include decision feedback equalizers (DFEs) and that perform non-contiguous mapping of received bits to frame bits. From this probability, calculation of a mean-time to false packet acceptance (MTTFPA) may be determined, and indication that a projected link MTTFPA is too low can be used to trigger an alert or invoke some safety mechanism. Associated operations may then be performed to ensure the link is prevented from being operated in an unsafe condition under which false packet acceptance may occur.

Abstract: Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed.

Abstract: A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue.

Abstract: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data.

Abstract: Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Abstract: Apparatus, system and method for encoding and decoding ancillary code for digital audio, where multiple encoding layers are merged. The merging allows a greater number of ancillary codes to be embedded into the encoding space, and further introduces efficiencies in the encoding process. Utilizing certain error correction techniques, the decoding of ancillary code may be improved and made more reliable.

Abstract: The present invention discloses a data error-detection system and the method thereof. The system includes an initializing module, an encoding module, a decoding module and a restoring module. The initializing module arranges the transmitting data in a 3D matrix to produce information data. The encoding module encodes the information data to produce checking data, and outputs encoding data which includes information data and checking data. The decoding module receives encoding data and detects information data according to the checking data to correct the information data and then produces 3D matrix receiving data. The restoring module produces receiving data according to the 3D matrix receiving data. Herewith, the effect of error-detection and correction of the data can be achieved.

Abstract: An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data decoder engine and the second sub-message from the second data decoder engine to yield an shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.

Abstract: In one embodiment, device for early stopping in turbo decoding includes a processor configured to receive a block of data to be decoded, compare hard decision bits resulting from decoding iterations and compare a minimum value of log likelihood ratio (LLR) of decoded bits against a threshold. The processor configured to match hard-decisions with previous iteration results. The processor may be configured to set an early stop rule after the matching hard-decisions with previous iteration results is matched. The processor may be configured to set an early stop rule when the minimum reliability of the output bits exceeds the threshold.

Abstract: Methods and apparatus for early stop algorithm of turbo decoding are disclosed. An example method comprises of combination of comparing of hard decisions of soft outputs of the current iteration and the previous iteration and comparing the minimum log likelihood results against a threshold. The decoding iteration is stopped once the hard decisions are matched and the minimum soft decoding result exceeds a threshold.

Abstract: The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.

Abstract: Improved strategies for a Cyclical Redundancy Check (CRC) are disclosed. A CRC check of a codeblock may be initiated by a CRC decoder before receiving all of the bits by a corresponding FEC encoder. Furthermore, an incremental CRC check with respect to the data packet without the need for requesting passed through data from higher layers.

Abstract: Disclosed are mobile communication devices and methods of a mobile communication device that determines that no response has been received within a predetermined period of time from a network to a transmission of an encoded data block in accordance with a commanded MCS. The device then determines an alternative MCS capable of coping better with variations in the radio environment with minimal damage or alteration than the commanded MCS and preemptively transmits the encoded data block in accordance with this more robust alternative MCS. In this way the mobile communication device does not continue failed attempts to transmit data in accordance with the commanded MCS. After the device receives notice of successful transmission of the encoded data block with the alternative MCS, the device will resume the use of the commanded MCS to transmit subsequent encoded data blocks.

Abstract: Systems and techniques for serial data stream operations are described. A described system includes a serial bus communicatively coupled with a memory structure to handle a serial data stream from or to the memory structure; generators configured to generate enablement signals that are associated with different bit-groups of the serial data stream, each of the enablement signals including pulses that are aligned with time-slots that are associated with a respective bit-group; logic elements configured to store internal states and produce output signals that are based on the serial data stream, the enablement signals, and the internal states, and circuitry configured to capture values. Each of the enablement signals enables a respective logic element to selectively change a respective internal state responsive to bit-values of a respective bit-group. Each of the captured values represents an output of a respective logic element that is responsive to all bit-values of a respective bit-group.

Abstract: A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code encoder can add input words to output register words, generating a feedback word, which can be supplied through a feedback loop that selectively transmits feedback words through weight arrays and intra-register adders, to the input of word registers. A controller can operate the cyclic code encoder in either an input mode or an output mode during which feedback words can be sequentially transmitted on the feedback loop and the states of the word registers can be updated and the final states of the word registers can be sequentially shifted out of the output word register as parity words.

Abstract: The present inventions are related to systems and methods for irregular decoding of regular codes in an LDPC decoder, and in particular to allocating decoding resources based in part on data quality.

Abstract: Forward error correction (FEC) m-bit symbol modulation. Any desired FEC, error correction code (ECC), and/or combination thereof generates coded bits for combination with either uncoded bits, separately generated coded bits, and/or combination thereof to generate a number of symbols that undergo mapping to a constellation whose respective constellation points have a mapping characterized by a maximum minimum intra-Euclidean distance between the respective constellation points thereby generating a sequence of discrete-valued modulation symbols. The sequence of discrete-valued modulation symbols may then undergo modulation of any of a number of different operations (e.g., digital to analog conversion [e.g., digital to analog converter (DAC)], scaling, frequency shifting, filtering, etc.) to generate a continuous time signal for transmission via a communication channel. Such a device operative to perform including such functionality, circuitry, capability, etc.

Abstract: Systems, methods, apparatus, and techniques are presented for processing a codeword. A Reed-Solomon mother codeword n symbols in length and having k check symbols is received, and the n symbols of the received Reed-Solomon mother codeword are separated into v Reed-Solomon daughter codewords, where v is a decomposition factor associated with the Reed-Solomon mother codeword. The v Reed-Solomon daughter codewords are processed in a respective set of v parallel processes to output v decoded codewords.

Abstract: A receiver for use in a wireless communications network capable of decoding encoded transmissions. The receiver comprises receive path circuitry for receiving and downconverting an incoming radio frequency (RF) signal to produce an encoded received signal; and a low-density parity check (LDPC) decoder associated with the receive path circuitry for decoding the encoded received signal. The LDPC decoder further comprises a memory for storing a parity check H matrix comprising R rows and C columns, where each element of the parity check H matrix comprises one of a shift value or a ?1 value; and a plurality of processing elements for performing LDPC layered decoding, wherein at least one processing element is operable to process in the same cycle a first row and a second row of the parity check H matrix.

Abstract: In one embodiment, a process determines a size of a video unit (e.g., frame) to transmit from a sender to a receiver across a communication channel for an associated video stream, and also determines an updated packet loss rate on the channel. In response, the process may dynamically determine both a number N of video data packets and a number M of forward error correction (FEC) packets to transmit for the video unit based on the size of the video unit, the updated packet loss rate on the channel, and an error resilience requirement for the video stream. In an illustrative embodiment, N and M are determined during transmission of the video stream through a look-up operation into a table indexed by the size of the video unit and the updated packet loss rate as co-indices, the co-indices co-indexing a pre-determined N and M pair.

Abstract: According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller configured to control data input and output to and from nonvolatile memories for channels. The encoding module configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories. The data controller configure to manage the encoded data in units of logical blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to planes of the same channel in each logical block.

Abstract: A method of identifying a parallel recovery plan for a data storage system comprises identifying base recovery plans for symbols of an erasure code implemented across a plurality of storage devices in a data storage system, generating a list of first recovery plans for a first symbol by manipulating the base recovery plans, and combining selected first recovery plans from the list to generate a set of parallel recovery plans to reconstruct a failed storage device.

Abstract: Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.

Abstract: A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code encoder can add input words to output register words, generating a feedback word, which can be supplied through a feedback loop that selectively transmits feedback words through weight arrays and intra-register adders, to the input of word registers. A controller can operate the cyclic code encoder in either an input mode or an output mode during which feedback words can be sequentially transmitted on the feedback loop and the states of the word registers can be updated and the final states of the word registers can be sequentially shifted out of the output word register as parity words.