Abstract: A method of determining an error detection code (EDC) on incoming data which includes a reserved bit field, comprising applying the incoming data to inputs of both an input data CRC (IDC) calculator and to an input data and reserved field CRC (IDRC) calculator, calculating the EDC on successive input data words and recursively updating the EDC in both the IDC and IDRC calculators, selecting a payload of the input data as a system output signal for all payload words, and subsequently selecting a output EDC word from the IDRC calculator in a time immediately following a final payload word which contains the reserved field.

Abstract: A data packet is transmitted by dividing it into sub-packets, for example by distributing successive bytes of the data packet to different sub-packets each containing at most p.sup.n -1 symbols, where p is a prime number, and transmitting the sub-packets along two or more respective paths. CRC checksums are added to the sub-packets, the checksum for each path being generated using a different and respective generator polynomial of degree b. These generator polynomials are selected so that, for arithmetic carried out modulo p, each polynomial has a respective factor of degree at least b-n+1, and the collection of polynomials which are each exactly divisible by all such factors constitutes a BCH code. As a result the system has advantageous properties in respect of error detection and implementation.

Abstract: Apparatus and methods for storing predefined information with error correcting code (ECC) in a direct access storage device are provided. Predetermined information is identified and loaded to an ECC generator for customer data to be read and written. The identified predetermined information includes an address for customer data to be read and written. The customer data is written and loaded in parallel to the ECC generator. Then the generated ECC that reflects the pre-loaded predetermined information is written at the end of the written customer data. The customer data and ECC is read and loaded in parallel to the ECC generator. Errors in the predetermined information that is not written to the disk surface, can be detected from the read ECC.

Abstract: An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

Abstract: An IDE controller having an IDE interface that includes a primary channel for transmitting primary data from a primary device and a secondary channel for transmitting secondary data from a secondary device; a primary CRC circuit for receiving the primary data, performing an operation on the primary data and generating primary CRC values; a secondary CRC circuit for receiving the secondary data, performing an operation on the secondary data and generating secondary CRC values, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; and a compare circuit for comparing the primary CRC values with the secondary CRC values and generating compare values.

Abstract: A method for handling different of types of data bit errors in a computer system. In one embodiment, the method comprises the step of storing a data line in a first storage location. The method also includes the step of retrieving the data line from the first storage location. Data bit errors in the data line are detected and the data line is marked as containing a data bit error and stored in a storage location if the data line is not to be used immediately by a requesting process; otherwise error handling is performed by halting the requesting process.

Abstract: An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

Abstract: A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle.

Abstract: A transform generator (20) has an input/output port (22). Coupled to the input/output port (22) is a controller (24). The input/output port (22) receives input transforms and data strings and outputs new transforms. A look up memory (26) is coupled to the controller (24) and is used to determine the new transforms. A shift module (28) and a combiner (30) are also coupled to the controller (24) and are used in combination with the memory (26) to determine a new transform.