Abstract: An encoder for encoding data from a communication channel, comprises a first address generator to generate a first address in accordance with the user data. A linear block encoder encodes the user data in response to the first address from the first generator. A transmitter transmits an output of the linear block encoder to the communication channel.

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding binary and duo-binary code. The reconfigurable MAP calculation circuit comprises M memory banks for storing N input data samples. Each input data sample comprises systematic data, non-interleaved parity data and interleaved parity data. The N input data samples are divided into M logical blocks and input data samples from each logical block are stored in each of the M memory banks. The reconfigurable MAP calculation circuit comprises M processing units. Each processing unit processes one of the M logical blocks. The reconfigurable MAP calculation circuit comprises a communication switch for coupling the M processing units to the M memory banks such that the M processing units simultaneously access input data samples from each of the M logical blocks in each of the M memory banks without collision.

Abstract: A system for conveying information includes a signal transport device. The signal transport device includes a set of links operable to convey a first set of information signals from a first computer module to a second computer module and a link operable to convey a transaction request credit signal associated with the first set of information signals, the signal indicating whether at least a portion of a transaction request message may be sent using the first set of information signals. The device also includes a set of links operable to convey a second set of information signals in the opposite direction of the first set of information signals and a link operable to convey a transaction request credit signal associated with the second set of information signals, the signal indicating whether at least a portion of a transaction request message may be sent using the second set of information signals.

Abstract: An arrangement and method for channel mapping in a UTRA TDD HSDPA wireless communication system by applying interleaving functions in first (530) and second (540) interleaving means to a bit sequence to produce symbols for mapping to physical channels, the first and second interleaving means being arranged to map symbols from respectively systematic and parity bits in a predetermined scheme, e.g., mapping symbols in a forward direction when a channel has an even index number, and in a reverse direction when a channel has an odd index number. The symbols may comprise bit-pairs, each of a systematic bit and parity bit. Systematic bits are preferably mapped to high reliability bit positions in TDD HSDPA, achieving a performance gain of between 0.2 dB and 0.5 dB. The forwards/reverse mapping allows a degree of interleaving that improves system performance in fading channels or channels disturbed by short time period noise or interference.

Abstract: Encoders and methods for designing encoders for Low Density Parity Check (LDPC) and other block codes are presented. An efficient and systematic method for designing partially parallel encoders is presented. A parallelism factor is selected such that the end result for the encoder is similar to the partially parallel G matrix multiplication method. In addition to the method an initial circuit is given for the G matrix multiplication encoder and the RU encoder. A circuit for the hybrid encoder is presented which achieves less power consumption and smaller area than an equivalent encoder based on the G matrix multiplication with a smaller critical path than previous encoders.

Abstract: A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.

Abstract: The invention relates to a method and a system for detecting errors in the communication of data from a transmitter to at least one receiver. In the method, in a first step on the side of the transmitter a first check value is generated at least from user data to be communicated; in a second step on the side of the transmitter a second check value is generated at least from the user data and the first check value; in a third step at least the user data, the first check value and the second check value are communicated to the receiver; in a fourth step on the side of the receiver the communicated user data and the communicated first check value are verified with the aid of the second check value; and in a fifth step on the side of the receiver the communicated user data are verified with the aid of the first check value.

Abstract: Techniques for generating cyclic redundancy check (CRC) values are provided. Bit messages that are to be transmitted to recipients are aligned to desired byte boundaries for purposes of generating CRC values, which are to be sent with the bit messages. The CRC values are rewound or adjusted back to values associated with original lengths of the bit messages before the CRC values are transmitted or forwarded with the bit messages to recipients.

Abstract: Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph.

Abstract: A system for computing a CRC value includes at least one memory for storing a data message, a current CRC value, and a plurality of lookup tables. The data message includes a plurality of words, with each word including a plurality of bytes. Each of the lookup tables stores a plurality of multi-byte CRC values. The system includes a processor for processing the message a word at a time. The processor is configured to update the current CRC value during processing each word based on an XOR of the word and the current CRC value, and based on a multi-byte CRC value retrieved from each one of the lookup tables.

Abstract: A multimedia distribution system is disclosed. The distribution system includes a transmitter unit that distributes content from a content provider to one or more wireless subscriber units. The transmitter unit includes a decoder configured to determine whether a plurality of incoming packets include one or more erasures, a transmitter configured to transmit the packets to a receiving unit, and an error detection code generator configured to generate an error detection code for each of the packets transmitted to the receiver unit, the error detection code being modified for each of the erased packets so that the receiver unit will be able to identify the erased packets.

Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

Abstract: A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n?1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit, and an arithmetic unit. The arithmetic unit includes a hardware circuit that is selectably operable to perform a row update and a column update. In such cases, a substantial portion of the circuitry of the hardware circuit used to perform the row update is re-used to perform the column update.

Abstract: A data transmission system includes parallel data paths for transmitting data, and an encoder for encoding the data such that an error correction code is generated for data at a same bit position across the parallel data paths.

Abstract: In an embodiment of the invention, an integrated circuit comprises an input module configured to receive a first data segment, an identifier module having a hard coded identifier, a processing module coupled to the input module and coupled to the identifier module and configured to process the first data segment with the hard coded identifier to generate a first error correction code, and an output module configured to transfer the first error correction code for storage on a storage system.

Abstract: A system and method is disclosed for detecting errors in memory. A memory subsystem that includes a set of parallel memory channels is disclosed. Data is saved such that a duplicate copy of data is saved to the opposite memory channel according to a horizontal mirroring scheme or a vertical mirroring scheme. A cyclic redundancy code is generated on the basis of the data bits and address bits. The generated cyclic redundancy code and a copy of the cyclic redundancy code are saved to the memory channels according to a horizontal mirroring scheme or a vertical mirroring scheme.

Abstract: A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.

Abstract: A communication circuit for verified communication comprising a transmitter having input terminals to receive a data word, an encoder configured to encode the data word to create an encoded word different from the data word, and output terminals configured to transmit the data word and the encoded word. A receiver is coupled to the transmitter and includes input terminals to receive the data word as a received word and the encoded word, a decoder configured to decode the encoded word to create a decoded word, and a comparator configured to compare the received word and the decoded word to create a select signal, and a selector responsive to the select signal and configured to select the received data word or the decoded word based at least in part on the select signal. Advantages of the invention include the ability to verify redundant received data without decreasing bandwidth or increasing latency.

Abstract: The security of data is enhanced by the use of cyclic redundancy checks. Data is encoded with one or more cyclic redundancy checks and then transmitted by a transmitter to a receiver. The receiver receives the encoded data and decodes it in order to use the one or more cyclic redundancy checks to determine whether the data was sent by an authorized user.

Abstract: A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

Abstract: A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC).

Abstract: A wireless communication device (200) including a first CRC coder that generates a first block of CRC parity bits on a transport block and associates the first block of CRC parity bits with the transport block, a segmenting entity that segments the transport blocks into multiple code blocks after associating, and a second coder that generates a second block of CRC parity bits on each code block and associates a second block of CRC parity bits with each code block. The first and second blocks of CRC parity bits are based on first and second generator polynomials. In one embodiment, the first and second generator polynomials are different. In another embodiment, the generator polynomials are the same and the transport block is interleaved before segmenting or the code block are interleaved before encoding with the second block of CRC parity bits.

Abstract: Cyclic redundancy check (CRC) processing is applied to a received sequence of data blocks that are defined by respective sequences of sets of parallel data. For each data block, there is produced a sequence of syndromes that respectively correspond to the sets of parallel data within the data block. The final syndrome in the sequence of syndromes corresponds to all of the data in the data block. The time required for CRC processing can be reduced by concurrently producing first and second ones of the syndromes that respectively correspond to first and second ones of the sets that are respectively contained in first and second ones of the data blocks.

Abstract: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). An encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. In one embodiment, a corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order.

Abstract: A method of generating a CRC for a composite sub-message based on a CRC generating polynomial having at least two factors. The composite sub-message includes sub-message data and a number, n, of trailing zeros. The method includes generating a first remainder based on the sub-message data and a first factor of the CRC generating polynomial. A second remainder is generated based on the sub-message data and a second factor of the CRC generating polynomial. The CRC for the composite sub-message is generated based on adjusted versions of the first and the second remainders.

Abstract: An apparatus and method for generating a (n, 3) code and a (n, 4) code using simplex codes are disclosed. To encode a 3-bit information bit stream to a (n, 3) codeword with n code symbols, a simplex encoder generates a first-order Reed-Muller codeword with (P+1) code symbols from the input information bit stream for n>P, and punctures the first code symbol of the (P+1) first-order Reed-Muller code symbols to produce a (P, 3) simplex codeword. An interleaver permutates the P code symbols of the (P, 3) simplex codeword by columns according to a predetermined pattern. A repeater repeats the column-permutated (P, 3) simplex codeword until the number of repeated codes is n and outputs a (n, 3) codeword with the n repeated code symbols.

Abstract: An encoding method encodes by using a quasi-cyclic code having a code length of n=m n0 and an information word length of k=m k0. The method includes the steps of: creating a systematic code with as many as (n0?k0) parity bits inserted therein in units of an information word k0; making all combinations of (n0?k0) parity bit positions that may occur in units of no bits; describing many of m×m cyclic matrices by rearranging the sequence of columns in a parity check matrix in the combinations; subjecting the parity check matrix to elementary transformation to create a unit matrix in which (n?k)×(n?k) matrices made up of the columns corresponding to the parity bit positions; regarding the transformed matrix as a first matrix and this matrix minus the unit matrix as a second matrix; and allocating (n?k) bit positions for the parity bits in such a manner that the number of non-zero elements included in the second matrix is minimized.

Abstract: A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.

Abstract: In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus (100) transmits, from two antennas (114A, 114B) , LDPC encoded data formed by LDPC encoding blocks (102A, 102B). In a case of a retransmittal, the multi-antenna transmitting apparatus (100) uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna (114A).

Abstract: A novel apparatus and method for encoding data using a low density parity check (LDPC) code capable of representation by a bipartite graph are provided. To encode the data, an accumulate chain of a plurality of low degree variable nodes may be generated. The accumulate chain may then be closed to form a loop twice, once using a low degree variable nodes and once using a higher degree variable which is higher than the low degree variable node, where the higher degree variable node comprises a non-loop-closing edge. In one embodiment, the plurality of low degree variable nodes may have the same permutation on each edge.

Abstract: A CRC redundancy calculation circuit is presented which is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data.

Abstract: A control channel encoder, e.g., in a UMB system, uses a channel structure that can efficiently transmit more information bits, yet achieve sufficient detection and false alarm performance. A control channel encoder can use a fixed encoder packet size, tail-biting convolutional coding, and Cyclical Redundancy Check (CRC). A control channel decoder can use Viterbi Decoding and a circular trellis check.

Abstract: A method for enhancing information security in a wireless communications system comprises receiving a data or control bit sequence and a user identity sequence, performing a CRC operation on the data/control bit sequence to generate a CRC bit sequence, and masking the CRC bit sequence with the user identity sequence to generate a coded bit sequence according to a formula. The formula comprises a first equation and a second equation, and the second equation calculates a plurality of coded bits of the coded bit sequence according to most significant bits or least significant bits of the user identity sequence and the CRC bit sequence.

Abstract: One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.

Abstract: Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.

Abstract: Methods and devices for encoding in parallel a set of data. bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset. The first subset is also encoded in parallel using the second subset. The first subset is also encoded in parallel using a subset of an immediately preceding set of data bits. Parallel encoding is realized by using an encoding module utilizing multiple single bit submodule. Each submodule receives a single bit from the first subset and either the second subset or the subset of the immediately preceding data set. Each single bit submodule produces a pair of output bits from the convolutional encoding of a single bit of the first subset and either the second subset or the subset of the immediately preceding data set. The multiple single bit submodules operate in parallel to simultaneously and collectively produce a set of data bits.

Abstract: A method of generating a CRC code to determine a variable field value for equalizing a CRC value, which is calculated based on data including the variable field value of a variable field included in a data field according to a generator polynomial, to a desired CRC value, comprises the steps of establishing a temporary variable field value, reading all corrective values which correspond to a bit number where a bit value of said temporary variable field value is “1”, from a conversion table which stores therein corrective values for indicating a bit to be inverted in the variable field value as “1” corresponding to a predetermined bit number, and exclusive-ORing the read corrective values to calculate a first calculated value, and, determining whether the first calculated value corresponds to the desired CRC value or not.

Abstract: A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first syndrome based on the first data and the first ECC code, (2) correcting the first data according to the first syndrome, while reading the second data, and calculating the second syndrome based on the second data and the second ECC code, (3) and correcting the second data according to the second syndrome, while reading the third data and calculating the third syndrome based on the third data and the third ECC code.

Abstract: LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified to LDPC symbol-check parallel decoding or LDPC hybrid-check parallel decoding. A novel approach is presented by which the edge messages with respect to the bit nodes and the edge messages with respect to the check nodes may be updated simultaneously and in parallel to one another. Appropriately constructed executing orders direct the sequence of simultaneous operation of updating the edge messages at both nodes types (e.g., edge and check). For various types of LDPC coded signals, including parallel-block LDPC coded signals, this approach can perform decoding processing in almost half of the time as provided by previous decoding approaches.

Abstract: An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop is set to a value equal to the modulus, left shifted one register position. Values of the working register are shifted multiple positions during a single loop iteration, and a shifted result is subtracted and compared to zero to determine subsequent contents of the working register.

Abstract: Disclosed is an encoding/decoding apparatus of a HARQ system using LDPC codes. A first LDPC code encoding apparatus encodes input information data and transmits the encoded data to the decoding apparatus. An interleaver interleaves the input information data. A second LDPC code encoder in parallel with the first LDPC code encoder performs LDPC code encoding on an output of the interleaver so as to transmit it to the decoding apparatus. The first LDPC code encoder transmits an output signal to the decoding apparatus at odd numbered retransmissions in response to a retransmission request from the decoding apparatus, and the second LDPC code encoder transmits an output signal to the decoding apparatus at even numbered retransmissions in response to the retransmission request from the decoding apparatus.

Abstract: A CRC generator/checker for generating CRC results, comprising: a set of CRC circuits connected in series, each CRC circuit responsive to a different control signal generated by a control logic, each CRC circuit having a seed input adapted to receive a seed, a data input adapted to receive and process a different set of M-bits of a data unit and a result output adapted to generate a result, the result output of a previous CRC circuit connected to the seed input of an immediately subsequent CRC circuit, the seed input of a first CRC circuit connected to an output of a remainder register, an input of the remainder register connected to an output of a multiplexer, the result outputs of the multiplicity of CRC circuits connected to different inputs of the multiplexer, the multiplexer responsive to a select signal generated by the control logic.

Abstract: A CRC calculation method and system for generating a CRC from a message is provided while improving the process time and simple to implement. A linear mapping matrix is used for the operation of the LFSR to generate the CRC and the maximum value of the non-zero entries in the mapping matrix is reduced by applying one or more raw operations to the linear mapping matrix in advance before the computation of mapping the input message to the CRC result. Flip-flops are additionally inserted before the generator matrix to obtain a pipeline architecture so as to further improving the operation speed thereof.

Abstract: An apparatus and method for detecting errors in received data and transferring only error-free data in data communications are provided. In the cyclic redundancy check (CRC) verification apparatus and method having a constant delay, irrespective of the length of a received data frame, input and output processing delay of received data is made to be constant. The CRC verification apparatus having constant delay comprises an input control unit which stores the start address of an input data frame in a memory storing the input data frame, and stores a CRC verification result in the start address location; and an output control unit which after a predetermined constant time passes from the start address, reads an input data frame and if the CRC verification result is normal, output the read data frame. The apparatus and method make the time taken for receiving a data frame, constant irrespective of the received data frame, while CRC verification is performed.

Abstract: A method and system for CRC calculation to an input message is provided while improving the process time and simple to implement. A linear mapping matrix corresponding to the LFSR to generate the CRC is planning, and the computation of the LFSR to the input message for the CRC generation becomes a simplified matrix multiplication. In the word-wise and doubleword-wise CRC32 cases, the input messages are padded with specific dummies before the prefix of the input message in accordance with their length types on the transmission side, or the CRC outputs derived from the received messages are compared with specific patterns in accordance with their length types on the reception side.

Abstract: A CRC generation unit includes a number of CRC calculation assemblies to be selectively employed to incrementally calculate a CRC value for a first sequence of N data bytes. The calculation is iteratively performed, one iteration at a time. Further, the selection of the CRC calculation assemblies is made in accordance with the group size of each of a number of data word groups of the N data bytes. In one embodiment, the CRC calculation assemblies include a first assembly for incrementally calculate the CRC value for an iteration, whenever the group size is n/2 bytes or less for the iteration, and a second assembly for incrementally calculate the CRC value for an iteration, whenever the group size is more than n/2 bytes for the iteration. In one embodiment, the CRC generation unit is a shared resource to multiple network traffic flow processing units of a network traffic routing IC.

Abstract: A CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple remainder values, for an iteration of an iterative CRC generation for a data block. In one embodiment, the unit also includes a selector to select one of the remainder values, and a register to store the selected remainder value, return the stored remainder value to the PDCs for formation of different bit length dividends, and output the stored remainder value of the last iteration as the generated CRC value. In one embodiment, the unit further includes alignment circuitry to align the data block. In one embodiment, multiple units are provided to generate the CRC values of successive variable length data blocks. In one embodiment, the units form a shared resource to multiple network traffic flow processing units of a network traffic routing IC.