Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

Abstract: A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device.

Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

Abstract: Aspects of the subject disclosure may include, for example, a processing system including a processor; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations including: dividing data provided for storage into data segments; encrypting each data segment of the data segments with an encryption key, thereby creating encrypted data slices; arranging a cluster of sectorized servers in an ordered list of sectorized servers; selecting a first sectorized server from the ordered list of sectorized servers; generating an access key; and sending a first encrypted data slice of the encrypted data slices and the access key to the first sectorized server, wherein the first sectorized server stores the first encrypted data slice in a sector of the first sectorized server, and retrieves the first encrypted data slice from the sector upon presentation of the access key. Other embodiments are disclosed.

Abstract: Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.

Abstract: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the 5 transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Abstract: A memory controller is to interface with a memory, associated with a plurality of pins, based on a codeword. The codeword is to include a plurality of n-bit symbols. An n-bit symbol of the codeword is to be formed from a plurality of n bursts over time associated with one of the pins of the memory.

Abstract: A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q?1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q?1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from a information packets, where n satisfies the formula Kmax×(q?1)?n.

Abstract: A method for data communication between a first node and a second node over a data path includes estimating a rate at which loss events occur, where a loss event is either an unsuccessful delivery of a single packet to the second data node or an unsuccessful delivery of a plurality of consecutively transmitted packets to the second data node, and sending redundancy messages at the estimate rate at which loss events occur.

Abstract: A data processing circuit includes an error processing circuit and a memory. Word data is configured by main body data to be divided into a plurality of partial words and redundant data. The redundant data is configured by error correction additional bits generated from the main body data on the basis of a predetermined error correction algorithm and the error correction additional bits include a plurality of parity bits corresponding to the partial words. The error processing circuit includes error correction circuit and parity check circuit into which the word data is input in parallel. The error correction circuit decides an error type by using the redundant data and corrects a correctable error. The parity check circuit performs a parity check on the basis of access-requested partial word and the corresponding parity bit.

Abstract: An apparatus and method are described for multi-bit error correction and detection. For example, one embodiment of a processor comprises: error detection logic to detect one or more errors in data when reading the data from a storage device, the data being read from the storage device with parity codes and error correction codes (ECCs); error correction logic to correct the errors detected by the error detection logic; and a matrix usable by both the error detection logic to detect the one or more errors and the error correction logic to correct the errors, the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region.

Abstract: A system and method for performing erasure code data protection and recovery computations using simple arithmetic and data manipulation functions. Other embodiments set forth techniques for using the computation functions with a multiplicity of compact one-dimension table lookup operations. A set of assigned multi-threaded processor threads perform computations on data values in parallel to generate erasure code data protection information and to perform data recovery operations using available data and the data protection information. During normal operations, in one embodiment, threads may perform parallel computations using a small set of simple arithmetic operations and data manipulation functions. In other embodiments, the threads may also use a multiplicity of compact one-dimension lookup tables stored within the multi-threaded processor or otherwise accessible by the multi-threaded processor to perform the computations.

Abstract: An error correcting method of a semiconductor memory device includes receiving first data from outside the semiconductor memory device. First check bits are generated based on the first data and a first parity generator matrix. The first parity generator matrix includes a plurality of columns of bits. The plurality of columns of bits are arranged in a plurality of parity generator matrix groups. An error correcting code (ECC) code word including a plurality of ECC code word groups is stored in the plurality of memory cell groups. Each of the plurality of ECC code word groups have the first data and the first check bits. The plurality of ECC code word groups correspond to the plurality of parity generator matrix groups, respectively.

Abstract: A method for decoding a variable length coded input including a plurality of binary code symbols into an output symbol includes: setting, by a decoder including a processor and memory storing a lookup table including a plurality of states, a current state to an initial state and a current branch length to an initial branch length; and identifying, by the decoder using the lookup table, a next state or a symbol of the output symbols based on a current state, a current branch length, and a next binary code symbol of the variable length coded input.

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.

Abstract: Processing data in a distributed data storage system generates a sparse check matrix correlating data elements to data syndromes. The system receives notification of a failed node in the distributed data storage system, accesses the sparse check matrix, and determines from the sparse check matrix a correlation between a data element and a syndrome. The system processes a logical operation on the data element and the syndrome and recovers the failed node.

Abstract: Embodiments relate to dynamically selecting an erasure code. State data is tracked to ascertain frequency of file access. One of at least two erasure codes are selected based on the tracked state data in order to lower data recovery cost. The erasure code may be selected as either a product code or a local reconstruction code. Each erasure code includes a mode that is either a fast code or a compact code. The fast code features a low recovery cost and the compact code features a low storage overhead for less frequently accessed data. Data is encoded with one of the selected erasure codes and one of the modes of the selected erasure code. Data blocks are dynamically converted between the fast and compact codes of the selected erasure code responsive to a workload change.

Abstract: The present invention relates to methods and devices for controlling a mobile terminal in a radio access network to transition between a plurality of communication states. This object is attained in a first aspect of the present invention by a method comprising the step of acquiring (S101) an indication regarding a pattern of burst data to be transmitted to the mobile terminal. Further, the method comprises the step of controlling (S102) the mobile terminal to transition to a less resource consuming communication state of the plurality of communication states upon occurrence of a period of transmission inactivity in the burst data.

Abstract: Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.

Abstract: A method begins by a processing module receiving data for storage and determining whether to partition the data in accordance with a data partitioning dispersed storage scheme. When the data is to be partitioned, the method continues with the processing module partitioning the data into a local data portion and a remaining data portion in accordance with the data partitioning dispersed storage scheme, dispersed storage encoding the local data portion to produce a plurality of local encoded data elements in accordance with dispersed storage encoding parameters, sending the plurality of local encoded data elements to an associated dispersed storage network (DSN) memory for storage therein, and sending the remaining data portion to another DS module.

Abstract: A method and system for enhanced security for A5/1 encoding, the method including choosing, at a transmitter, bits within a layer 1 header of a slow associated control channel (‘SACCH’) message for randomization; and setting, at the transmitter, the chosen bits randomly prior to channel coding and encryption of the slow associated control channel message. Further the method may include choosing, at a transmitter, a number of bits to toggle after convolution coding of a message containing a slow associated control channel message, the number of toggled bits being sufficiently low to allow correction at a receiver; and toggling, at the transmitter, said bits based on the channel conditions of the message.

Abstract: A semiconductor device includes a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred.

Abstract: A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first programmable processor, a store-with-release operation, executing, with a second programmable processor, a load-with-acquire operation, and loading, with the second programmable processor, the value of the shared variable data from a cache of the second programmable processor.

Abstract: Methods, apparatus and systems for error correction of n-valued symbols in (p,k) codewords including Reed Solomon codes of p n-valued symbols with n>2 and k information symbols have been disclosed. Coders and decoders using a Linear Feedback Shift Registers (LFSR) are applied. An LFSR can be in Fibonacci or Galois configuration. Errors can be corrected by execution of an n-valued expression in a deterministic way. Error correcting methods using Galois arithmetic are disclosed. Methods using Cramer's rule are also disclosed. Deterministic error correction methods based on known symbols in error are provided, making first determining error magnitudes not necessary. An error location methods using up and down state tracking is provided. Methods and apparatus executing the methods with binary circuits are also disclosed. Systems using the error correcting methods, including communication systems and data storage systems are also provided.

Abstract: In one embodiment, a tape drive system includes a write channel for writing data to a magnetic tape, the write channel utilizing a rate-(232/234) reverse concatenated modulation code. The write channel includes logic adapted for receiving a data stream comprising one or more data sets, logic adapted for separating each data set into a plurality of sub data sets, logic adapted for encoding each sub data set with a C2 encoding, logic adapted for encoding each C2-encoded sub data set with a modulation code, logic adapted for encoding each modulated sub data set with a C1 encoding, and logic adapted for simultaneously writing the encoded modulated sub data sets to data tracks of the magnetic tape. Other systems for writing data to a magnetic tape utilizing a rate-(232/234) reverse concatenated modulation code are described according to various other embodiments.

Abstract: A semiconductor device includes first and second circuits disposed separately from each other. The first circuit may include: a counting unit suitable for generating count codes, each bit of which is cyclically changing, wherein the count codes include a number of toggles of a sampling signal toggling with a preset frequency representing a distance of single round trip of the sampling signal between the first and second circuits; and a pulse generation unit suitable for generating a measurement pulse according to the count codes representing the distance, wherein the pulse generation unit determines a pulse width of the measurement pulse according to the distance.

Abstract: An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.

Abstract: Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed.

Abstract: A method for controlling access operations of a flash memory includes: receiving first source data from a host; generating a plurality of first scrambled signals according to a plurality of pseudo random sequences and the first source data; obtaining a plurality of transmission powers of the first scrambled signals; and selecting a target scrambled signal from the first scrambled signals according to the transmission powers for storing to the flash memory. An associated flash memory device and an associated flash memory controller are also provided.

Abstract: The proposed invention teaches basic principles of “orthonormal transform” to be used to convert a set of discrete samples into a set of coefficient real samples that is contained in a finite field. The number of real values in each coefficient samples is finite and coded for transmission using digital modulation. It also teaches that handling of multi-path fading of Doppler effects implies that the Bit Error Rate (BER) performance as a function of Bit Energy/Noise (Eb/N0) is close to the performance of Additive White Gaussian Noise (AWGN) channel. The effect of impairments is minimized and only the effect of thermal noise (AWGN) is maintained. The inventive apparatus is simple and maintains constant end-to-end response time, sustainable effective data rate and bounded error performance which is conducive to specify a Quality of Service (QoS) which is useful for service provisioning.

Abstract: An improved method for forward error correction (FEC) in packetized networks. The proposed FEC method improves upon the conventional methods by reordering packets in advance to a certain depth. This allows for dispersing losses of groups of packets. Additionally, the method provides for a dynamic change of a current FEC scheme. In order to defend packet sequences from group losses, the FEC packets are dispersed within the packet stream in such a manner that the packets of the same sequence are located as far as possible from each other. The packets are mixed for minimization of losses and effective recovery.

Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

Abstract: Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed.

Abstract: Handling burst error events with interleaved Reed-Solomon (RS) codes. A received signal, that has undergone convolutional interleaving sometime before, is received from a burst noise affected communication channel. The signal undergoes convolutional deinterleaving and the codewords generated there from undergo appropriate successive cyclic shifting to arrange burst noise affected symbols of various codewords into at least some common symbol locations. For example, at least two codewords have burst noise affected symbols in common symbol locations. An ensemble decoder jointly decodes multiple codewords during a same time period (i.e., processes multiple codewords simultaneously). By processing multiple codewords simultaneously, the ensemble decoder has greater error correction capability than a decoder that processes a single codeword at a time.

Abstract: Methods for digital signal processing and transmission/reception systems utilizing the methods based on the use of LDPC codes, for example a LDPC code with a 3/5 code rate, in combination with a QAM modulation, for example the 16QAM or 64QAM or 256QAM modulation. In transmission, a bit permutation (Demux) is carried out prior to the QAM constellation mapping function, and in reception, the bit permutation is carried out after the QAM constellation demapping function.

Abstract: A method is dedicated to encoding data that must be transmitted by means of a wave-based transmission infrastructure, and comprises i) a step consisting of creating in parallel M first matrices having T rows and C columns with subsets of data from B successive received bursts, the subsets of data from each burst being distributed within at least two successive first matrices, ii) a step consisting of creating in parallel M second matrices each having T rows and N columns with parity symbols resulting from encoding the data that is respectively contained in the rows of each of the M first matrices, iii) a step consisting of creating in parallel M first matrices having K rows and C columns with parity symbols resulting from encoding the data that is respectively contained in the columns of each of the M first matrices, and iv) a step consisting of distributing by interlacing, firstly, J subsets of parity symbols from each second matrix into J successive sets, and secondly P subsets of parity symbols from each t

Abstract: Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.

Abstract: In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding interleavers/deinterleavers in the different subword-processing paths use different interleaving/deinterleaving algorithms.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device comprises a memory and a controller. The memory is for data storage. When the data storage device receives first source data to be written to the memory from a host, the controller generates at least one first input data according to the first source data, scrambles the first input data according to a plurality of pseudo random sequences to obtain a plurality of first scrambled signals, calculates a plurality of transmission powers of the first scrambled signals, and selects a target scrambled signal with a lowest transmission power to be stored in the memory from the first scrambled signals.

Abstract: An apparatus and method of an outer Forward Error Correcting (FEC) code for a mobile broadcast service based on TD-SCDMA network is disclosed.

Abstract: Systems and methodologies are described that facilitate interleaving encoded control channel information for transmission over an uplink channel. The encoded control channel information, for example, can include encoded Channel Quality Indicator (CQI) information, encoded Precoding Matrix Indicator (PMI) information, and/or Rank Indicator (RI) information. CQI information, PMI information, and/or RI information can be encoded at an access terminal, for instance, by applying a punctured Reed Muller block code to generate a sequence of encoded bits. The encoded bits can be interleaved to reorder the sequence utilizing one or more interleaving approaches. Examples of interleaving approaches that can be leveraged include prime number based interleaving, generalized bit reversal interleaving, column-row interleaving with column bit reversal, and/or M-sequence based interleaving. Further, the reordered sequence of encoded bits can be transmitted to a base station over an uplink channel.

Abstract: Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed.

Abstract: An assignment scheme exploits the Media Access Control (MAC) layer protocol features under various MAC layer call scenarios. In one embodiment, the Hamming distance between pairs of critical Data Units are assigned to codewords with a minimum distance of dmin2=8 bits, thereby increasing the hard decision error correcting capability from 1 bit to 3 bits when deciding between these pairs of Data Units. The method for assigning data unit identification (DUID) codes by a radio operating within a wireless communication system includes determining by the radio whether an expected burst is a 4 Voice Burst with Encryption Synchronization Signaling (4V); when the expected burst is 4V, decoding the DUID within the received burst using an increased minimum distance; and when the expected burst is not 4V, decoding the DUID within the received burst using a minimum distance.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes a first detector, a second detector, a decoder and a unified memory buffer. An input data set is received by the first detector that performs a data detection and provides a first detected data set. The decoder receives a derivative of the first detected data set and performs a decoding operation that yields a decoded data set. In some cases, the derivative of the first detected data set is an interleaved version of the first detected data set. The decoded data set is written to a unified memory buffer. The first decoded data set is retrievable from the unified memory buffer and a derivative thereof is provided to the second detector. In some cases, the derivative of the decoded is a de-interleaved version of the decoded data set.

Abstract: A decoding method implemented in a deinterleaver is provided, converting a television signal to image data. A preset mechanism is provided for converting the television signal to the image data. The preset mechanism comprises a plurality of multiplication and addition operations performed using a database and an adder.

Abstract: An encoding system for encoding error control codes may include a first encoder configured to encode an input bit stream to generate first bit streams of C-bits, where c is an integer greater than zero, and a second encoder may be configured to receive the first bit streams and shuffle data of the received first bit streams to generate second bit streams. The data shuffling of the first bit streams may adjust an error distribution of the second bit streams. An encoding method may include encoding an input bit stream to generate first bit streams of C-bits, and receiving the first bit streams and shuffling data of the received first bit streams to generate second bit streams. An error distribution of the second bit streams may be adjusted based on the data shuffling.

Abstract: A method of protecting important data in digital content and an apparatus therefor are provided. The method includes: receiving digital content which includes first important data; receiving reference data which includes second important data and authentication data for verifying whether the first important data is modified; and selectively correcting the first important data included in the digital content based on the reference data.

Abstract: In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: In an embodiment, regarding an addition of a kb-bit number A and a b-bit random number r, element data of a pre-calculated table C? is set based on a sum AH+rH of a value AH of upper b/2 bits of a number A2, which is lower b bits of the number A, and a value rH of upper b/2 bits of the random number r and the sum AL+rL of a value AL of lower b/2 bits of the number A2 and a value rL of lower b/2 bits of the random number r in such a way that presence/absence of carrying-over of A2+r is indicated. Accordingly, the size of the pre-calculated table needed to be reduced for obtaining an addition result of upper (k?1)b bits by mutually adding the kb-bit number A and the b-bit number r.