Abstract: An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code (“ECC”) generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells as a plurality of data bit strings in a first direction and as a plurality of data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC generator generates a respective correction code in the first direction for each data bit string in the first direction and also generates a respective correction code in the second direction for each data bit string in the second direction. The ECC controller is coupled to the memory cells and the ECC generator.

Abstract: A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a second portion. The processing logic uses the first portion for random error correction and the second portion for erasure error correction.

Abstract: An apparatus for producing a word of a de-interleaved sequence of bits from a sequence of bits stored in a memory is described. In one embodiment, the apparatus includes a read circuit for selecting bits of the stored sequence and forming the selected bits into a word, and a logic network arranged to produce the word of the de-interleaved sequence by concatenating sections of a plurality of words produced by the read circuit. The technique can also be used to achieve interleaving, rather than de-interleaving, of a data sequence.

Abstract: A communications line monitoring system of the present invention comprises a plurality of relay apparatus and a communications line monitoring apparatus for monitoring a line quality of a communications line of relayed data, and each of the relay apparatus comprises error detecting unit for detecting errors in received data, previous error detection determination unit for determining whether or not error detection has already been performed in other apparatus based on previous error detection information of the received data, and initial error detection process unit for, only when an error is detected and the error was undetected in other apparatus, autonomously notifying error detection information to the communications line monitoring apparatus, and for adding previous error detection information to data for transmission.

Abstract: Error bursts are randomized by an interleaver which makes use of “set leaders” to generate permutation indices. The permutation indices are used to route bits from initial positions in an input bit stream to re-arranged or randomized positions in an output bit stream. When the output bit stream is then transmitted and subsequently received by a de-interleaver which returns the received bits to their initial, pre-randomized positions, the resulting received signal has an acceptable bit error rate.

Abstract: A method of storing DVB-H data from a DVB-H data burst, the method comprising: identifying erasures in the data burst; and storing non-erasure data from the data burst in memory locations of a memory that would be used to store erasures.

Abstract: Methods and apparatus for generating parity symbols for a data block are disclosed. One of the proposed methods includes: determining a multiplicator polynomial for a first-direction symbol line of the data block, receiving a set of symbols on the first-direction symbol line, multiplying each of the set of symbols by the multiplicator polynomial to generate a set of product polynomials, repeating the determining, receiving, and multiplying steps for a plurality of first-direction symbol lines of the data block to generate a plurality of sets of product polynomials, and summing the plurality of sets of product polynomials to generate a set of parity polynomials. The coefficients of the set of parity polynomials constitute parity symbols of the data block.

Abstract: The conventional error conceal processing generates a greatly fluctuating irregular sound which is unpleasant to ears and causes a remarkable echo effect and click noise. A notification signal detection unit (301) judges processing for an input frame. In case of an error frame, a sound detection unit (303) makes judgment whether a preceding non-error data frame is a sound signal. If it is a sound frame, a sound copying unit (304) generates a replacing frame. If it is a non-sound frame, a transient signal detection unit (305) judges whether it is an attack signal by the transient signal detection and selects an appropriate area from the preceding non-error frame.

Abstract: A hardware random number generator (RNG) has a source of entropy for providing a bit stream (DIS) comprising successive bits of a first state and a second state. The RNG includes a first digital corrector circuit configured to provide from two successive bits in the bit stream an output bit of an output bit stream according to a first scheme to ensure that bits in the output bit stream are independent from one another. A serially connected second digital corrector circuit ensures that the bits in the output bit stream are also unbiased, so that the output bit stream is truly random. A Gaussian generator connected to an output of either the first corrector or the second corrector generates from the output bit stream words having standard Gaussian deviates.

Abstract: An interleaver parameter generator circuit used to calculate and generate on an as needed basis interleaver parameters for interleaving blocks of information of varying lengths in accordance with a pseudorandom pattern defined by the 3GPP standard. The interleaver parameter generator circuit calculates and generates the defined interleaver parameters based on an input parameter that represents the length of the block of information to be interleaved. At least one of the defined parameters is calculated and generated using a decomposed form of its definition. The interleaver parameter generator circuit uses well known circuit blocks such as multipliers, subtractors, Compare-and-Select circuits and other circuits to calculate and generate the defined parameters.

Abstract: Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of bit failures in a line, respectively. The updating of first and second counters after a third time correction of bit failure in the line is disabled.

Abstract: A system and method for characterizing the jitter of a periodic signal. Samples of the signal are taken with a sampling device. A set of samples representing a particular value of the signal in multiple cycles of the periodic signal is collected. Those values are formed into a histogram. The histogram is matched to a probability distribution function. By identifying parameters that shape the probability distribution function to match the histogram of actual samples, characteristics of the jitter are determined. This technique may be employed as part of the calibration or verification of the jitter injection instrument such as might be used for testing semiconductor devices. Measurements may be made with a sampling device that is calibrated to NIST standards. In this way, the jitter measurements become NIST traceable.

Abstract: The proposed invention teaches the principle of KV transform coding is an orthogonal and invertible “embedded transform coding” method that provides a very efficient error control with low-complexity decoding and operates at very low Eb/N0. It is unique in the sense that it corrects errors and the remaining samples in error are known unlike other known techniques. The proposed invention has been implemented with error correction, single retransmission of selected samples in error and interleaving of samples of KV blocks to achieve BER of 10?7 at average EB/N0 of <10 dB and BER of 10?3 at an average BER of <3 dB. More over, the proposed system has a code redundancy of log2 (n) for correcting first order correction of one sample in error out of four samples received with a code rate of 2/3. The invention is useful for noisy wireless networks.

Abstract: Devices, software, and methods measure a burstiness of packet loss episodes in transmissions of voice data through networks. At least one burstiness statistic is determined to quantify how the lost packets are distributed with respect to the received packets within the sequence. The burstiness statistic is optionally used to determine a figure of merit, which in turn can be used to give a grade for predicting how well a packet loss concealment scheme will work.

Abstract: A method of determining optimal FEC configuration parameters, a communications controller, a communications link and a communications node is disclosed. In one embodiment, the communications controller, includes: (1) a processor, (2) a communications system information collector configured to receive operational information from a communications system having a block encoder, a block decoder and a decision feedback equalizer, (3) a code determiner configured to employ the operational information to select, from a set of candidate codes, a random error correction code or a burst error correction code that has a least error correction capability and satisfies a target performance specification for the communications system and (4) a parameter selector configured to select configuration parameters associated with the selected random error correction code or the selected burst error correction code and send the selected configuration parameters to the block encoder and the block decoder.

Abstract: Systems, methods and data structures are provided for representing robust data transmitted within a control system. The data structure includes at least two data fields identifying sub-modules and sub-modes of the control system, and optionally includes a third field for designating a primary operating mode of the control system and/or a fourth field representing a handshaking bit or value. The operating modes, sub-modes and sub-module designators are represented by values of the bits selected such that no single bit transition results in the selection of another valid operating state of the control system. As a result, single bit errors will not produce erroneous operating results. Similar concepts can be optionally applied to ensure that errors in contiguous sets of four, eight or any other number of bits do not produce valid states represented by the data structure.

Abstract: Embodiments of the invention generally provide methods, systems, and articles of manufacture for selecting a data bus inversion (DBI) mode of operation. A comparison circuit of a device may receive multiple packets of data to be transmitted to another device over a bus connecting the devices. The comparison circuit may compare the multiple packets of data and select a DBI mode of operation that conserves power and reduces noise on the bus.

Abstract: Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that separate chips and data lines are not required to support ECC. The memory devices on the modules each contain additional indirectly addressable ECC segments associated with addressable segments of the device. The temporally multiplexed ECC data is read from and written to the indirectly addressable segment associated with the addressable data transmitted in the burst mode transfer. In some embodiments, two types of burst modes are supported, one which includes ECC data and one which does not. This allows one type of memory module to support both ECC and non-ECC systems, and in some cases to use ECC for some data and not for other data in the same system. Other embodiments are described and claimed.

Abstract: An embodiment may include an apparatus comprising a dejitter buffer to receive packets containing audio data, a codec coupled with the dejitter buffer, the codec to receive coded audio frames from the dejitter buffer and decode them, and a concealed seconds meter coupled with the dejitter buffer, the concealed seconds meter to record concealment events by the decoder to provide an objective measure of media impairment. Another exemplary embodiment may be a method comprising receiving packets containing audio information at a dejitter buffer, decomposing the packets to coded audio frames, sending the coded audio frames to a decoder and decoding the frames, generating a concealment output stream if the decoder does not receive a valid frame from the dejitter buffer, and recording concealment events to provide an objective measure of media impairment.

Abstract: Apparatus, and an associated method, for recovering the informational content of an encoded data block. Data bursts are delivered to a receiver. A series of data bursts together include all of the informational content of the encoded data block. A detector detects delivery to the receiver of the data bursts. A determiner determines indicia associated with the communicated data. And, responsive thereto, the data is decoded, selectably utilizing fewer than all of the data bursts that form the encoded data block.

Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: A system for transmitting data between stations, such as base stations and subscriber stations in a wireless telecommunications system, employs variable set of interleaving parameters for its interleaving operations. By using different set of interleaving parameters with the interleavers, data which would otherwise be aligned when transmitted from a station to many stations, or from many stations to a station, will not be aligned after interleaving has been performed. This reduces the peak to average ratio required for a transmitter and/or can reduce interference experienced at receivers in the system. This is especially true if a significant proportion of the otherwise aligned signals are symbols which require zero energy to transmit.

Abstract: A method of embedding an additional layer of error correction into an error correcting code, wherein information is encoded into code words of said code over a first Galois field and wherein a number of code words are arranged in the columns of a code block comprising a user data sub-block and a parity data sub-block, provides an additional layer of error correction that can be easily implemented without losing compatibility improving the error correction capabilities. The method includes the steps of: encoding the rows of at least the user data sub-block separately or in groups using a horizontal error correcting code over a second Galois field larger than the first Galois field to obtain horizontal parities, and embedding the horizontal parities as additional layer in the error correcting code.

Abstract: A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving method is improved by sensing generation of an internal address corresponding to an embedded address, and generating a redundancy flag signal, such that the embedded address is an address preceding the address of the memory cell of the normal cell array to be repaired by at least one clock.

Abstract: Error bursts are detected and corrected in a communication system using shortened cyclic codes, such as shortened Fire codes. Data is loaded into a first error syndrome register and a second error syndrome register. The data in the registers may be evaluated to determine if the data bits contain a correctable error. Shortened zero bits are shifted into the second error syndrome register. A number of zero bits are shifted into the first error syndrome register to trap an error burst pattern in the data. A determination is made as to the number of zero bits shifted into the second error syndrome register to trap the location of the error burst in the data. Using the number of zero bits shifted into the second error syndrome register and the error burst pattern, the error in the data is located and corrected.

Abstract: Error bursts are randomized by an interleaver which makes use of “set leaders” to generate permutation indices. The permutation indices are used to route bits from initial positions in an input bit stream to re-arranged or randomized positions in an output bit stream. When the output bit stream is then transmitted and subsequently received by a de-interleaver which returns the received bits to their initial, pre-randomized positions, the resulting received signal has an acceptable bit error rate.

Abstract: The present invention is a correcting system for correcting a linear block code generated by coding an original data via a data coding process when a predetermined correction portion of an original data is corrected by a variant correction data. The correcting system comprises a coding module and a correcting module. The coding module is used to code the variant correction data via the data coding process to generate a corresponding variant correction code. The correcting module is used to store the variant correction code and calculate the variant correction code and the linear block code to generate a substitute code to substitute the linear block code. Therefore, if the data is modified after an optical recording system has completed coding the data, the optical recording system could add the substitute code to generate the renewed linear block code, unnecessarily reprocessing the complicated data coding process.

Abstract: An apparatus and method to facilitate validation and/or test of serial interfaces by analyzing error event types based at least in part on a code-stamp, compare engine logic and a memory for error capture.

Abstract: A method for interlacing digital data to reduce transmission errors includes dividing a stream of digital data into consecutive blocks of bits, and interlacing each block of bits by writing to an interlacing table. The interlacing table is arranged in the form of rows and columns of memory addresses, with a number of the rows and columns corresponding to predetermined interlacing parameters. The access sequences to the memory addresses for interlacing the blocks of bits are different from each other. The method further includes reading a block of bits in the interlacing table according to a memory addresses access sequence, and also writing bits to a consecutive block of bits according to the memory addresses access sequence during the reading.

Abstract: An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.

Abstract: A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The expansion of the base matrix Hb uses identical submatrices for 1s in each column of the second part H?b2, and the expansion uses paired submatrices for an even number of 1s in hb.

Abstract: A method, apparatus and program storage device for correcting a burst of errors together with a random error using cyclic or shortened cyclic codes is disclosed. The present invention solves the above-described problems by providing a received word to a syndrome register defined by a polynomial of degree n-k, said polynomial generating a cyclic or shortened cyclic code, wherein n is the length and k is the number of information bits in the codeword. The syndrome gets modified each time the received (possibly noisy) word is shifted. The contents of the syndrome register are processed to identify a random error together with an error burst of the received word. Then correction of the random error and the burst is made and a corrected codeword is generated.

Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.

Abstract: The present invention provides a system and method for explicitly transmitting a block attribute in the data of a block. In one embodiment, a current block of data is randomized in accordance with an ID value from the current block and from at least one temporally adjacent block of data. The ID of the current block is selected such that when combined with determined bits of the data results in the value of the block attribute. During a decoding process, the block attribute is retrieved by accessing the determined bits of the data. In one embodiment, the data is then decoded by generating possible candidate decodings and evaluating the candidate decodings based upon confidence metrics.

Abstract: A method of transmitting convolutionally encoded data with separate, independent and looped encoding over at least one data portion. The data is distributed over one or more cycles, and a plurality of cycles can be grouped into packets for discontinuous transmission if necessary. Weighted decoding is effected independently and cycle by cycle: it starts at a robust location, with a relatively high likelihood, and terminates at a weak location, with a weak likelihood, ignoring the concept of time. This limits the size of the packets of errors and prevents the propagation of packets of errors due to scrambling. Independent encoding and decoding of data can be effected without exchanging parameters between cycles and the parameters of each cycle (size, redundancy, constraint length) can be separate. Different degrees of protection and time-delay are permitted as a function of the nature of the data to be transmitted (voice, digital data, signaling, etc.).

Abstract: A method of forward error control in which a transmitter receives data from an input device and creates one or more original codewords that are transmitted onto each of two physically distinct telecommunications channels. Two copies of the original codeword are transmitted to the receiver via physically distinct channels to increase the robustness of the telecommunications channel between the transmitter and the receiver and to minimize the elapsed time between when the transmitter transmits the original codeword and when receiver has a final estimate of the original codeword available for output.

Abstract: The present invention provides for adaptive and multimode decoding, in a data packet-based communication system, to provide improved received signal quality in the presence of burst erasures or random bit errors, with particular suitability for real-time, delay sensitive applications, such as voice over Internet Protocol. In the presence of burst erasures, the adaptive multimode decoder of the present invention provides burst erasure correction decoding, preferably utilizes a maximally short (MS) burst erasure correcting code, which has a comparatively short decoding delay. Depending upon the level of such burst erasures, different rate MS codes may be utilized, or other codes may be utilized, such as hybrid or multidescriptive codes. When no burst erasures are detected, the adaptive multimode decoder of the present invention provides random bit error correction decoding, in lieu of or in addition to corresponding burst erasure correction coding.

Abstract: An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.

Abstract: Methods and apparatus of the present invention can be used to implement a communications system wherein different devices using the same LDPC code can be implemented using different levels of parallelism. The use of a novel class of LDPC codes makes such differences in parallelism possible. Use of a factorable permuter in various embodiments of the invention make LDPC devices with different levels of parallelism in the encoder and decoder relatively easy to implement when using the codes in the class of LDPC codes discussed herein. The factorable permuter may be implemented as a controllable multi-stage switching devices which performs none, one, or multiple sequential reordering operations on a Z element vector passed between memory and a Z element vector processor, with the switching one individual vectors being controlled in accordance with the graph structure of the code being implemented.

Abstract: Devices, software, and methods measure a burstiness of packet loss episodes in transmissions of voice data through networks. At least one burstiness statistic is determined to quantify how the lost packets are distributed with respect to the received packets within the sequence. The burstiness statistic is optionally used to determine a figure of merit, which in turn can be used to give a grade for predicting how well a packet loss concealment scheme will work.

Abstract: A host system for generating a software built-in self-test engine (SBE) is provided for enabling on-chip generation and application of a re-generative functional test on a complex device such as a microprocessor under test. The host system comprises user directives provided to indicate user desired actions; instruction information provided to define a suite of instructions; and a SBE generation tool arranged to generate a software built-in self-test engine (SBE) based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device such as a microprocessor under test and activation of a re-generative functional test on the complex device under test (DUT).

Abstract: A system and method for providing adaptive rate selection mitigates impulse-like noise and allows for interleaving and RS coding, while not excessively delaying data transmission. Generally, the system utilizes a memory and a processor, wherein the processor is programmed by software stored within the memory to perform the step of reading a specified data transmission delay rate for a channel utilized for data transmission. A Reed Solomon encoder is utilized by the adaptive rate system, which performs the steps of: reading a specified number of redundant bytes in a Reed Solomon frame; determining a level of impulse protection control from the number of redundant bytes in the Reed Solomon frame and a maximum code word length; and determining a number of symbols comprised within the Reed Solomon frame. In addition, an interlever is utilized for determining an interlever depth via use of said number of symbols comprised within the Reed Solomon frame and the specified data transmission delay rate for the channel.

Abstract: A circuit for controlling the random character of a bit flow, including an input shift register receiving the bit flow and having its outputs exploited in parallel, at least one element for comparing at least a partial content of the input register with predetermined patterns, a plurality of counters in a number at most equal to the number of predetermined patterns, and an element for detecting the exceeding of at least one threshold by one of the counters, the result of this detection conditioning the state of a word or bit indicative of the random or non-random character of the bit flow.

Abstract: A method for interleaving data frames transmitted via a modem pool, each of the data frames including a plurality of codewords having a predefined level of error correction, including assigning the data frames to corresponding modem timeframes, where codeword symbols in each of the data frames are assigned to time slots in the modems in the corresponding timeframes such that the level of error correction is sufficient to correct error/loss caused to any of the symbols given a predefined level of modem loss/malfunction, and moving any of the codeword symbols assigned to one of the timeframes to another of the timeframes such that the level of error correction is sufficient to correct error/loss caused to any of the symbols given a predefined level of cross-modem error burst while preserving the level of error correction sufficient to correct error/loss caused to any of the symbols given the level of modem loss/malfunction.

Abstract: A process and apparatus is described for recovering from optical transmission degradation due to scintillation effects in optical free space. A payload bit stream is encoded into Reed-Solomon codewords. These are fragmented and distributed as interleaved segments over a cell matrix of a SDRAM buffer store which is made large enough to correct a burst error occurring over 20 million consecutive bits. The rate imbalance between conventional read vs. write operations for SDRAM devices, which would otherwise obviate their use in this application by preventing real time operation, is overcome by an address remapping that avoids having to changing page addresses each time SDRAM memory is referenced. The remapping facilitates a more nearly equal allocation of READ overhead and WRITE overhead. An optical communications system employs at both the transmit and receive ends, substantially equivalent SDRAM buffer with address remapping capability.

Abstract: A data packet type communication system utilizes packet framing wherein preambles are split into two or more subpreambles, separated by a number of data or a priori known symbols. A receiver chooses among individual and combined subpreamble options for determining synchronization. When a noise impulse prevents detection of one subpreamble, the impulse is detected, and preamble correlation proceeds using an unaffected subpreamble. When no impulse is detected, combined subpreambles are used.

Abstract: A method and apparatus for reducing the information error rate of a communication network. The apparatus comprises a selector device coupled to a Framer and to an Interleaver. The selector device is configured to receive system information and the Framer is configured to receive user information. The apparatus is coupled to equipment which operate the communication network based on system parameters. The apparatus and method of the present invention improve the coding and effectively increase the interleaving depth applied to user information thus reducing the information error rate of the communication network without having to alter or modify any of the system parameters.

Abstract: A communication system 100 employs turbo encoding having a turbo interleaver 106 that interleaves input data 101 efficiently with little use of system resources. The turbo interleaver 106 reads address locations of the data bits into an interleaver matrix array 206 row by row and interleaves the address locations by bit reversal of the row indexes with accompanying permutation of the corresponding address locations in the rows of the matrix 206, bit reversal of the column indexes with accompanying permutation of the corresponding address locations in the columns of the matrix 206 and shifting the address locations within each row a predetermined number of column locations based on the particular row number.

Abstract: A method and apparatus for decoding a frame of interleaved information bits in a communications system, where the decoding of the frame of interleaved information bits may begin before all of the bits in the frame are received at a decoding site. The frame of interleaved information bits has a frame start time and a frame end time. The frame also includes a first fractional segment that has a start time that is the same as the frame start time and an end time that is before the frame end time.