Abstract: A Galois field arithmetic operation circuit substituting (2^m?1) elements (m is an integer) expressed by m bits of Galois field GF(2^m) includes: a base calculation unit configured to calculate m linear independent elements out of the (2^m?1) elements; and a linear development unit configured to calculate the remaining (2^m?1?m) elements not included in the m linear independent elements by combination of the m linear independent elements respectively. The Galois field arithmetic operation circuit may be included in a memory device or other system.

Abstract: A method begins by a processing module receiving data for storage and interpreting the data to identify the data as redundant array of independent disks (RAID) data. The method continues with the processing module interpreting the RAID data to identify at least one of RAID block data and RAID parity data. When the RAID data includes RAID block data and RAID parity data the method continues with the processing module encoding the RAID block data in accordance with error coding dispersal storage function parameters to produce at least one set of encoded data slices and outputting the at least one set of encoded data slices to a dispersed storage network memory.

Abstract: A storage device of a DSN includes a plurality of memory devices, an interface, and a processing module. The storage device receives an encoded data slice of a set of encoded data slices, wherein a data segment is dispersed storage error encoded to produce the set of encoded data slices. The dispersed storage error encoding includes arranging the data segment into a data matrix of data blocks, generating an encoded data matrix from the data matrix and an encoding matrix, and arranging encoded data blocks of the encoded data matrix into the set of encoded data slices. The storage unit then divides the encoded data slice into encoded data slice partitions and generates a parity data partition therefrom. The storage device then stores the encoded data slice partitions and the parity data partition in separate memory devices.

Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.

Abstract: A method begins with a processing module of a dispersed storage network (DSN) identifying an encoded data slice of a set of encoded data slices that requires rebuilding and identifying storage units of the DSN that store the set of encoded data slices. The method continues with the processing module determining a rebuilding metric regarding the identified encoded data slice and selecting a sub-set of the storage units for retrieving a decode threshold number of encoded data slices of the set of encoded data slices based on the rebuilding metric. When the decode threshold number of encoded data slices have been retrieved, the method continues with the processing module decoding the decode threshold number of encoded data slices to produce a reconstructed data segment and generating a rebuilt encoded data slice from the reconstructed data segment.

Abstract: A system and method for minimizing power consumption in a transceiver circuit that uses a digital high-speed serial communications link between at least two devices is presented. Comma code matching is generally used as a means for establishing byte synchronization and for determining and preventing data transfer errors. However, comma code matching, when performed in high speed serial communications links that can transfer data at rate of giga-bits per second, can use a significant amount of power. Thus, the system and method described herein maintain comma code matching in an off-state, and transition comma code matching from an off-state to an on-state when a substantive operational change occurs in the serial communications link.

Abstract: A method of generating a sequence of display frames for display on a display device, wherein the sequence of display frames are derived from a data string which is encoded to include error correction in order to enable recreation of the data string at a receiving device, includes dividing the data string to be encoded into a plurality of source segments; encoding the plurality of source segments to generate a plurality of codewords, each codeword comprising a plurality of codeword bits; and positioning codeword bits in the sequence of frames.

Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

Abstract: Systems and methods are provided for securing data in virtual machine computing environments. A request is received for a security operation from a first virtual machine operating in a host operating system of a first device. In response to receiving the request, a first security module executes the security operation, the first security module implemented in a kernel of the host operating system. The result of the security operation is provided to the first virtual machine.

Abstract: A method begins by a processing module receiving data for storage and interpreting the data to identify the data as redundant array of independent disks (RAID) data. The method continues with the processing module interpreting the RAID data to identify at least one of RAID block data and RAID parity data. When the RAID data includes RAID block data and RAID parity data the method continues with the processing module encoding the RAID block data in accordance with error coding dispersal storage function parameters to produce at least one set of encoded data slices and outputting the at least one set of encoded data slices to a dispersed storage network memory.

Abstract: A method begins with a processing module storing a set of encoded data slices in memory of a dispersed storage network (DSN), where a data segment is encoded using an error coding dispersal storage function to produce the set of encoded data slices. The method continues with the processing module adding the data segment to a rebuilding list, where encoded data slices of data segments identified in the rebuilding list are checked via a rebuilding process to detect errors and, when one of the encoded data slices has an error, the rebuilding process rebuilds the one of the encoded data slices. The method continues with the processing module, in response to a condition, removing the data segment from the rebuilding list.

Abstract: A systematic encoder such as a systematic polar encoder for channel encoding to ameliorate the effects of noise in a transmission channel. The codeword carries a data word to be transmitted transparently, and also carries a parity part derived from the data word and a fixed word. Implementations advantageously reduce coding complexity to the order of N log(N), wherein N is the dimension of a matrix of the nth Kronecker power associated with a matrix effectively employed by the encoder.

Abstract: In cable modem termination systems (CMTS) and other information transmission systems, a method for changing the interleave depth associated with each data stream is provided. This may be done dynamically, and for any subset of downstream devices such as modems. The interleave depth may be set on an individual device level. Embodiments may decrease data receiving latency on devices that do not suffer from error rates, such as caused by burst noise, while maintaining throughput on devices with high error rates.

Abstract: Embodiments of systems, apparatuses, and methods for correcting double bit burst errors using a low density parity check technique are disclosed. In one embodiment, an apparatus includes an encoder to generate a parity vector by multiplying a first version of a data vector by a matrix. The parity vector is to identify correctable double-bit burst errors in a second version of the data vector. The apparatus also includes logic to concatenate the parity vector and the first version of the data vector.

Abstract: Provided are a method, system, and article of manufacture for iterative data secret-sharing transformation and reconversion. In one aspect, data secret-sharing transformation and reconversion is provided in which each bit of an input stream of bits of data is split, on a bit by bit basis, into a pair of secret-sharing bits, and the secret-sharing bits of each pair of secret-sharing bits are separated into separate streams of secret-sharing bits. In this manner, one secret-sharing bit of each pair of secret-sharing bits may be placed in one stream of secret-sharing bits and the other secret-sharing bit of each pair may be placed in another stream of secret-sharing bits different from the one stream of secret-sharing bits. Confidentiality of the original input stream may be protected in the event one but not both streams of secret-sharing bits is obtained by unauthorized personnel.

Abstract: A method begins by a processing module receiving data for storage and interpreting the data to identify the data as redundant array of independent disks (RAID) data. The method continues with the processing module interpreting the RAID data to identify at least one of RAID block data and RAID parity data. When the RAID data includes RAID block data and RAID parity data the method continues with the processing module encoding the RAID block data in accordance with error coding dispersal storage function parameters to produce at least one set of encoded data slices and outputting the at least one set of encoded data slices to a dispersed storage network memory.

Abstract: A method begins with a slice server receiving a request to access a virtual digital data storage vault. The method continues by determining whether the virtual digital data storage vault is a first virtual digital data storage vault or a second virtual digital data storage vault. The slice server supports a portion of each of the first and the second virtual digital data storage vaults. When the virtual digital data storage vault is the first or the second virtual digital data storage vault, the method continues by determining whether the request is valid. When the request is valid, the method continues by executing the request to generate a response.

Abstract: A method of upgrading software components within a dispersed data storage network is disclosed. A list of identifiers corresponding to devices within the dispersed data storage network is assembled. Each member of the list is assigned to an upgrade set based on the devices that are reachable by the vaults associated with the device.

Abstract: Correction of structured burst errors in data is provided by a system that includes an encoder and is configured for performing a method. The method includes receiving data that includes a plurality of subsets of data. The data is encoded by an encoder using a combination of a first error correcting code and a second error correcting code. The first error correcting code is configured to provide error recovery from a structured burst error in one of the subsets of data, the structured burst error having a length less than a specified maximum length. The second error correcting code is configured to extend the first error correcting code to provide error recovery from the structured burst error in any of the subsets of data. The encoded data is output.

Abstract: A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.

Abstract: Approaches are disclosed for encoding N symbols of a sequence in parallel using an R parity symbol encoding algorithm. A first symbol matrix is added to a first parity matrix over a finite field to produce a first intermediate matrix. The first intermediate matrix is multiplied by at least a first coefficient matrix and a second coefficient matrix over the finite field to produce a second intermediate matrix. A second symbol matrix is multiplied by at least the second coefficient matrix to produce a third intermediate matrix. The second and third intermediate matrices are added to produce a revised parity matrix.

Abstract: A systematic encoder such as a systematic polar encoder for channel encoding to ameliorate the effects of noise in a transmission channel. The codeword carries a data word to be transmitted transparently, and also carries a parity part derived from the data word and a fixed word. Implementations advantageously reduce coding complexity to the order of N log(N), wherein N is the dimension of a matrix of the n th Kronecker power associated with a matrix effectively employed by the encoder.

Abstract: Disk drives are described in which blocks of data spanning multiple sectors are encoded into a plurality of codewords which are then divided into segments that are physically separated (distributed) on the disk surface over multiple sectors in a distributed codeword block so that the codewords have an improved worst case SNR in comparison to individual sectors. This results in more even SNR performance for each codeword, which improves the performance for portions of a track which have lower than the average SNR. Embodiments are described in which the distributed codeword blocks span across tracks.

Abstract: An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. The predetermined matrix is represented by a two-dimensional grid of elements. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.

Abstract: A method, apparatus and decoder for decoding cyclic code are proposed. The decoding method comprises: receiving a transmitted cyclic code; calculating the initial syndrome of the cyclic code; by using the initial syndrome and w prestored successive shift operators, calculating respectively w successive shift syndromes in a w-bit window of the cyclic code in parallel; and detecting/locating error in the cyclic code based on the obtained syndromes. The decoding apparatus corresponds to the above method. And the corresponding decoder is also proposed in this invention. The method, apparatus and decoder according to the invention could process the cyclic code within a window width and thus enhance decoding efficiency in parallel.

Abstract: Examples are disclosed for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is made as to whether the ECC encoded data includes either a single error or more than one error. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes more than one error, separate error locations are identified for the more than one error. The single error or the more than one error is corrected and the ECC encoded data is then be decoded.

Abstract: Resource mapping and coding schemes to handle bursty interference are disclosed that provide for spreading the modulated symbols for one or more transmission code words over more symbols in the time-frequency transmission stream. Certain aspects allow for the modulated symbols to be based on bits from more than one code word. Other aspects also provide for re-mapping code word transmission sequences for re-transmissions based on the number of re-transmissions requested by the receiver. Additional aspects provide for layered coding that uses a lower fixed-size constellation to encode/decode transmissions in a layered manner in order to achieve a larger-size constellation encoding. The layered encoding process allows the transmitter and receiver to use different coding rates for each coding layer. The layered encoding process also allows interference from neighboring cells to be canceled without knowledge of the actual constellation used to code the interfering neighboring signal.

Abstract: An application programming interface (API) executed by a first processing unit combines audio data samples with error code values generated for those samples. The API then causes a data stream to be opened having sufficient bandwidth to accommodate combined samples made up of audio data samples and corresponding error code values. The combined samples are then transmitted to a decoder and validation unit within a second processing unit that receives the combined data, strips the error code values and validates the audio data based on the error code values. When the error code values indicate that the audio data has been compromised, the second processing unit terminates the output of sound derived from the audio data.

Abstract: A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.

Abstract: Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=pk, k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage by ensuring that q and s are uth and vth powers respectively of a common base r, where u and v are positive integers and k f u, whereby p(k/u)v=s.

Abstract: In cable modem termination systems (CMTS) and other information transmission systems, a method for changing the interleave depth associated with each data stream is provided. This may be done dynamically, and for any subset of downstream devices such as modems. The interleave depth may be set on an individual device level. Embodiments may decrease data receiving latency on devices that do not suffer from error rates, such as caused by burst noise, while maintaining throughput on devices with high error rates.

Abstract: This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data.

Abstract: An interleaving method in a mobile communication system is provided. The interleaving method includes encoding a plurality of bits to output encoded bits in a sequence, interleaving the encoded bits based on a modulation order to generate interleaved encoded bits comprising consecutive bits having a size based on the modulation order, the consecutive bits corresponding to consecutive bits of the encoded bits, scrambling the interleaved encoded bits with a scrambling code to generate scrambled bits, and modulating the scrambled bits based on the modulation order to output at least one symbol.

Abstract: The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer.

Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Abstract: An improved method for forward error correction (FEC) in packetized networks. The proposed FEC method improves upon the conventional methods by reordering packets in advance to a certain depth. This allows for dispersing losses of groups of packets. Additionally, the method provides for a dynamic change of a current FEC scheme. In order to defend packet sequences from group losses, the FEC packets are dispersed within the packet stream in such a manner that the packets of the same sequence are located as far as possible from each other. The packets are mixed for minimization of losses and effective recovery.

Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

Abstract: A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated.

Abstract: In cable modem termination systems (CMTS) and other information transmission systems, a method for changing the interleave depth associated with each data stream is provided. This may be done dynamically, and for any subset of downstream devices such as modems. The interleave depth may be set on an individual device level. Embodiments may decrease data receiving latency on devices that do not suffer from error rates, such as caused by burst noise, while maintaining throughput on devices with high error rates.

Abstract: An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.

Abstract: Disclosed herein is a decoding device including: an extracting section, a storing section, an allocating section, and a decoding section. The extracting section acquires data containing plural code words and information other than the plural code words in one frame, and extracts the plural code words from the data every one code word. The storing section at least stores the one code word extracted by the extracting section. The allocating section sets time obtained by dividing time for the one frame by the number of code words contained in the one frame as time allocated to decoding of one code word. The decoding section decodes the code word within the time allocated by the allocating section.

Abstract: Handling burst error events with interleaved Reed-Solomon (RS) codes. A received signal, that has undergone convolutional interleaving sometime before, is received from a burst noise affected communication channel. The signal undergoes convolutional deinterleaving and the codewords generated there from undergo appropriate successive cyclic shifting to arrange burst noise affected symbols of various codewords into at least some common symbol locations. For example, at least two codewords have burst noise affected symbols in common symbol locations. An ensemble decoder jointly decodes multiple codewords during a same time period (i.e., processes multiple codewords simultaneously). By processing multiple codewords simultaneously, the ensemble decoder has greater error correction capability than a decoder that processes a single codeword at a time.

Abstract: Methods and circuits detect a burst error in a block of data bits. Coset calculator circuits calculate coset leaders from a syndrome generated from the data bits of the block. The coset calculator circuits calculate the coset leaders for each frame of the data bits. For each frame, comparator circuits input a corresponding coset leader of the coset leaders. Each comparator circuit determines, for each burst-length portion of one or more burst-length portions within the corresponding coset leader, whether the coset bits of the corresponding coset leader are zero except for the coset bits within the burst-length portion. An error-locator circuit outputs an error vector describing the burst error in the block in response to one of the comparator circuits determining that the coset bits of the corresponding coset leader are zero except for the coset bits within one of the burst-length portions within the corresponding coset leader.

Abstract: Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder.

Abstract: A radio transmitting/receiving device uses a channel interleaver with turbo codes serving as error-correcting codes to convert burst errors into random errors. The radio transmitting/receiving device, in Code Block Concatenation (15), when dividing a Transport Block into a plurality of Code Blocks, performs channel coding so that burst errors that occur during transmission are distributed to all the Code Blocks. Therefore, when burst errors occur, the errors can be uniformly distributed to all Code Blocks in a Transport Block so that no unevenness occurs in error resilience between the Code Blocks.

Abstract: A process of encoding information data in a sequence of bursts ( . . . , Bi?2, Bi?1, Bi, Bi+1, . . . ), each burst comprising a block of information symbols and a block of redundancy symbols. The block of redundancy symbols (Ri) of the current burst (Bi) of the sequence is generated by calculating a sum of a series of coding values relating to a series of bursts (Bi?2, Bi?1), each coding value of the series of coding values being obtained by a respective coding function applied to the block of information symbols of the corresponding burst of the series of bursts.

Abstract: Techniques to decode tail biting convolutional code are disclosed. A plurality of sets for a trellis may be determined. Each set may include a first stage and a second stage of the trellis. Path metrics for each state in a set may be determined when the first stage and the second stage have a same state. The path metrics may be compared to determine a state with a minimum path metric. Bits from the state with the minimum path metric may be output. Other embodiments are described and claimed.

Abstract: Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).

Abstract: The present invention is related to systems and methods for applying a data decode algorithm to different rotations or modifications of a decoder input as part of data processing.

Abstract: A method is dedicated to encoding data that must be transmitted by means of a wave-based transmission infrastructure, and comprises i) a step consisting of creating in parallel M first matrices having T rows and C columns with subsets of data from B successive received bursts, the subsets of data from each burst being distributed within at least two successive first matrices, ii) a step consisting of creating in parallel M second matrices each having T rows and N columns with parity symbols resulting from encoding the data that is respectively contained in the rows of each of the M first matrices, iii) a step consisting of creating in parallel M first matrices having K rows and C columns with parity symbols resulting from encoding the data that is respectively contained in the columns of each of the M first matrices, and iv) a step consisting of distributing by interlacing, firstly, J subsets of parity symbols from each second matrix into J successive sets, and secondly P subsets of parity symbols from each t