Abstract: An error correction code includes a separate error code portion for each of two or more separate burst erasure durations (or burst error durations). For each burst erasure duration, the code can be employed to recover from the burst erasure with a different delay time. Each error code portion has a particular parameter for burst duration (B) and delay (T), meaning that the code can be used to recover from a burst erasure of duration B with delay T. Each error code portion is based on separating the source symbols into sub-symbols and diagonally interleaving the sub-symbols based on the (B,T) parameters for the error code portion. Accordingly, different burst erasures are recovered from with different delays.

Abstract: There are provided a content data transmission method, device, and program that minimize serious disturbances in reproduced content on the reception side, caused by a transmission error of encoded data, without sending feedback information from the reception side to the transmission side. When an encoder creates encoded data to be distributed, the encoder creates plural items of encoded data at the same time or creates FEC data at the same time in advance and, when storing the data in a file, stores the data as if the data were one item of encoded data. When a distribution server distributes the data using the file, the plurality of items of encoded data are automatically distributed at the same time and the FEC data is distributed. A client receives the plurality of items of encoded data or the FEC data to reduce the probability of data shortage due to a packet loss and, as a result, the deterioration in the image quality and the audio quality is reduced.

Abstract: A method of storing DVB-H data from a DVB-H data burst, the method comprising: identifying erasures in the data burst; and storing non-erasure data from the data burst in memory locations of a memory that would be used to store erasures.

Abstract: A method and apparatus for decoding received digital data representing video, audio, information or a combination thereof. After a forward error correction (FEC) frame sync lock is detected, a counter is incremented corresponding to the number of identical control words decoded from the received data. If the number of identical control words is above a threshold value, the control word is used to operate the decoder in a mode corresponding to the control word. Otherwise, the system repeats the operation of determining whether a FEC frame sync lock is detected.

Abstract: Management of requests from a host to an external storage medium. An execution queue stores commands to be executed, and each command corresponds to a request from the host for data. A holding queue stores executed commands until receipt of an acknowledgment from the host that the host has, e.g., received the data corresponding to the command from the external storage medium. An outgoing queue stores acknowledged commands and has a maximum storage limit. A counter is provided, and a separate logic block increments the counter when a command is stored in the execution queue and decrements the counter when an acknowledged command is deleted from the outgoing queue. The separate logic disables execution of commands stored in the execution queue when the value of the counter equals the maximum storage limit of the outgoing queue.

Abstract: In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.

Abstract: When memory cells enter a data holding mode, a control circuit of a semiconductor memory device reads out a plurality of data from the memory cells to generate and store a check bit for error detection and correction, and performs a refresh operation in a period within an error occurrence allowable range of an error correcting operation performed by an ECC circuit by using the check bit. Before a normal operation mode is restored from the data holding mode, the control circuit performs control such that an error bit of the data is corrected by using the check bit. In an entry/exit period, read and write are performed by a page operation.

Abstract: A system for transmitting a digital broadcasting signal includes a Reed-Solomon encoder that encodes a dual transport stream including a normal stream and a turbo stream to obtain an encoded dual transport stream; an interleaver that interleaves the encoded dual transport stream to obtain an interleaved dual transport stream; and a turbo processor that detects the turbo stream from the interleaved dual transport stream to obtain a detected turbo stream, encodes the detected turbo stream to obtain an encoded turbo stream, stuffs the encoded turbo stream back into the interleaved dual transport stream to obtain a reconstructed dual transport stream, and compensates the reconstructed dual transport stream for a parity error due to the encoded turbo stream to obtain a parity-compensated dual transport stream.

Abstract: An assignment scheme exploits the Media Access Control (MAC) layer protocol features under various MAC layer call scenarios. In one embodiment, the Hamming distance between pairs of critical Data Units are assigned to codewords with a minimum distance of dmin2=8 bits, thereby increasing the hard decision error correcting capability from 1 bit to 3 bits when deciding between these pairs of Data Units. The method for assigning data unit identification (DUID) codes by a radio operating within a wireless communication system includes determining by the radio whether an expected burst is a 4 Voice Burst with Encryption Synchronization Signaling (4V); when the expected burst is 4V, decoding the DUID within the received burst using an increased minimum distance; and when the expected burst is not 4V, decoding the DUID within the received burst using a minimum distance.

Abstract: A turbo stream processing device and method. A turbo stream processing device includes a turbo stream detector to receive a dual transmission stream in which a turbo stream and a normal stream are multiplexed, and to detect the turbo stream; an outer encoder to encode the turbo stream; an outer encoder to interleave the turbo stream which is encoded at the outer encoder; and a turbo stream stuffer to reconstruct the dual transmission stream by stuffing the interleaved turbo stream into the dual transmission stream. Accordingly, the reception performance can be enhanced by more robustly processing the turbo stream in the dual transmission stream.

Abstract: A system and method are provided to detect an extended error burst in a data interface. An original error burst has a given length prior to or during transmission. Data transmission processing can extend the original error burst beyond its original length to become an extended error burst with an effective length greater than the original error burst length. Such data transmission processing can include: de-interleaving data on a multi-lane data interface; feedback from a Decision Feedback Equalizer (DFE) receiver; and/or block line decoding, such as 8B/10B block line code decoding. An extended error burst detector can include a suitable error detecting code, such as an r-bit cyclic redundancy check (CRC) code developed in relation to known extended error burst patterns, to detect all extended error bursts based on an up to r-bit original error burst. The detector can also detect error bursts that are not extended beyond the original error burst length.

Abstract: A method for reducing data loss includes a first computing step for computing an intermediate result for each redundancy information entity of a redundancy set by processing respectively associated data information entities of a given data set on at least two main diagonals of a parity check matrix representing an error correction coding scheme. The method further includes a second computing step for computing the information content of the respective redundancy information entity dependent on the respective intermediate result.

Abstract: A wideband code division multiple access (W-CDMA) user equipment (UE) operating in frequency division duplex mode for receiving data over at least one of a plurality of high speed (HS) shared control channels (SCCHs) is disclosed. The UE includes means for monitoring the plurality of HS-SCCHs; means for receiving a packet over at least one of the plurality of HS-SCCHs; and means for determining whether a UE identification is present in the packet and whether a circular redundancy code (CRC) of the packet is correct by processing a mask field. The mask field has an N-bit CRC modulo 2 combined with an N-bit UE identification.

Abstract: A method and apparatus for decoding data is provided herein to show how to turbo decode LDPC codes that contain a partial dual diagonal parity-check portion, and how to avoid memory access contentions in such a turbo decoder. During operation, a decoder will receive a signal vector corresponding to information bits and parity bits and separate the received signal vector into two groups, a first group comprising signals corresponding to the information bits and one or more parity bits, a second group comprising a remainder of the parity bits. The first group of received signals is passed to a first decoder and the second group of received signals is passed to a second decoder. The decoders are separated by an interleaver and a deinterleaver. Iterative decoding takes place by passing messages between the decoders, through the interleaver and the deinterleaver, and producing an estimate of the information bits from the output of the first decoder.

Abstract: A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. Each enhanced data packet includes an adaptation field in which the pre-processed enhanced data are inserted. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction, and the trellis encoder performs trellis encoding on the RS-coded data packets.

Abstract: A MIMO transmitter comprises a scrambler; an encoder parser responsive to the scrambler; a forward error correction encoder responsive to the encoder parser, wherein the encoder applies a parity check matrix derived from a base matrix; an interleaver responsive to the forward error correction encoder; a QAM mapping module responsive to the interleaver; an inverse fast Fourier transform module responsive to the QAM mapping module; and an output module responsive to the inverse fast Fourier transform module.

Abstract: A Reed-Solomon (RS) decoding apparatus having high error correction capability and a method thereof are provided. The apparatus includes: error location and analysis polynomial generating units for performing a modified Euclid algorithm by receiving syndrome data upon receipt of an enable signal, and suspending input of the syndrome data and outputting error location polynomial data and error analysis polynomial data by executing the modified Euclid algorithm independently upon receipt of a disable signal; a controlling unit for controlling the error location and analysis polynomial generating unit and the input of the syndrome data; and switching units for providing the syndrome data to corresponding error location and analysis polynomial generating unit upon receipt of the enable signal and controlling the input of the syndrome data upon receipt of the disable signal. The number of the switching units is identical to that of the error location and analysis polynomial generating units.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: Methods and techniques are disclosed for correcting the effect of cycle slips in a coherent communications system. A signal comprising SYNC bursts having a predetermined periodicity and a plurality of known symbols at predetermined locations between successive SYNC bursts is received. The received signal is partitioned into data blocks. Each data block encompasses at least data symbols and a set of check symbols corresponding to the plurality of known symbols at predetermined locations between a respective pair of successive SYNC bursts in the signal. Each data block is processed to detect a cycle slip. When a cycle slip is detected, the set of check symbols of the data block are examined to identify a first slipped check symbol, and a phase correction applied to data symbols of the data block lying between the first slipped check symbol and an end of the data block.

Abstract: Methods, apparatuses, and systems to determine whether a transmission signal block was fully transmitted are described herein. The determination may be made at least in part by calculating one or more bit error probabilities for one or more to be transmitted bursts of the transmission signal block.

Abstract: A method and system for managing memory using Hybrid Automatic Repeat Request in a communication system is provided. The method includes storing a retransmitted burst in a memory. The retransmitted burst includes plurality of bits. One or more of memory address of the retransmitted burst and the information corresponding to the retransmitted burst is recorded in a location table. The location table records memory addresses and the information corresponding to a plurality of bursts stored in the memory. The method further includes determining one or more preceding bursts corresponding to the retransmitted burst stored in the memory using location table. Thereafter, a combined burst is generated using the retransmitted burst and one or more preceding burst, if one or more preceding bursts corresponding to the retransmitted burst are stored in the memory. The combined burst includes the plurality of bits.

Abstract: A computer-readable storage element has code stored thereon that programs a processing device within a communication device to implement a method. The method includes: receiving a plurality of bursts and detecting a failure to receive a preceding header burst; extracting embedded data from the plurality of bursts; determining from the embedded data whether the plurality of bursts comprises valid voice bursts; and when the plurality of bursts comprises valid voice bursts, generating at least one header burst using the embedded data, and transmitting the at least one header burst and the voice bursts.

Abstract: Handling burst error events with interleaved Reed-Solomon (RS) codes. A received signal, that has undergone convolutional interleaving sometime before, is received from a burst noise affected communication channel. The signal undergoes convolutional deinterleaving and the codewords generated there from undergo appropriate successive cyclic shifting to arrange burst noise affected symbols of various codewords into at least some common symbol locations. For example, at least two codewords have burst noise affected symbols in common symbol locations. An ensemble decoder jointly decodes multiple codewords during a same time period (i.e., processes multiple codewords simultaneously). By processing multiple codewords simultaneously, the ensemble decoder has greater error correction capability than a decoder that processes a single codeword at a time.

Abstract: Disclosed is a method and apparatus for completely recovering received data with high reliability using LDPC codes without short-sized cycles in a digital communication system using an error-correcting code. The method includes performing exponent conversion of a predetermined number of exponent matrixes stored in advance in a memory so as to generate new exponent matrixes based on the exponent conversion, and generating new LDPC codes using the new exponent matrixes.

Abstract: A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form. data symbols; and an arranging (interleaving) part arranges(interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged(interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.

Abstract: The errors that may occur in transmitted numerical data on a channel affected by burst errors, are corrected via the operations of: ordering the numerical data in blocks each comprising a definite number of data packets; generating for each block a respective set of error-correction packets comprising a respective number of correction packets, the respective number identifying a level of redundancy for correcting the errors; and modifying dynamically the level of redundancy according to the characteristics of the bursts and of the correct-reception intervals between two bursts. Preferential application is on local networks, such as W-LANs for use in the domestic environments.

Abstract: A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period.

Abstract: An erasure forecasting system includes a control module, an erasure feed-forward module, and an erasure decoder. The control module selects erasure parameters and determines error-detection thresholds for forecasting erasure in an input signal. The erasure feed-forward module receives the input signal, forecasts erasure in the input signal, generates an erasure feed-forward signal based on the erasure parameters and the error-detection thresholds, and generates codewords based on the erasure feed-forward signal and the input signal. The erasure decoder determines that the input signal is one of erroneous and not erroneous based on the erasure feed-forward signal.

Abstract: Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)?K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)?K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.

Abstract: A digital broadcasting system transmitting and receiving a broadcast stream created from a broadcast source. The system includes a hierarchical coding unit (2) coding the broadcast source depending on a characteristic of the broadcast source and generating, from the coded broadcast source, a first layer code and a second layer code which can respectively be used for reproduction of the broadcast source and includes a synthesis unit (5) generating data bursts, each including the generated first and second layer code.

Abstract: A transmitter apparatus wherein a simple structure is used to successfully suppress the degradation of error rate performance that otherwise would be caused by fading or the like. There are included encoding parts (11—1-11—4) that encode transport data; a mapping part (3304) that performs such a mapping that encoded data sequentially formed by the encoding parts (11—1-11—4) are not successively included in the same symbol, thereby forming data symbols; and a symbol interleaver (3301) that interleaves the data symbols. In this way, a low computational complexity can be used to perform an interleaving process equivalent to a bit interleaving process to effectively improve the reception quality at a receiving end.

Abstract: In an exemplary embodiment, a base station includes an antenna for transmitting signals on a downlink to a plurality of user devices. The base station also includes a processor, and memory in electronic communication with the processor. Interleaving instructions are stored in the memory. The interleaving instructions are executable by the processor to interleave coded data in accordance with an interleaving algorithm in order to generate interleaved data. The interleaving algorithm is configured to accommodate use of different transmission bandwidths for data transmission. OFDMA processing instructions are also stored in the memory. The OFDMA processing instructions are executable by the processor to perform OFDMA processing on the interleaved data. The OFDMA processing facilitates the use of a varying number of sub-carriers for channel transmission.

Abstract: A receiving system and a data processing method are disclosed. The receiving system includes a signal receiving unit, an FIC handler, a manager, and a decoding unit. The signal receiving unit receives multiple Reed-Solomon (RS) frames comprising desired mobile service data for multiple ensembles and fast information channel (FIC) data including an indicator field, wherein the indicator field indicates whether or not the desired mobile service data are delivered through the multiple ensembles. The FIC handler obtains the indicator field from the FIC data. The manager determines at least one ensemble based upon the indicator field. And, the decoding unit decodes IP streams of the desired mobile service data from the RS frame of the determined ensemble.

Abstract: Modification of the prior-art M/H system to better suit transmission of internet-protocol (IP) transport packets includes a standard codeword length for a plurality of various options for transverse Reed-Solomon coding of M/H data, which options offer different degrees of forward-error-correction capability. A 235-byte standard codeword length for TRS coding of M/H data allows extending the FIC-Chunks in the Fast Information Channel signaling to double length so as to substantially increase the capability of such signaling to convey information concerning M/H services. In some transmitter apparatus constructed in accordance with aspect of the invention the TRS encoder in the M/H Frame encoder is modified for transmitting the parity bytes of TRS codewords before, rather than after, the data bytes of those TRS codewords.

Abstract: Apparatus and methods are provided to correct burst errors from a communication channel. Embodiments may include correcting burst errors in received data using a decoder configured as a Meggitt decoder with an additional selection criterion to correct a burst error having a length larger than the code error correction capability.

Abstract: Holographic recording drives encode data for recording into a holographic medium. The steps comprise run length limited encoding three bytes of data into 5×5 matrix information, the data subject to a 4-byte error correction code; and providing the 5×5 matrix information to a spatial light modulator (SLM), as a portion of a two-dimensional pixel matrix of the spatial light modulator, for recording into a holographic image on the holographic medium.

Abstract: According to a first aspect, the invention relates to a method for protection against errors in a transmission system in which a data flow includes a plurality of time-divided base flows to be transmitted as bursts, characterised in that it comprises, for one base flow, calculating a direct inter-burst error correction, and associating the calculated correction with bursts of the flow in order to provide a protection against the total or partial loss of one or more bursts of the flow.

Abstract: A system, an apparatus and a method for transmitting/receiving data coded by a low density parity check matrix code are provided. The apparatus for transmitting data coded by a low density parity check code includes: a low density parity check encoder for encoding input data based on the low density parity check code; and a bit puncturer for puncturing columns in an order of columns which least degrade a performance caused by puncturing in the low density check code according to a code rate of an output data. Accordingly, the low density parity check code having superior performance can be implemented to the next generation mobile communication system supporting various code rates.

Abstract: A receiver for a mobile communication system includes a channel equalizer for receiving a burst and generating a soft decision output associated with the burst, a soft decision correction circuit follows the channel equalizer and a decoder receives and decodes a block of bursts. The soft decision correction circuit calculates a correction factor based on the soft decision output for the burst and applies the correction factor to the burst prior to the burst entering the decoder.

Abstract: A circuit is provided for performing interleaving and deinterleaving functions in a digital communication system. The circuit includes a single-port memory that reads first data units from a first interleaved sequence of address locations to generate a first data stream and that writes second data units from a second data stream to the address locations. A first address generator module communicates with the single-port memory and generates a first interleaved sequence of addresses that correspond to the address locations and correspond to one of an interleaving function and deinterleaving function between the first data stream and the second data stream.

Abstract: A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further including, an address controller that causes data to be de-interleaved when read from the buffer and data to be interleaved when written to the buffer.

Abstract: A system and method for erasure flagging for errors-and-erasures decoding in storage devices includes determining a deviation measure between a read/write head position relative to a track of symbols in storage media. A reliability value is determined for the symbols based on the deviation measure. Flagging the symbols with a reliability value below a threshold as erasures is performed. The symbols are decoded using errors-and-erasures decoding in an iterative procedure.

Abstract: Methods, software, circuits and systems involving a low complexity, tailbiting decoder. The method relates to appending and/or prepending data subblocks to a serial data block, decoding and estimating starting and ending states for the serial data block, and when the starting and ending states are not identical, iterating the decoding and estimating step(s) and (eventually) disallowing at least one starting and/or ending state. The circuitry generally includes a buffer, tailbiting logic configured to append and/or prepend a subblock to the serial data block, a decoder configured to (i) decode the serial data block and (ii) estimate starting and ending states for the serial data block, and iteration logic configured to instruct the decoder to repeat the decoding and starting/ending state estimating functions when the starting and ending states are not identical.

Abstract: A wireless communications apparatus according to the present invention includes a scheduler which allocates, to a user apparatus, at least one resource block included in a system bandwidth; an interleaver which rearranges an order of bits within a bit sequence according to a specified pattern; a unit which creates a transmit symbol including the interleaved bit sequence; and an interleaving-pattern determining unit which determines a range of the bit sequence to be rearranged based on a number of the resource blocks, a data modulation scheme, and a channel encoding rate, determines a rearranging pattern according to the range, and communicates the determined pattern to the interleaver.

Abstract: An interleaver parameter generator circuit used to calculate and generate on an as needed basis interleaver parameters for interleaving blocks of information of varying lengths in accordance with a pseudorandom pattern defined by the 3GPP standard. The interleaver parameter generator circuit calculates and generates the defined interleaver parameters based on an input parameter that represents the length of the block of information to be interleaved. At least one of the defined parameters is calculated and generated using a decomposed form of its definition. The interleaver parameter generator circuit uses well known circuit blocks such as multipliers, subtractors, Compare-and-Select circuits and other circuits to calculate and generate the defined parameters.

Abstract: Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of bit failures in a line, respectively. The updating of first and second counters after a third time correction of bit failure in the line is disabled.

Abstract: Devices, software, and methods measure a burstiness of packet loss episodes in transmissions of voice data through networks. At least one burstiness statistic is determined to quantify how the lost packets are distributed with respect to the received packets within the sequence. The burstiness statistic is optionally used to determine a figure of merit, which in turn can be used to give a grade for predicting how well a packet loss concealment scheme will work.

Abstract: A channel interleaving method and apparatus in a communication system using a low density parity check (LDPC) code. Upon receipt of information data bits, an encoder encodes the information data bits into an LDPC codeword using a predetermined coding scheme. A channel interleaver interleaves the LDPC codeword according to a predetermined channel interleaving rule. A modulator modulates the channel-interleaved LDPC codeword into a modulation symbol using a predetermined modulation scheme.

Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits, wherein the H-matrix is capable of being partitioned into a first matrix and a second matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1, wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint, and outputting the sequence of encoded bits.

Abstract: A system, method and machine-readable medium for pruning an S-random interleaver starting with an interleaver permutation having N elements and alternating between invalidating the last element of the interleaver permutation and invalidating the last element of a corresponding inverse interleaver permutation until the interleaver permutation has K elements, K being less than N, the method being characterized by the use of a reference vector having N flags and comprising: storing a value in an element of the reference vector corresponding to the value of the each element invalidated in the interleaver permutation.