Abstract: A method for decoding multiword information comprises steps (a) to (h). In step (a), a multiword information cluster including high protective words and low protective words is provided, wherein the multiword information, high protective words and low protective words can be ECC data, BIS data and LDC data, respectively. In step (b), the low protective words are partitioned into multiple groups. In step(c), the low protective words are de-interleaved, so as to generate a low protective word cluster including multiple segments corresponding to the multiple groups. In step (d), any error of the low protective words is detected, so as to generate segment erasure indicators with localities. In step (e), the low protective words and the segment erasure indicators are stored into a first memory, e.g., a DRAM. In step (f), the segment erasure indicators are stored into a second memory, e.g., a SRAM. In step (g), erasure bits of the low protective word are generated based on the segment erasure indicators.

Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.

Abstract: If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations which can be performed is restricted. To solve the above problems, the present invention can record data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention.

Abstract: A receiver is to receive an encoded data block that was encoded using a convolutional encoder and includes source bits and error detection bits. The receiver may include a Viterbi decoder, a de-mapper and an error detection unit. The error detection unit is to determine whether an error correction capability of the Viterbi decoder is sufficient to recover the source bits from the encoded data block. The Viterbi decoder is to decode the encoded data block only if the encoded data block is not free of errors and if the error correction capability of the Viterbi decoder is sufficient to recover the source bits from the encoded data block.

Abstract: A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.

Abstract: A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving method is improved by sensing generation of an internal address corresponding to an embedded address, and generating a redundancy flag signal, such that the embedded address is an address preceding the address of the memory cell of the normal cell array to be repaired by at least one clock.

Abstract: A Post-Viterbi processor generates a plurality of candidate codewords based on a plurality of dominant error patterns for a particular communication channel. The Post-Viterbi processor selects one among the candidate codewords as a corrected codeword upon determining that the candidate codeword is error free.

Abstract: A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with a prescribed subcarrier frequency. Each code word fragment includes a prescribed number of code word bits based on a prescribed modulation of the interleaved data stream, and the code word bits for each code word fragment are written into respective selected locations of the corresponding memory bank based on the prescribed modulation and the corresponding prescribed subcarrier frequency. Write enable signals, bit selection signals, and address signals for each of the code word bits are generated based on applying logical operands to a cascaded sequence of successively delayed signals synchronous with a local clock signal. The deinterleaver module outputs deinterleaved data from the memory banks based on parallel output of the respective stored code word bits from a selected address of the memory banks.

Abstract: Techniques for detecting and correcting burst errors in data bytes formed in a two-level block code structure. A second level decoder uses block level check bytes to detect columns in a two-level block code structure that contain error bytes. The second level decoder generates erasure pointers that identify columns in the two-level block structure effected by burst errors. A first level decoder then uses codeword check bytes to correct all of the bytes in the columns identified by the erasure pointers. The first level decoder is freed to use all of the codeword check bytes only for error byte value calculations. The first level decoder does not need to use any of the codeword check bytes for error location calculations, because the erasure pointers generated by the second level decoder provide all of the necessary error locations. This techniques doubles the error correction capability of the first level decoder.

Abstract: Error bursts are detected and corrected in a communication system using shortened cyclic codes, such as shortened Fire codes. Data is loaded into a first error syndrome register and a second error syndrome register. The data in the registers may be evaluated to determine if the data bits contain a correctable error. Shortened zero bits are shifted into the second error syndrome register. A number of zero bits are shifted into the first error syndrome register to trap an error burst pattern in the data. A determination is made as to the number of zero bits shifted into the second error syndrome register to trap the location of the error burst in the data. Using the number of zero bits shifted into the second error syndrome register and the error burst pattern, the error in the data is located and corrected.

Abstract: Error bursts are randomized by an interleaver which makes use of “set leaders” to generate permutation indices. The permutation indices are used to route bits from initial positions in an input bit stream to re-arranged or randomized positions in an output bit stream. When the output bit stream is then transmitted and subsequently received by a de-interleaver which returns the received bits to their initial, pre-randomized positions, the resulting received signal has an acceptable bit error rate.

Abstract: To shorten a time required for a decoding process of a turbo codes without an increase in an operating frequency of the decoder by making concurrent operations of two soft-output decoders possible, the present invention provides soft-output decoders (101, 102) for outputting a reliability information likelihood, interleavers (103, 105) for interleaving transmission information to supply to the soft-output decoder, interleaver (104, 106) for interleaving a reliability information likelihood to supply to the soft-output decoder, and deinterleavers (107, 108) for deinterleaving the reliability information likelihood to supply to the soft-output decoder. Since these elements are constructed as two circuits having the same configuration and two soft-output decoders are operated concurrently in an iterative decoding process for a second time et seq. in the iterative decoding process of the turbo codes, a processing time required for the decoding process for the second time et seq. can be reduced by half.

Abstract: An error-correction coding method and an error-correction decoding method utilize error detection and error correction for an audio signal when a video signal and the audio signal are multiplexed and transmitted by a DVI. After an error correction code is added to each sample (sample data unit) of the digital audio signal, n continuous (n: integer equal to or larger than 2) pieces of the samples (sample data units) of the digital audio signal, to which error correction codes are added, are interleaved to generate a coded audio signal.

Abstract: An error-correction coding method and an error-correction decoding method utilize error detection and error correction for an audio signal when a video signal and the audio signal are multiplexed and transmitted by a DVI. After an error correction code is added to each sample (sample data unit) of the digital audio signal, n continuous (n: integer equal to or larger than 2) pieces of the samples (sample data units) of the digital audio signal, to which error correction codes are added, are interleaved to generate a coded audio signal.

Abstract: A decoder for decoding data from a communication channel includes a parity check matrix including M tiers, wherein M?B, Dmin=B*M for M=1 . . . E or B*M?Dmin?F for M>E. Dmin is the minimum Hamming distance and tc=M, wherein tc is a column weight. The parity check matrix includes no period-four cycles. B, Dmin, E, F and M are integers. A soft channel decoder is configured to decode data. A soft linear block code decoder is configured to decode data decoded by the soft channel decoder in accordance with the parity check matrix.

Abstract: A signal separation circuit (11) normally outputs a main signal, but outputs a TMCC signal when an error detection and correction unit (4) sets a completion flag. Main signals are input via a selection circuit (3) to an execution unit (4), where error correction of the main signals is performed. The error-corrected main signals are supplied via a switching circuit (8) to a first data output circuit (9). Meanwhile, TMCC signals are input via the selection circuit (3) to an execution unit (4), error correction is carried out to the TMCC signals. The error-corrected TMCC signals are supplied via switching circuit (8) to a second data output circuit (10).

Abstract: A computationally efficient method and system for decoding shortened cyclic codes is presented. The increase in computational efficiency is achieved by improvement of the syndrome calculation step. Two embodiments of the present invention are described; the first embodiment is optimized for a hardware implementation and the second embodiment is optimized for a Digital Signal Processor (DSP) implementation. The present invention is applicable to decoding of all the binary shortened cyclic codes, including Fire codes used for Coding Scheme-1 (CS-1) for GSM.

Abstract: The present invention is a method and system for encoding digital data. The encoding system proceeds the step of calculating error detection code and the step of scrambling the main data at the same time to decrease times for the access to the first memory. The present invention comprises a second memory. The encoding system can access more than one recording column per-time, which further decreases times for the access to the first memory.

Abstract: A method and system for maintaining communication of data in a communication link between a transmission site and a reception site during a momentary disruption of the communication link includes storage of data during the disruption, and optionally both prior to and subsequent to the disruption, to enable communication subsequently to the disruption. In one embodiment, data is stored over an interval of time longer than the disruption and centered on the disruption, and is scrambled prior to communication between the transmission site and the reception site. Unscrambling of the data in a received sequence and application of error-correction code to the received sequence regains information which would have been lost in the disruption. Use may also be made of buffers at both of the sites for saving data which was to be transmitted during the disruption, and communicating the data to the end-user buffer subsequent to the disruption.

Abstract: An error correction algebraic decoder and an associated method correct a combination of a B-byte burst of errors and t-byte random errors in a failed sector, by iteratively adding and removing an erasure (N?B) times until the entire failed sector has been scanned, provided the following inequality is satisfied: (B+2t)?(R?1), where N denotes the number of bytes, B denotes the length of the burst of errors, t denotes the total number of random errors, and R denotes the number of check bytes in the failed sector. This results in a corrected sector at a decoding latency that is a generally linear function of the number of the check bytes R, as follows: Decoding Latency=5R(N?B).

Abstract: A recording/reproducing apparatus records and reproduces, over a partial response channel, a recording signal produced by encoding data according to a convolutional code and reproduces the data from a reproduction signal by iterative decoding using likelihood information. A burst error detector detects a burst error part in the reproduction signal. A substituting part substitutes, for a sampling value included in the burst error part, a predetermined value according to a detected result of the burst error detector.

Abstract: Architecture for enhancing the encoding/decoding of information of a channel. A stream of incoming information bits are arranged into a first array of information bits. The first array of information bits are processed into a first code of bits, which bits form a plurality of first code words having a minimum distance to neighboring error events. Selected bits of the first code are rearranged into a second array of bits by intermittent successive rotations of the selected bits of the first code. A second code is then generated from the second array of bits to increase the minimum distance to the neighboring error events.

Abstract: A communication device capable of correcting a burst error exceeding a correcting capability of an error correcting code by only transmitting one packet. With respect to data to be transmitted, a frame generating section 22 generates a frame for which an error detecting process, etc., is performed. A frame dividing section 23 divides the generated frame, by a predetermined number, into a plurality of divided frames. A transmission control section 24 generates a packet in which the plurality of divided frame are copied predetermined times. A transmitting section 25 sends the packet to a receiver. A receiving section 35 receives the packet transmitted from a transmitter. A reception control section 34 divides the received packet by the predetermined number. A frame reconstructing section 33 reconstructs the frame by assembling the divided frames in predetermined order. A frame processing section 32 performs an error correcting process, etc., for the reconstructed frame.

Abstract: A method of transmitting convolutionally encoded data with separate, independent and looped encoding over at least one data portion. The data is distributed over one or more cycles, and a plurality of cycles can be grouped into packets for discontinuous transmission if necessary. Weighted decoding is effected independently and cycle by cycle: it starts at a robust location, with a relatively high likelihood, and terminates at a weak location, with a weak likelihood, ignoring the concept of time. This limits the size of the packets of errors and prevents the propagation of packets of errors due to scrambling. Independent encoding and decoding of data can be effected without exchanging parameters between cycles and the parameters of each cycle (size, redundancy, constraint length) can be separate. Different degrees of protection and time-delay are permitted as a function of the nature of the data to be transmitted (voice, digital data, signaling, etc.).

Abstract: A system and method is provided for interleaving data in a communications device. The system includes a memory for storing symbols of a data block, a read module and a write module, each of which is coupled to the memory. The system also includes a interleaving logic module coupled to the read and write modules. The interleaving logic module determines an interleaving sequence comprising a sequence of memory addresses. Each memory address is then communicated sequentially to the read and write modules. When the read module receives the address, the read module reads the stored data symbol. When the write module receives the address, the write module writes a symbol from a next data block to the vacated address. The interleaving logic module repeats these steps until every symbol of the stored block has been read and every symbol of the next data block has been written to memory.

Abstract: To interleave a binary sequence a represented by the polynomial a ? ( x ) = ? i = 0 n - 1 ? a i ? x i , where n=R.M with R?M, i being an integer which may be written i=r.M+c, r and c being integers, r?0 and c ? [0, M?1], there is obtained, from the sequence a, an interleaved binary sequence a*. The interleaved binary data sequence a* represented by the polynomial a * ? ( x ) = ? i = 0 n - 1 ? a i ? x i * where i*=[r?h(c)].M+c mod n, the h(c) being obtained by the choice of an M-tuple h0=[h0(0), . . . , h0(M?1)] of non-negative integers less than R?1 such that, given a predetermined set ? of circulating matrices P of dimension M×M, for any matrix P of ?, the residues modulo R of the components of the vector h0.P are not nil; and the corresponding choice of an M-tuple h obtained from h0 by the application of a permutation moving h0(c) to position L×c mod M, the integer L being relatively prime with M.

Abstract: Errors in a first data signal of a first error correction code system in a reproduced signal are corrected to get first correction-resultant data. Errors in a second data signal of a second error correction code system in the reproduced signal are corrected to get second correction-resultant data. All address information pieces in the second correction-resultant data for every error correction block are subjected to error checks. When at least one of all the address information pieces is correct, a descramble initial value is set in response to the correct address information piece. When all the address information pieces are erroneous, a correct address information piece is estimated from an address information piece associated with a previous error correction block and the descramble initial value is set in response to the estimated correct address information piece. The first correction-resultant data are descrambled in response to the descramble initial value.

Abstract: An interleaver (11b) for filling an interleaver matrix (51) used in interleaving a packet of bits for transmission as symbols via a wireless communication channel in a wireless communication system (11 12) including a modulator (11c), the interleaver (11b) having a number of rows (or columns, depending on whether bits are pulled column-wise or row-wise for encoding as symbols by the modulator) that is not divisible by the number of bits in a symbol, but having at least as many bits as in a packet, and so having, unavoidably, more elements than there are bits in a packet.

Abstract: A software implementation of a Reed-Solomon decoder placing a constant load on the processor of a computer. A Berlekamp-Massey Algorithm is used to calculate the coefficients of the error locator polynomial, a Chien Search is used to determine the roots of the error locator polynomial, and a Forney Algorithm is used to determine the magnitude of the errors in the received digital code word. Each step is divided into m small tasks where m is the number of computational blocks it takes to read in a code word and the processor can pipeline or parallel process one task from each step each time a block is read.

Abstract: A data transmission system is provided for transmitting user data to and receiving data from a communication channel, including a parity check matrix having M tiers, wherein M?2, Dmin=2*M for M=1 . . . 3 or 2*M?Dmin?6 for M>3, wherein Dmin is the minimum Hamming distance, tc=M, wherein tc is the column weight, and cycle?4=0. A linear block encoder encodes the user data in response to the parity check matrix, and a transmitter transmits an output of the linear block encoder to the communication channel. A soft channel decoder decodes data, and a soft linear block code decoder to decode data decoded by the soft channel decoder in response to the parity check matrix.

Abstract: A syndrome S is found from a received information D and a parity check matrix for correcting burst errors up to b bits. The syndrome S is inputted to p sets of burst error pattern generation circuits that correspond to information frames overlapping each other by (b?1) bits and each having a length of 2b bits. If a burst error is included entirely in any one of the p sets of burst error pattern generation circuits, then the burst error pattern is outputted. An error pattern calculation circuit executes OR respectively on overlapping bits output from the error pattern generation circuits. By executing exclusive OR on an output of the error pattern calculation circuit and received information D, corrected information Ds is obtained. As a result, a burst error in the received information can be detected and corrected.

Abstract: A memory optimized system and method for data interleaving/de-interleaving are disclosed. A data interleaver/de-interleaver may be implemented with a memory device and an improved data interleaver/de-interleaver. The improved data interleaver/de-interleaver may be implemented with a controller, a first array, and a second array. The first array identifies a maximum depth value for each of a plurality of memory segments responsive to both a block data length and the desired interleaving/de-interleaving depth. The second array comprises an index associated with each of the plurality of memory segments that may be used to derive write and read addresses.

Abstract: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The write module is configured to receive a burst of data and write blocks of data from the burst into the memory. The write module is also configured to provide control information to the read logic. The control information includes a rolling burst counter and a burst profile bank identifier for each block. If interleaving is activated, the control information also includes information pertaining to how the read module should interleave the block. If interleaving is not activated, the control information also includes the byte length size of the burst. The read module reads blocks of data from memory in either an interleaved fashion or a non-interleaved fashion in accordance with the control information.

Abstract: An apparatus encodes an input information bit stream comprised of 5 bits into a (11,5) codeword comprised of 11 coded symbols. The apparatus comprises a Reed-Muller encoder for encoding the input information bit stream into a first order Reed-Muller codeword comprised of 16 coded symbols; and a puncturer for selecting a second coded symbol position or a third coded symbol position out of the 16 coded symbols constituting the first order Reed-Muller codeword, puncturing the coded symbols at intervals of 3 symbols beginning at the selected position, and thus outputting an optimal (11,5) codeword.

Abstract: An effective data multiplexing method wherein an error correction ability is exerted at the maximum so that data transmission quality is improved and a data transmitting method in which an interleaving process applicable to data transmission using interpolation pilot signal is performed are provided. The data multiplexing method includes the steps of: coding input data for each input channel; multiplexing said data which is coded; performing an interleaving process on said data which is multiplexed; and outputting said data. In the data transmitting method, when an interleaving process is performed, an interleaver is used in which the number of columns of the interleaver is twice as many as the number of slots of a frame.

Abstract: An user interface for reading data recorded in infra-red on the surface of a card upon which may also be recorded a visual representation is disclosed. The reading apparatus comprises scanning means for scanning in the encoded fault tolerant digital form of the data on the surface, means for processing the scanned data and for decoding the data into a secondary digital format and means for outputting the secondary digital format to an output device with which the secondary digital format is usable. The output device presents the data in a human readable form. The data may include text and/or images equivalent to recording a book, newspaper, manual or a database.

Abstract: Devices, software, and methods measure a burstiness of packet loss episodes in transmissions of voice data through networks. At least one burstiness statistic is determined to quantify how the lost packets are distributed with respect to the received packets within the sequence. The burstiness statistic is optionally used to determine a figure of merit, which in turn can be used to give a grade for predicting how well a packet loss concealment scheme will work.

Abstract: Disclosed is a turbo channel encoding and decoding device for a CDMA communication system. When the input data frames are very short, the device assembles input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding and decoding, the frames are reassembled into the original input frames.

Abstract: A turbo channel encoding/decoding device for a CDMA communication system. The device segments an input frame into multiple sub frames of an appropriate length when the input data frame is very long, and then encodes and decodes the sub frames. Otherwise, when the input data frames are very short, the device composes input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding/decoding, the frames are recomposed into the original input frames.

Abstract: The present invention relates to method and apparatus that records/reproduces data to/from an optical disk to rearrange user data such as video and/or audio data or to restore original data order by scanning each ECC block in a U-pattern. The present method arranges data in a data block in U-pattern scanning order on the block to randomize data sequence, and records the data block, of which data order has been randomized, sequentially along a track of a writable disk, whereby it is possible to recover individually a long burst error due to track-wise scratch, dust, fingerprint, or the like because an burst-error is scattered in a restored ECC block.

Abstract: A method for data related downlink signaling including selectively tailoring the UE ID to create a UE ID value, which is then added to a data field to create a data mask. This data mask is then further processed as the CRC field and transmitted with the data burst to provide CRC-related functions. An alternative embodiment discloses initializing a CRC generator with UE identification prior to CRC generation. This implicitly includes the UE ID within the CRC without requiring additional overhead signaling.

Abstract: Techniques are described for maintaining the orthogonality of user waveforms in multi-user wireless communication systems, such as systems using the code division multiple access (CDMA) modulation scheme in the presence of frequency-selective fading channels. Unlike conventional systems in which spreading is performed on individual information-bearing symbols, the “chip-interleaved block-spreading” (CIBS) techniques described herein spread blocks of symbols. A transmitter includes a block-spreading unit to form a set of chips for each symbol of a block of information-bearing symbols and to produce a stream of chips in which the chips from different sets are interleaved. A pulse shaping unit within the transmitter generates a transmission signal from the stream of interleaved chips and transmits the signal through a communication channel.

Abstract: A method for interleaving data frames transmitted via a modem pool, each of the data frames including a plurality of codewords having a predefined level of error correction, including assigning the data frames to corresponding modem timeframes, where codeword symbols in each of the data frames are assigned to time slots in the modems in the corresponding timeframes such that the level of error correction is sufficient to correct error/loss caused to any of the symbols given a predefined level of modem loss/malfunction, and moving any of the codeword symbols assigned to one of the timeframes to another of the timeframes such that the level of error correction is sufficient to correct error/loss caused to any of the symbols given a predefined level of cross-modem error burst while preserving the level of error correction sufficient to correct error/loss caused to any of the symbols given the level of modem loss/malfunction.

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: A process and apparatus is described for recovering from optical transmission degradation due to scintillation effects in optical free space. A payload bit stream is encoded into Reed-Solomon codewords. These are fragmented and distributed as interleaved segments over a cell matrix of a SDRAM buffer store which is made large enough to correct a burst error occurring over 20 million consecutive bits. The rate imbalance between conventional read vs. write operations for SDRAM devices, which would otherwise obviate their use in this application by preventing real time operation, is overcome by an address remapping that avoids having to changing page addresses each time SDRAM memory is referenced. The remapping facilitates a more nearly equal allocation of READ overhead and WRITE overhead. An optical communications system employs at both the transmit and receive ends, substantially equivalent SDRAM buffer with address remapping capability.

Abstract: A data packet type communication system utilizes packet framing wherein preambles are split into two or more subpreambles, separated by a number of data or a priori known symbols. A receiver chooses among individual and combined subpreamble options for determining synchronization. When a noise impulse prevents detection of one subpreamble, the impulse is detected, and preamble correlation proceeds using an unaffected subpreamble. When no impulse is detected, combined subpreambles are used.

Abstract: A communication system 100 employs turbo encoding having a turbo interleaver 106 that interleaves input data 101 efficiently with little use of system resources. The turbo interleaver 106 reads address locations of the data bits into an interleaver matrix array 206 row by row and interleaves the address locations by bit reversal of the row indexes with accompanying permutation of the corresponding address locations in the rows of the matrix 206, bit reversal of the column indexes with accompanying permutation of the corresponding address locations in the columns of the matrix 206 and shifting the address locations within each row a predetermined number of column locations based on the particular row number.

Abstract: An error flag generation apparatus and method for error correction, wherein the apparatus includes: a frame-sync error memory which stores frame-sync error information for each data block; a BIS (Burst Indicator Subcode) error flag memory which stores a BIS error flag for each data block; and an error flag generator, which generates an error flag indicating error existence/absence for ECC (Error-Correction Coding) data with reference to the frame-sync error information stored in the frame-sync error memory and the BIS error flag stored in the BIS error flag memory. Therefore, the error flag generation apparatus and method for error correction can be easily implemented with improved error-correction performance and be advantageous in cost.

Abstract: A convolutional interleaver includes an interleaver memory partitioned into a plurality of circular buffers, wherein each of the circular buffers has associated write pointers and read pointers, and wherein the interleaver is configured to selectively read symbols from an input vector and store the input symbols in the interleaver memory in accordance with the write pointers, and to selectively read symbols from the interleaver memory to form an output vector in accordance with the read pointers. In one aspect, symbols are written to the interleaver prior to reading; in another, the position of the write pointer corresponds to the position of the read pointer within the circular buffer, and symbols are read from said interleaver memory prior to writing. In another aspect, a de-interleaver applies the concepts and algorithms described above in an inverse manner.

Abstract: Method and system for indicating that at least one row or column of a DVD data block has an uncorrectable number of errors, by marking or flagging the corrupted codewords of a codeword with defect detect signals. When a column (or row) of the data block is found to contain more than a thereshold number of errors, a selected number w of distinguishable codeword values (DSVs) “x” is associated with at least one column (or with at least one row) of the block. When the block is further processed and the presence of more than a threshold number of DSVs is sensed, the system interprets this occurrence as indicating that an uncorrectable group of errors has occurred in a column and/or row of the block.