Abstract: A method of determining error values including loading an error correction code (ECC) entity having rows representing data symbols, determining an error location for a first row, generating an error syndrome for the first row, determining an erasure constant array from the error location, determining an error location for each of the remaining rows, generating an error syndrome for each of the remaining rows and determining the error values for each of the rows from the corresponding error location and corresponding error syndrome and the constant.

Abstract: Methods and apparatus are disclosed for generating and checking CRC values using a multi-byte CRC generator and a binary Galois field (“GF2”) multiplier. These methods and apparatus could be used in an unlimited number of applications and environments, such as part of computer or communications device (e.g., router or switch). The CRC generator and/or checker may be implemented singularly or in a combination of technologies, including, but not limited to, software, firmware, hardware, customized circuitry, application-specific integrated circuits, etc. A CRC generator is used to calculate a preliminary CRC value on a block of information. This CRC generator may be a balanced XOR tree or some other implementation, which calculates the preliminary CRC value on groups of n bytes of data at a time, where n is some integer greater than one. For example, when data is transferred over a 512 wide bit bus, typically the value of n would be 64 (i.e., 512 bits divided by 8 bits per byte).

Abstract: Error bursts are detected and corrected in a communication system using shortened cyclic codes, such as shortened Fire codes. Data is loaded into a first error syndrome register and a second error syndrome register. The data in the registers may be evaluated to determine if the data bits contain a correctable error. Shortened zero bits are shifted into the second error syndrome register. A number of zero bits are shifted into the first error syndrome register to trap an error burst pattern in the data. A determination is made as to the number of zero bits shifted into the second error syndrome register to trap the location of the error burst in the data. Using the number of zero bits shifted into the second error syndrome register and the error burst pattern, the error in the data is located and corrected.

Abstract: Adjusting a clock signal includes receiving a data stream, detecting a bit in the data stream using a first amount of data in the data stream, adjusting the clock signal based on the detected bit, detecting the bit in the data stream using a second amount of data in the data stream, the second amount of data comprising more data than the first amount of data, and correcting the clock signal if a result of initial detecting differs from a result of subsequent detecting.

Abstract: A method of transmitting and receiving data packets over a channel susceptible to random burst and/or white gaussian noise channel errors. Each data packet is encoded to form error correctable encoded data packets. Each error correctable encoded data packet is interleaved to form interleaved error correctable encoded data packets. Each interleaved error correctable encoded data packet is modulated to form modulated interleaved error correctable encoded data packets. Each modulated interleaved error correctable encoded data packet is transmitted over the channel. The channel can be a telephone line. The encoding includes performing Reed Solomon encoding on each data packet to form Reed Solomon error correctable encoded data packets. Each data packet is cyclic redundancy check encoded prior to performing Reed Solomon encoding. Modulated interleaved error correctable encoded data packets are received from the channel.

Abstract: A interleaver/de-interleaver mechanism for reducing the latency of transmitted interleaved codewords. The interleaver/de-interleaver mechanism utilizes a shortened first codeword which functions to offset the interleaving and transmission on subsequent codewords so as to achieve reduced latency depending on the degree of shortening applied. The interleaver/de-interleaver mechanism is particularly useful in power line carrier based systems to reduce the exposure to burst errors by providing interleaving with minimal latency penalty.

Abstract: Methods and systems for providing sparing tables are described. In one embodiment, at least one media for storing data is received and processed. Processing takes place by identifying burst errors having burst error locations. A determination is made as to whether any of the burst errors can be combined for purposes of entry annotation in a sparing table associated with the media. A sparing table is then configured with entries associated with the burst errors. In an event that a burst error can be combined with at least one other burst error, an entry is provided in the sparing table that reflects one or more burst error combinations.

Abstract: A method and apparatus for coding and decoding a sequence of data packets with use of a novel class of forward error correcting codes having coding rates greater than 1/2 which nonetheless provide relatively high levels of channel protection against burst erasures with a relatively low decoding delay. In accordance with certain illustrative encoder embodiments of the present invention, the source information contained in each of a plurality of packets to be coded is similarly divided into a plurality of (similar) corresponding portions, and “checksums” are computed over multiple data packets, each such checksum being based on different (i.e., non-corresponding) portions of at least two of the multiple packets. These “checksums” are then advantageously appended to various subsequent data packets to be coded.

Abstract: Interleavers are used in data transmission and storage applications to introduce diversity into a data stream, thereby making adjacent symbols more independent with respect to a transfer environment of variable quality. Conventional interleavers require storage in whole units of data blocks. This storage requirement complicates implementations for applications where available circuit area is limited and data rates and block sizes are large. A novel interleaver produces an interleaved data block using storage space that is only a fraction of the size of the input data block.

Abstract: A method and apparatus for detecting the location of burst errors in serially transmitted data or reducing the susceptability to burst errors in the serially transmitted data. Successive received data words have bits selectively interleaved over a plurality of interleaved data words via burst interleave logic prior to transmitting the interleaved data words over a serial data channel. The selective bit placement assures that the bits in the original data word are spaced apart by at least a predetermined number of bits when the bits are transmitted over the serial data channel. Word framing is performed on the received serial data stream and the interleaved data words are de-interleaved. In the event of a burst error of m bits or less on the serial data channel, the burst error appears as a single bit error in each recovered data word following transmission over the data channel. An error detection code or error correction code is employed to detect or correct single bit errors in the recovered data words.

Abstract: An apparatus is adapted for interleaving an incoming stream of data blocks, each of which has a predetermined number (N) of block units indexed consecutively from 0 to (N−1), The interleaving is accomplished at a predetermined interleaving depth (D). A first one of the block units has no delay associated therewith, and subsequent ones of the block units in a designated one of the data blocks have a delay equal to (D−1) more than an immediately preceding one of the block units in the designated one of the data blocks. The apparatus includes a data buffer configured to have a number of lines equal to (N−1), an output unit, and a control unit. Each of the lines has a size sufficient to accommodate a predetermined number of the block units. The output unit outputs one of the block units of the incoming stream directly when the delay associated therewith is equal to zero.

Abstract: A to-be-sent signal (20) is comprised of a header (21) and convolution encoded data (22). An error correcting code (23) has a capability to correct a bit error or burst error contained in an objective data (24) placed apart from the header (21) in said convolution encoded data (22). Because an error arises easily in data placed apart from a header compared with that positioned near said header generally, said error correcting code (23) is added to data placed apart from said header and the addition of said error correcting code is omitted in data placed near to said header, thereby reducing whole information contents and transmission power.

Abstract: Methods and apparatus for cyclic code codeword creation, error detection, and error correction are disclosed. The methods and apparatus utilize a set of permuted generator polynomials, each representing shifted and exclusive-ored (XORed) versions of the cyclic code generator polynomial according to a specific input bit pattern. The permuted generator polynomial may be provided by look-up table, hardware, or a software equivalent of this hardware. Use of the permuted generator polynomial greatly reduces the number of calculations required to calculate syndromes and trap errors in codewords. The permuted generator polynomial can be used to replace m iterations of a polynomial division operation with a single XOR operation. The bit pattern used to select a permuted generator polynomial is derived from the m high-order bits of the dividend at each step.

Abstract: Data of an input data series is written into a first interleaver. The data is read out column by column or row by row from the first interleaver and written into a plurality of second interleavers column by column or row by row. The data is read from each of the second interleavers and written into one or a plurality of third interleavers as necessary. The operation is repeated once or a plurality of times, thereby reading the data from each of the interleavers and generating a data series. Interleaving is carried out by generating interleaving patterns with a plurality of interleaving patterns. Further, an interleaving pattern suitable for turbo encoding or transmission is generated.

Abstract: An iterative method and system are disclosed for locating errors in interleaved code words. The system and method generate column parity check symbols using symbols from selected columns in the interleaved code words. The width of each column parity check symbol is reduced, followed by the reduced column parity check symbols being merged to create merged column check symbols. A Reed-Solomon encoding algorithm is performed on the merged column check symbols to generate error locating check symbols which are combined with the reduced column parity check symbols to create an error locating code word. The error locating check symbols are stored with the interleaved code words in memory. Following retrieval from memory, the error locating code word is reconstructed and decoded upon the detection of at least one uncorrectable interleaved code word from decoding the interleaved code words.

Abstract: An encoding/decoding apparatus generates data sequences with first and second interleave structures by respectively performing data on a data sequence to be encoded, interleaving processes based on different first and second data interleaving schemes, generates sequences of first and second error correcting codes respectively corresponding to the data sequences with the first and second interleave structures, and generates an encoded data sequence which has the generated sequences of first and second error correcting codes affixed to the data sequence to be encoded. The encoding/decoding apparatus decodes a data sequence to be decoded, included in the encoded data sequence, by using the data interleaving processes and the sequences of first and second error correcting codes.

Abstract: A method of interleaving data for transmission is provided wherein first and second interleaving patterns for arranging data symbols in a source data stream into first and second transmitted data streams are selected. Each of said data symbols has at least one bit. The first and second transmitted data streams are transmitted substantially simultaneously on separate transmission channels to at least one receiver. The first and second patterns are used to transmit the data symbols in the source data stream in a different order on the respective transmission channels to maximize recovery of the source data stream when the transmission channels are blocked. The selected interleaving patterns can involve reordering the data symbols throughout the first and second transmitted data streams using different reordering criteria The reordering. criteria can vary on a frame-by-frame basis if the source data stream is time division multiplexed. Complementary data can be sent on respective transmission channels.

Abstract: A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.

Abstract: A wireless telephone system comprising a base unit coupleable to one or more external telephone lines and having a base transceiver, and at least one wireless handset. The wireless handset has a handset transceiver for establishing a digital link with the base unit via the base transceiver over a wireless channel, wherein the handset and base unit communicate via the digital link by fixed-size audio packets comprising a plurality of audio data samples and a plurality of error correction bits. Qualities of the digital link are monitored to determine whether a change in error rate occurs. In response to the determination, a packet structure of subsequent audio packets is changed from a first packet structure to a second packet structure to change the relative number of bits devoted to audio data samples and to error correction bits.

Abstract: The present invention provides for adaptive and multimode decoding, in a data packet-based communication system, to provide improved received signal quality in the presence of burst erasures or random bit errors, with particular suitability for real-time, delay sensitive applications, such as voice over Internet Protocol. In the presence of burst erasures, the adaptive multimode decoder of the present invention provides burst erasure correction decoding, preferably utilizes a maximally short (MS) burst erasure correcting code, which has a comparatively short decoding delay. Depending upon the level of such burst erasures, different rate MS codes may be utilized, or other codes may be utilized, such as hybrid or multidescriptive codes. When no burst erasures are detected, the adaptive multimode decoder of the present invention provides random bit error correction decoding, in lieu of or in addition to corresponding burst erasure correction coding.

Abstract: Timing characteristics of message-oriented transports are measured using common personal computers which easily support a wide variety of analytical tools. The apparatus measures timing characteristics of bursty message traffic over relatively low-speed digital transports such as the Musical Instrument Digital Interface (MIDI). The apparatus includes means for generating a reference pulse stream, such as a sequencer. A transcoder device receives the reference pulse stream and routes the pulse stream to a device under test and, in analog form, to a first channel input of a digital recording device, such as a sound card installed in a personal computer. The transcoder also receives an output pulse stream from the device under test and routes the output pulse stream, in analog form, to a second channel input of the digital recording device. A differential technique allows timing errors in the reference pulse stream to be eliminated from measurements.

Abstract: An interleaver in which a frame of data to be interleaved is stored in at least a portion of an array having R rows and C columns, the portion having Nr(l) rows and Nc(l) columns that satisfy the inequality Nr(l)×Nc(l−1)<L<Nr(l)×Nc(l) where Nc(l) is a prime number and Nc(l−1) is the highest prime number less than Nc(l). The elements of each row are permuted according to a predetermined mathematical relationship, and the rows are permuted according to predetermined mapping.

Abstract: A method for generating correction codes that can correct a single error and detect two adjacent errors in an information word for a range of (n, k) values, where k denotes the length of the information word in bits and n denotes the length of the coded information word in bits. The method generates a parity check matrix, then multiplies a received word by the parity check matrix to produce a syndrome corresponding to one of two mutually exclusive sets of syndromes if the word contains at least one error. Information in the word is corrected by inverting a bit containing an error if the produced syndrome corresponds to one of the sets of syndromes. An uncorrectable two bit adjacent error is reported if the produced syndrome corresponds to the other of the two sets of syndromes and no error is reported if the produced syndrome contains all zeros.

Abstract: A system for memory word error correction that enables correction of burst errors in memory words. The system is based on an adaptation of two-error correction BCH code which yields burst error correction without increasing the number of error correction bits in the memory words over prior two-error BCH code error correction schemes. The adaptation of two-error correction BCH code when combined with additional techniques for detecting columns of burst errors enables the correction of burst errors and additional random bit errors in memory words.

Abstract: An error correction and detection technique provides a correction code for correcting single bit errors as well as detecting but not correcting two adjacent bits in error. A received word, which may contain errors, is multiplied by a parity check matrix to produce a syndrome corresponding to one of first and second mutually exclusive sets of syndromes if the received word contains at least one error, each single bit error in the received bit word corresponding one-to-one with a member of the first of the sets of syndromes and each two bit adjacent error corresponding non-uniquely to a member of the second of the sets of syndromes. A syndrome containing all zeros is produced if the received word contains no errors. One bit data errors in the received word are corrected, two bit errors are reported, and no action is taken if the word contains no errors.

Abstract: A method and system for locating control channels, particularly digital control channels, are described. By grouping the channels which are candidates for carrying supervisory messages in blocks indicative of their relative likelihood for being used as control channels, a mobile station can begin its search for a control channel with channels which are most likely to actually be control channels. Placing location information on other channels allows the mobile station to be redirected to a control channel when it reads one of these other channels. Similarly, by placing information describing the location of a control channel in a message associated with handoff, a mobile station avoids the necessity of having to relocate a new control channel associated with the base station to which the mobile has been handed off.

Abstract: Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors are detected while allowing differentiation between memory addressing failures that are required to stop the system and memory cell failures that allow continued operation. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst. The retrieved predefined pattern is compared to the generated expected pattern for identifying a type of an addressing error.

Abstract: In a data transmission method and system, user signals are transmitted wirelessly, and a maximum delay for the system has been defined. The system includes circuitry at the transmitting end for sequentially performing an outer and inner coding on the signals to be transmitted, and circuitry for performing a first interleaving after the outer coding. The interleaving length of the first interleaving is chosen within the scope of the maximum delay defined for the system. To ensure improved performance, the system includes circuitry for performing a second interleaving after the inner coding, and the interleaving length of the second interleaving is substantially equal to the interleaving length of the first interleaving.

Abstract: Disclosed is method and apparatus for error code correction using product code. The method includes: (a) reading a data frame and associated check bytes from a media; (b) generating an error correction model for the data frame and associated check bytes, where the error correction model is defined by non-zero syndromes in the check bytes of Q dimension code words and P dimension code words of the data frame; (c) examining the generated error correction model; and (d) correcting the data frame using a combination of error correction systems that are selected based on the examining of the generated error correction model.

Abstract: The information coding device has: a first labeling means adapted to associate, with the information to be coded, K “initial” first degree polynomials, a coding means which performs a polynomial calculation: to form K “coded” sequences of P, greater than or equal to K, “coded” polynomials, the first being equal to one of the K initial polynomials and the others to the product of the preceding polynomial and a predetermined polynomial, and to form a “resultant” sequence of P “resultant” polynomials respectively equal to the sums of the coded polynomials of same rank of the K coded sequences, a second one-to-one labeling means adapted to label the points of a quadrature amplitude modulation signal constellation with the Q2 resultant polynomials, for two adjacent points of the constellation, the polynomials labeling them have one identical coefficient and the other coefficient differing only by 1 modulo Q, and a modulator for quadrature amplitude

Abstract: An apparatus and method for generating a (n, 3) code and a (n, 4) code using simplex codes are disclosed. To encode a 3-bit information bit stream to a (n, 3) codeword with n code symbols, a simplex encoder generates a first-order Reed-Muller codeword with (P+1) code symbols from the input information bit stream for n>P, and punctures the first code symbol of the (P+1) first-order Reed-Muller code symbols to produce a (P, 3) simplex codeword. An interleaver permutates the P code symbols of the (P, 3) simplex codeword by columns according to a predetermined pattern. A repeater repeats the column-permutated (P, 3) simplex codeword until the number of repeated codes is n and outputs a (n, 3) codeword with the n repeated code symbols.

Abstract: Disclosed is a thermal asperity pointer processing apparatus and method for processing apparatus for generating erasure locations from a thermal asperity signal. The thermal asperity signal indicates an error burst in an interleaved data sector. The apparatus includes a thermal asperity pointer recorder, a storage unit, and a thermal asperity pointer processing unit. The thermal asperity pointer recorder is adapted to receive a thermal asperity signal and is configured to generate a thermal asperity event information associated with the thermal asperity signal. The thermal asperity event information includes a thermal asperity duration, a starting interleave number, and a starting interleave address of the thermal asperity signal in the interleaved data sector.

Abstract: Data is encoded to maximize subsequent recovery of lost or damaged compression parameters of encoded data. In one embodiment, at least one compression parameter is used to define a pseudorandom sequence and the data is shuffled using the pseudorandom sequence. In one embodiment, a bit reallocation process and code reallocation process are performed on the data to randomize the data.

Abstract: An error correction method for data bytes in a memory uses an error correcting block code such as a Hamming code to detect and correct errors, if any, in the data bytes. The error correction method can be performed by relatively simple and inexpensive logic circuitry while improving the speed of error correction to reduce delays in the external data access time.

Abstract: A method and apparatus for improving burst error correction. The method and apparatus involve transmitting block codes with interleaving, and predicting a burst error in the received block codes. Burst error prediction includes decoding received block codes and determining if the decoding is successful. The method includes receiving a code having an error correction capability, an erasure detection capability and a burst error length associated with it. A decoding step is performed to find an error in the code. The error has a length associated with it. The decoding is successful if the error length found is less than twice the error correction capability. If an initial decode attempt is not successful, then a burst error length is associated with the code and another decode is performed. The burst error length has an initial value that is less than the error correction capability.

Abstract: A novel and improved method and apparatus for address generation in an interleaver is provided. In accordance with one embodiment of the invention, an address is generated using a random address fragment and a bit reversed address fragment. The bit reversed address fragment is selected by first generating two consecutive candidate bit reversed fragments. The second bit reversed address fragment is selected when the first bit reversed address fragment generates an address that is greater than a maximum address. The address generator allows address generation for interleaver and deinterleaver frame sizes of N, where N is not an integer power of two, without any cycle penalty.

Abstract: A method for error correction coding (ECC) by using shuffling of a digital data supplied as a bit stream in a digital-video home system. Three methods are suggested for error correction coding/decoding. One method is where an outer ECC process for 18 ECC blocks is performed earlier than an inner ECC process for the 18 ECC blocks. Another method is where an outer ECC process and an inner ECC process for an ECC block are carried out sequentially and implemented in order for 18 ECC blocks. These two methods employ a predetermined shuffling algorithm. The third method is where an outer ECC process is firstly performed for 18 ECC blocks by using the shuffling algorithm, and then an inner ECC process is implemented by the sync block according to a recording order on tracks. The outer parity information is produced by processing the data from the shuffled sync block.

Abstract: A disk drive that includes a disk defining a multiplicity of sectors operates in accord with a method comprising the steps of providing a firmware-controlled state machine which can be in any of a plurality of states including an off-line in-progress state. While the state machine is in the off-line in progress state; a firmware-controlled scan of the multiplicity of sectors is performed. While performing the firmware-controlled scan, steps are performed to maintain a list of sector identifiers such that each sector identifier in the list points to a sector that has failed, preferably repeatedly, to provide valid data on the fly. While the state machine is not in the offline in-progress state; the drive responds to a request to write data at a specified sector by determining whether the specified sector matches a sector identifier in the list, and if so, autonomously performing a read-verify-after-write operation.

Abstract: The present invention relates to a transmission rate matching apparatus and a method thereof for a next generation mobile communication system. In the conventional technology, when data bit is transmitted from a terminal to a base station, it is transmitted by radio frames, each column of a block interleaver includes biased data bit.

Abstract: Information is transmitted in an uplink to a satellite by applying an outer code to an information block to form an outer coded block. The outer coded block is then inner coded when a short block code is applied, thereby producing a concatenated coded block.

Abstract: A method and means for enhancing the error detection and correction capability obtained when a plurality of data byte strings are encoded in a two-level, block-formatted linear code using code word and block-level redundancy. This is accomplished by vector multiplication of N data byte vectors and a nonsingular invertible integration matrix with nonzero minors with order up to B to secure the necessary interleaving among N data byte vectors to form modified data byte vectors. The selected patterns of interleaving ensure single-pass, two-level linear block error correction coding when the modified data vectors are applied to an ECC encoding arrangement. The method and means are parameterized so as to either extend or reduce the number of bursty codewords or subblocks to which the block-level check bytes can be applied.

Abstract: A method for coded transmission of data is disclosed. A first code word interleaved in a first plurality of burst transmissions is recovered for further processing. The recovered code word is decoded to correct and identify any errors within the code word. Using the results of the above-decoding, bad burst transmissions are identified and erased. Subsequently, a second code word interleaved within a second plurality of burst transmissions is recovered. The second plurality of burst transmissions includes the erased burst transmissions from the first plurality of burst transmissions. The received second code word is then errors and erasures decoded.

Abstract: There is provided an apparatus for processing data for generating an error correction product code block devised so as to maintain the current level of redundancy after the error correcting ability is modified as a result of advancement of semiconductor and data recording/transmission technologies. Unlike any known technique of configuring a Reed-Solomon error correcting product code block of (M+P0)×(N+PI) bytes for an information data of (M×N) bytes, an error correcting product code block data structure is obtained by configuring a (K×(M+1)×(N+P))-byte Reed-Solomon error correcting product code block for (K×M×N)-byte data, making K variable to consequently make the entire size of the Reed-Solomon error correcting product code block variable. At the same time, the error correcting ability varies in proportion to the value of K without increasing redundancy.

Abstract: Apparatus, and an associated method, for performing error-correction operations to correct errors in a block of block-encoded data. Two ALUs are operable in parallel to perform finite-field mathematical operations and to calculate addresses used pursuant to the error-correction calculations. Instructions pursuant to which the ALUs are operable are stored in a memory device. The instructions are retrieved during operation of error-correcting calculations. The manner by which the error-correcting apparatus operates is alterable by appropriate alteration of the instructions stored at the memory device.

Abstract: A method of interleaving data for transmission is provided wherein first and second interleaving patterns for arranging data symbols in a source data stream into first and second transmitted data streams are selected. Each of said data symbols has at least one bit. The first and second transmitted data streams are transmitted substantially simultaneously on separate transmission channels to at least one receiver. The first and second patterns are used to transmit the data symbols in the source data stream in a different order on the respective transmission channels to maximize recovery of the source data stream when the transmission channels are blocked. The selected interleaving patterns can involve reordering the data symbols throughout the first and second transmitted data streams using different reordering criteria. The reordering criteria can vary on a frame-by-frame basis if the source data stream is time division multiplexed. Complementary data can be sent on respective transmission channels.

Abstract: A method of encoding data is described herein. According to the method, source data elements are coded using one or more product codes having a common component code. The resulting one or more primary product codewords consist of a plurality of first codewords of the common component code. One or more first sets of codewords of the common component code are assembled such that each of the first sets comprises two or more distinct first codewords forming part of a same primary product codeword. Each of the codewords of each of the first sets is codeword-mapped to a second codeword of the common component code using a one-to-one codeword-mapping. One or more second sets of second codewords are provided, where each second set corresponds to a first set of codewords. The codeword-mapping includes re-ordering, according to a known interleaving pattern, the symbols within a codeword.

Abstract: A system that redefines how data is distributed on a conventional writable compact disc (CD-R/E). A rearrangement of the data on the disc provided during the writing operation preserves eight-to-fourteen channel frames and the control and display (C&D) channel and burst error mitigation while providing a direct access storage device (DASD) format and capability. The CD-DASD format is suitable for preformatting the CDs and has constant size sectors recorded contiguously along the spiral track. Each sector is independently addressable and synchronous with the C&D data word and ATIP channel words on the CD-R disc. The system uses the components of a conventional CD device and a mapping controller address translator to encode and decode the data bytes using a conventional CIRC encoder/decoder. A rectangular product code of C1 and C2 CIRC subcodes is provided that is interleaved to mitigate the effects of handling.

Abstract: A digital communication apparatus (20) transmits sectors of digital values that include error correction values used to detect and correct errors within the sector. Each sector consists of a number of blocks (70, 72, 74) and the error correction values of each block (70) are useful in correcting up to a maximum number of erroneous digital units (78, 84) in that block (70). The digital communication apparatus (20) encodes the blocks of digital units to transmit them through a channel (32) and then decodes the channel's representation of those encoded blocks, where the channel's representation occasionally contains burst errors.

Abstract: A digital modulation circuit which minimizes a DC component of an NRZI modulated code sequence while setting the T.sub.max and T.sub.W not to be varied. An m-n coding mode is determined for each data block composed of the predetermined number of m-bit datawords. That is, an m-n coding mode which minimizes the absolute value of the DSV is selected and the selected m-n coding mode is utilized for the m-n coding of the current data block. The code indicating the selected m-n coding mode is multiplexed to the m-n coded current block. An m--m mapping table is also determined for each data block. That is, such an m--m mapping table that minimizes the absolute value of the DSV is selected and the selected m--m mapping table is utilized for the m--m translation of the current data block. Then, the m--m mapped data block is m-n translated into a code block composed of the same number of n-bit codewords by utilizing the single m-n translation table.

Abstract: A burst error limiting symbol detector system includes a symbol detector circuit responsive to a truncated sample signal for detecting binary symbols encoded in a truncated sample signal with reference to at least one preselected reference level; a feedback equalizer circuit for providing a feedback equalizer signal for cancelling undesired samples in an input signal; a summing circuit, responsive to the input signal and the feedback equalizer signal for providing the truncated sample signal to the symbol detector circuit; and a feedback suppressor circuit responsive to the truncated sample being within a predetermined range of the preselected reference level for suppressing the feedback equalizer signal to prevent marginal detected binary symbols from contributing to the cancellation of undesired samples in the input signal.