Abstract: A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.

Abstract: In some situations, the programming of one memory die can be suspended in favor of the programming of another memory die. This can lead to a delay in certain programming operations. To avoid this problem, a data storage device can perform dynamic logical page write ordering by determining an availability of each memory die of a plurality of memory dies and changing a programing order of the plurality of memory dies in response to the determined availability.

Abstract: A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

Abstract: A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.

Abstract: A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix (G matrix) formed of a concatenation of a parity matrix (P matrix) and an identity matrix; determining a number of rows in the P matrix for a truncated P matrix in view of a correcting strength and a number of data bits; selecting a first subset of rows and a second subset of rows in the P matrix, wherein a first sum of row weights of each row in the first subset of rows is equal to or less than a second sum of row weights of each row in the second subset of rows; and generating the truncated P matrix by keeping the first subset of rows of the P matrix so as to minimize a number of logic gate operations.

Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.

Abstract: A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.

Abstract: Data log-base logical block devices are used to control parameter-based versioning at a block-device level. Memory in the block device stores data log indicating data and corresponding metadata, the metadata indicating a particular historical time. The block device may receive a request, such as a remote procedure call (RPC), for data from the logical block device, and identify data included in the data log having metadata that matches or satisfies a historical time parameter included in and extracted from the request.

Abstract: A method for execution by one or more processing modules of a storage network begins by receiving an access request for a set of encoded data slices, where the data object is segmented into a plurality of data segments, a data segment of which is dispersed error encoded in accordance with dispersed error encoding parameters to produce the set of encoded data slices. The method continues by determining whether a revision for one or more encoded data slices in a first storage module is a most recent revision level for the one or more encoded data slices and when the one or more encoded data slices is a most recent revision level, determining whether the revision level for the one or more encoded data slices in a second storage module is the most recent revision level.

Abstract: A processing-in-memory (PIM) device includes an CRC logic circuit configured to generate write data and a write fail check signal from write input data when a write operation in an operation mode is performed, and generate a fail flag signal and converted data from read data and a read fail check signal when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the converted data and buffer data, based on the fail flag signal to generate MAC operation result data.

Abstract: A technique utilizes grafting and differential based (diff-based) data seeding to hydrate a special virtual disk (vdisk) on a multi-node cluster with data changes (differences) between a reference vdisk stored on the cluster and a snapshot stored in an external repository to enable failover (including failback) recovery of an application workload in a disaster recovery environment. The application workload is stored as a workload vdisk on local storage of the cluster and snapshots of the workload vdisk are generated and organized as a vdisk chain on the cluster. One or more snapshots of the vdisk chain may be replicated to the external repository using a long-term snapshot service. Each replicated snapshot may be backed up from the cluster to the external repository at the granularity of a vdisk, referred to herein as an external datasource disk. The special vdisk is a thinly provisioned, datasource-backed vdisk that is grafted onto the vdisk chain, e.g., as a child vdisk of the reference vdisk.

Abstract: In one example, an apparatus comprises first, second and third memory devices, an error detection circuit, and an error correction circuit. The error detection circuit is configured to detect a mismatch among data stored at the first, second, and third memory devices, and responsive to detecting the mismatch, provide a correction signal representing a majority state of the data. The error correction circuit is configured to write the majority state of the data into at least one of the first, second, or third memory devices responsive to the correction signal.

Abstract: A redundant data calculation method and apparatus. The method is applied to the redundant data calculation apparatus including a processor and a redundant data calculation unit. In the method, after obtaining to-be-processed data, the processor stores the to-be-processed data in cache space of the redundant data calculation unit. The redundant data calculation unit obtains the to-be-processed data from the cache space and performs calculation for checking the to-be-processed data to obtain redundant data corresponding to the to-be-processed data.

Abstract: A method and apparatus for determining stripe consistency, including an operation node that obtains n groups of CRC data blocks corresponding to a target stripe, where the target stripe includes n first data blocks, the n first data blocks include k original data blocks and m EC data blocks of the k original data blocks, the n groups of CRC data blocks are respective CRC data blocks of n groups of second data blocks, one group of second data blocks includes m transformation results obtained by performing m times of EC transformation on one first data block, both k and m are positive integers, and n=m+k.

Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.

Abstract: A technique protects user data within a storage system. The technique involves, in response to a request signal that directs the storage system to store the user data, generating first parity and second parity based on the user data. The technique further involves storing the first parity and the user data in a data uber of the storage system, the data uber providing redundant array of independent disks (RAID) protection. The technique further involves storing the second parity in designated free storage of the storage system, the designated free storage being separate from the data uber.

Abstract: A data processing device including a memory having a plurality of memory locations for respectively storing a value, wherein the data processing device has, for each memory location, an associated error detection memory area, a memory controller which is configured, when a value is written to a memory location, to store an associated error detection code in the error detection memory area associated with the memory location, a memory access element, and an integrity checker configured to perform an EDC check.

Abstract: An apparatus that includes a memory cell array, an I/O terminal supplied with an original write data in a normal operation, a compression logic circuit configured to generate a compressed test data in a test operation based on a test read data read from the memory cell array, and a syndrome generator configured to generate a first syndrome based on the original write data in the normal operation and generate a second syndrome based on the compressed test data in the test operation.

Abstract: A magnetic disk device includes a disk including a plurality of error sectors including a defect, a first track having a first parity sector, and a controller. The controller is configured to, upon receiving a write command to write first data in a first region of a portion of the first track, which is a portion of the first track, first perform an XOR operation on all sectors of the first track other than one or more sectors of the first region and the first parity sector of the first track, and then write the first data in the one or more sectors of the first region, perform a second XOR operation on the one or more sectors of the first region and the result of the first XOR operation, and write the result of the second XOR operation in the first parity sector.

Abstract: A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.

Abstract: A method may comprise detecting an error associated with accessing a set of data items. The set of data items are programmed to a respective memory page associated with a stripe of a plurality of stripes. In response to determining that the set of data items comprises one or more codewords, a first data recovery process is performed to recover the one or more codewords based at least in part on RAIN redundancy metadata. In response to determining that the set of data items comprises additional parity metadata, a second data recovery process is performed to recover the additional parity metadata based at least in part on LUN redundancy metadata. In response to determining that the set of data items comprises RAIN redundancy metadata, a first data reconstruction process is performed to regenerate the RAIN redundancy metadata based at least in part on one or more sets of codewords.

Abstract: Systems and methods described herein may relate to providing a dynamically configurable error correction code (ECC) circuitry able to process data having one of a variety of widths. This multi-width ECC circuitry may generate error correction code bits (ECC bits) using, for example, an encoder or a decoder characterized by a fixed data width. Translation circuitry (e.g., a format converter) may translate data received from data utilization circuitry between a data width used by the data utilization circuitry and the fixed data width used by the encoder or the decoder.

Abstract: A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.

Abstract: The present technology includes a controller including an allocation manager configured to determine whether a host identification (ID) output from a host is an allocable ID, an address manager configured to perform an allocation operation using the host ID to select logical blocks corresponding to the host ID when the host ID is received from the allocation manager, and output an address of the logical blocks as an allocation address, and a map table component configured to store a map table in which logical block addresses and physical block addresses are respectively mapped, select a logical block address corresponding to the allocation address, and output the physical block address mapped to the selected logical block address, a memory system including the controller, and a method of operating the memory system.

Abstract: A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. Data communication is made more efficient by removing the need to copy data in the networking stack, using hardware accelerated end-to-end checksum calculation, and supporting transmission formatting of data and header for special cases.

Abstract: Provided are systems and methods for managing storage of machine data. In one embodiment, a method can be provided. The method can include receiving, from one or more data sources, raw machine data; processing the raw machine data to generate processed machine data; storing the processed machine data in a data store; and determining an allocated data size associated with the processed machine data stored in the data store, wherein the allocated data size is the size of the raw machine data corresponding to the processed machine data stored in the data store.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The memory device is arranged into at least a first super device and a second super device, each of the super devices having a plurality of active zones. The controller is configured to determine that each of the super devices includes both cold zones and hot zones, where a cold zone is a zone that is overwritten less than a hot zone. The controller is further configured to move cold zones from one super device to another super device upon determining that the another super device is below a threshold limit, where the threshold limit is a minimum free space to be maintained in a super device. The controller is further configured to move cold zones between super devices, such that the cold zones are concentrated in at least one super device.

Abstract: A storage error identification/reduction system includes a storage error identification/reduction subsystem coupled to a storage subsystem including a block. The storage error identification/reduction subsystem receives first data, and writes the first data to first storage locations in the block while writing storage error identification data to second storage location(s) in the block that each are located adjacent at least one of the first storage locations, with the storage error identification data including predetermined values that are written to predetermined locations included in the second storage location(s) in the block. The storage error identification/reduction subsystem then reads the storage error identification data from the second storage location(s) and, based on the predetermined values and predetermined locations of the storage error identification data, identifies errors resulting from the reading of the storage error identification data.

Abstract: A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for storing and accessing data. A method for storing data includes: dividing, in response to receiving a request for storing data from a client, the data into a plurality of data blocks; storing the plurality of data blocks in a plurality of servers respectively; generating metadata of the data to record corresponding addresses for storing the plurality of data blocks in the plurality of servers; and storing the generated metadata in a metadata repository. The embodiments of the present disclosure can effectively improve data transmission efficiency, data availability, and data security in a cloud storage system.

Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive in a storage system, from a host device, mapping information associating a key identifier of a datastore-level key with a corresponding datastore comprising multiple logical storage devices of the storage system, to store the mapping information in a datastore-level key data structure of the storage system, to utilize the key identifier to obtain in the storage system the datastore-level key from a key management server external to the storage system, and responsive to receipt of at least one IO operation from the host device relating to at least one of reading or writing encrypted data of at least one of the logical storage devices of the datastore, to utilize the obtained datastore-level key to access the encrypted data in unencrypted form in the storage system.

Abstract: An electronic control device includes a nonvolatile memory having allocated two storage areas that are exclusively switchable between an active state and an inactive state, the two storage areas being set such that in a state in which a program is written in the storage area in the active state, a program is written for updating to the storage area in the inactive state in response to an instruction from an external device, followed by switching the storage area in the active state to the inactive state and switching the storage area in the inactive state to the active state. In the electronic control device, when the program written in the storage area in the active state differs from the program written in the storage area in the inactive state, the program written in the storage area switched to the active state is copied to the storage area in the inactive state.

Abstract: A method comprising: receiving a request to read data stored in an array of drives; determining that the data is stored on one or more degraded drives in the array; reconstructing the data from one or more drives in the array other than the degraded drives; providing the reconstructed data in response to the request; and after providing the reconstructed data, writing the reconstructed data to one or more drives in the array other than the degraded drives.

Abstract: A method, computer system, and computer program product for data monitoring management are provided. A first invalid zero value candidate from a data stream is received. A memory location for the first invalid zero value candidate is received. At a first time an access connection to the memory location is established. At a second time subsequent to the first time the access connection to the memory location is checked. Based on the checking, a determination is made whether the first invalid zero value candidate contains an invalid zero value.

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.

Abstract: An information processing apparatus including a memory and a memory controller writing data to the memory in response to a write for writing the data to the memory, in which the memory executes error correction processing for each data of a predetermined data length, and the memory controller executes, in place of the memory, read modify write processing in a case where a data length of the data related to the write instruction is smaller than the predetermined data length.

Abstract: A method for managing soft errors associated with one or more safety programmable logic controllers (PLCs) is provided. The method includes receiving an expected soft error rate for type(s) of input/output (I/O) modules over time, receiving respective soft error data that was aggregated by the respective safety PLCs based on soft errors detected by I/O modules coupled to the respective safety PLCs. Actual soft error rates are determined per I/O module type based on the received soft error data, and soft error rates are predicted for the safety PLC(s) per I/O module type. The actual and/or predicted soft error rates are compared to the expected soft error rate per I/O module type. The method further includes taking one or more actions in response to a threshold deviation between the actual and/or predicted soft error rates relative to the expected soft error rate for the corresponding I/O module type.

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting (EC) layout constitutes a first layout in the form of a Latin Square.

Abstract: Examples herein relate to a storage system that separately handles portions of a write operation that are aligned and misaligned with respect to retrievable segments from a storage device. For misaligned portions, a buffer can be used to store misaligned retrievable segments and update the segments with content provided with the write operation. Aligned portions of content associated with a write request can be written directly to the storage medium or overwrite corresponding retrievable segments present in the buffer. A table or array can track logical block addresses that correspond to content in the buffer or in the storage. Content in the buffer can be kept in the buffer without being backed-up or persisted to the storage until a triggering event occurs such as power loss or low space in the buffer.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: The operational continuity of a programmable device, and a controller using the same is enhanced.

Abstract: Storage devices are capable of identifying zones for sharing parity blocks across zones. Active zones may be segregated across multiple active zones having similar zone properties, and grouped so that parity buffers can be shared. By identifying zones for optimal parity sharing, storage devices and systems can: (i) maintain independent parity for all zones during initial zone writes (i.e. during an erased state when data is written directly to pages and not to the zones), (ii) track zone write pointers and frequency of writes in the zones, (iii) segregate zones with higher correlation and group them together, (iv) utilize these groupings placed across various channels so that zones with high correlations, comprising of the zones that are written together and at the same rate, share the parity buffers, and (v) load and XOR individual parity buffers for optimal parity sharing across all zones.

Abstract: An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits.

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.

Abstract: A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix; transforming the generating matrix into a systematic form, wherein the transformed generating matrix is composed of a parity matrix and a check matrix; sorting rows of the parity matrix according to row weights; determining a number of rows in the parity matrix to be truncated; generating a truncated parity matrix by keeping the sorted rows of the P matrix that have weights less than or equal to weights of the truncated rows of the P matrix so as to minimize a number of logic gate operations; and forming an error correction circuit with the number of logic gate operations minimized according to the truncated P matrix to correct the error of the codeword.

Abstract: Various embodiments, methods, and systems for erasure coding with overlapped local reconstruction codes, are provided. An erasure coding scheme can be defined based on Overlapped Local Reconstruction Codes (OLRC) that achieve high storage efficiency by providing fault tolerance properties that optimize reconstruction for common cases of failures while maintaining the reconstruction costs for uncommon case of failures. In operation, a data chunk is divided into data fragments. The data fragments correspond to zones. A plurality of parity fragments is computed using the data fragments. A parity fragment is computed using a subset of the data fragments. The plurality of parity fragments are assigned to the zones comprising the data fragments, where the data fragments and the plurality of parity fragments define overlapped local construction codes having a plurality of local groups. An unavailable data fragment is recoverable from at least two local groups from the plurality of local groups.