Abstract: Embodiments of a declustered, fault-tolerant array of storage devices for use with computer, networked, cloud-based, and other data storage applications are described. In some embodiments, the array generates a chunk group mapping with a high utilization of storage device space, provides evenly distributed hot spares, supports multiple erasure schemes including Reed-Solomon codes and Local Reconstruction Codes, and provides high storage device rebuild speed after storage device failure. Embodiments of methods of generating chunk group mappings are also disclosed. In some embodiments, chunk group mappings are determined based on the desired erasure scheme, the number of storage devices connected to the declustered, fault-tolerant array of storage devices, and a generated balanced incomplete block design or a generated partial balanced incomplete block design.

Abstract: A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation.

Abstract: A storage system comprises a first controller and a plurality of storage devices. The plurality of storage devices configure RAID, each of which includes one or more non-volatile memory chips providing storage space where data from a host computer is stored, and a second controller coupled to the non-volatile memory chips. In case where the first controller receives an update request to update first data to second data from the host computer, the second controller in a first storage device of the storage devices is configured to store the second data in an area different from an area where the first data has been stored, in the storage space of the first storage device; generate information that relates the first data and the second data; and generate an intermediate parity based on the first and the second data.

Abstract: A storage system, including: (a) a primary storage entity utilized for storing a data-set of the storage system; (b) a secondary storage entity utilized for backing-up the data within the primary storage entity; (c) a flushing management module adapted to identify within the primary storage entity two groups of dirty data blocks, each group is comprised of dirty data blocks which are arranged within the secondary storage entity in a successive sequence, and to further identify within the primary storage entity a further group of backed-up data blocks which are arranged within the secondary storage entity in a successive sequence intermediately in-between the two identified groups of dirty data blocks; and (d) said flushing management module is adapted to combine the group of backed-up data blocks together with the two identified groups of dirty data blocks to form a successive extended flush sequence and to destage it to the secondary storage entity.

Abstract: A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.

Abstract: A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

Abstract: A device is provided with: memory cell array including plurality of first and second memory cells and one or more third memory cells; judging circuit that judges plurality of data values held by selected first and second memory cells of the first and second memory cells, by referring to reference potential corresponding to reference data held by a selected third memory cell; and error detection and correction circuit that detects whether or not there is error in the judged data values of the first and/or second memory cells, with judged data value of the first and second memory cells as error correcting code. When the error detection and correction circuit detects that there is error exceeding error correction capability in the judged data values, control is performed to write reference data to the selected third memory cell.

Abstract: A mass storage memory device is disclosed. The device includes a plurality of blades where two blades are used to store parity data corresponding to data stored in the other blades. The device also includes a controller configured to write data to the blades along stripes extending from the other blades to the two blades, where the parity data within a stripe is based on the data written to the other blades in the stripe, and wherein the parity data includes two or more types of parity data.

Abstract: A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value. The reclaim control unit determines whether or not to perform a read reclaim operation depending on the comparison result and a read voltage used to read the data. The read reclaim operation copies the data to a memory block different from a memory block having stored the data.

Abstract: Techniques for opportunistic data storage are described. In one embodiment, for example, an apparatus may comprise a data storage device and a storage management module, and the storage management module may be operative to receive a request to store a set of data in the data storage device, the request indicating that the set of data is to be stored with opportunistic retention, the storage management module to select, based on allocation information, storage locations of the data storage device for opportunistic storage of the set of data and write the set of data to the selected storage locations. Other embodiments are described and claimed.

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit.

Abstract: In the controller circuit of a non-volatile memory system, data is protected by CRC (cyclic redundancy code) between functional blocks of the controller: Before a data set is transmitted from one functional block (such the host interface) to another functional block (such as data encryption or ECC), corresponding CRC is generated and transferred with the data. At the second block, the data set can be checked with the CRC at the second block before it operates on the data. This allows the controller to check for internal transfer errors early, allow for corrupted data to be re-requested, such as from a host when this process is applied to a data write operation. After the second block finishes with the data, a new CRC can then be generated to protect the data on its next internal transfer. This arrangement can particularly useful for functional blocks that transform the data set.

Abstract: Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of data locations, and an error detection module coupled to the quantizing circuit. In some embodiments, the error detection module includes an encoder configured to encode incoming data with redundant data derived from the incoming data and a decoder configured to detect errors in stored data based on the redundant data.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: A method for testing memory devices under test (DUTs) using automated test equipment (ATE) is presented. The method comprises retrieving a portion of raw test data from a memory device under test (DUT). It also comprises comparing the portion of raw test data with expected test data to determine failure information, wherein the failure information comprises information regarding failing bits generated by the memory DUT. Next, the method comprises utilizing paging to transfer data comprising the failure information to a filtering module and filtering out the failure information from transferred data using the filtering module. Further, it comprises updating a fail list using the failure information, wherein the fail list comprises address information for respective failing bits within the memory DUT. Finally, it comprises repeating all the prior steps for the next block of raw test data.

Abstract: Example embodiments of the present invention relate to a method and a system for improving performance of flash cache memory, such as in a host of a storage environment, for example, by preventing a cache cell from reaching an operation limit. The method includes determining that a number of operations to a first cell of a flash memory has reached a threshold and managing the flash memory according to the determination to prevent a failure of a second cell of the flash memory.

Abstract: Method and system for a network device are provided. The method includes generating error correction code (ECC) for writing data to a ternary content addressable memory used by the network device; storing the ECC code and the data at the TCAM; generating an ECC for a search key, used for searching the TCAM; and detecting any error in the stored data by using the search key with appended ECC.

Abstract: In one embodiment of the invention, a method for protecting a content addressable memory is disclosed. The method includes storing a marker bit associated with each data block stored in a random access memory (RAM), states of the marker bit representing whether the data block was recently read from the RAM or recently written into the RAM; receiving a client address pointing to a starting address of a data block stored in the RAM; comparing the client address against one or more addresses stored in a content addressable memory (CAM) to determine a hit indicating the client address was stored in the CAM or a miss indicating the client address was not stored in the CAM; and in response to a miss, the method further includes checking a state of the marker bit associated with the data block pointed to by the client address.

Abstract: A method begins by a dispersed storage (DS) processing module selecting a data segment and verifying integrity values of encoded data slices generated by encoding the data segment. When integrity values of a decode threshold number of encoded data slices are affirmatively verified, the method continues with the DS processing module verifying an integrity value of the data segment. When the integrity value of the data segment is affirmatively verified, the method continues with the DS processing module generating a new set of encoded data slices. The method continues with the DS processing module verifying concurrency of the set of encoded data slices with the new set of encoded data slices and for each encoded data slice having a negative concurrency verification, flagging the encoded data slice as being potentially compromised.

Abstract: Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area.

Abstract: A storage subsystem receives writes via a storage subsystem interface and reduces a number of the writes. Data associated with the reduced number of writes is stored in storage devices of a single drive. Computed redundancy information is stored in the storage devices. A data redundancy scheme is implemented via a disk controller that is enabled to operate without a loss of data in the presence of at least a single failure of any of the storage devices.

Abstract: A disk array device includes: a plurality of disk devices including a strip that stores divided data or a parity; a control device to divide the stripe for each of the plurality of disk devices into the divided data having a size of the strip and write the divided data; and a memory to store new data that corresponds to the divided data stored in the strip, wherein the control device detects whether or not the new data is discrete and performs a first write operation or a second write operation when the new data is discrete.

Abstract: A method for selecting the scrambling and descrambling data transmitted in a storage system containing ECC and scramble engines with a seed table is disclosed and the steps comprises: encoding a data sent from a HOST interface by an ECC encoding engine and transmitting the data to a LFSR scramble engine; scrambling the data by the LFSR scramble engine and transmitting to a storage device; creating a seed value and transmitting the seed value to a seed table by the LFSR scramble engine; receiving the seed value from the seed table and the scrambled data from the storage device by a LFSR descramble engine, and descrambling the scrambled data based on the seed value and transmitting to an ECC decoding engine; and decoding the descrambled data received from the LFSR descramble engine and then acquiring the original data sent from the HOST interface.

Abstract: The present technology relates to a data processing device and a data processing method that enable tolerance against error of data to be improved. In the case in which an LDPC code having a code length of DVB-S.2 of 16200 bits and an encoding rate of 1/3 is modulated by 16 QAM, if a code bit of 4×2 bits and a (i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of two consecutive symbols are set to bits b#i and y#i, a demultiplexer performs interchanging to allocate b0, b1, b2, b3, b4, b5, b6, and b7 to y6, y0, y3, y4, y5, y2, y1, and y7, respectively. The present invention can be applied to a transmission system transmitting an LDPC code or the like.

Abstract: A disk device includes a recording medium having a plurality of recording surfaces, where each of the recording surfaces includes a system region for recording system data related to an operation of the disk device, and a controller configured to control recording of the system data in the system region. The controller is further configured to divide the system data to be recorded into a plurality of portions of divided data of the same size. The controller is further configured, after recording of a first portion of divided data in a first system region disposed on a first recording surface, to start recording a second portion of divided data in a second system region disposed on a second recording surface. The recording of the second portion of divided data is started after a switching time, during which switching from the first recording surface to the second recording surface transpires.

Abstract: A method includes generating error detection information associated with data to be stored at a cache in response to determining that the data is clean. The method also includes storing the clean data at a first region of the cache. The method further includes generating error correction information associated with data to be stored at the cache in response to determining that the data is dirty. The method also includes storing the dirty data at a second region of the cache.

Abstract: A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.

Abstract: A memory controller and an operating method of the memory controller are provided. The operating method includes: performing error correction on data, including a plurality of chunks, in a unit of a chunk; determining if a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and controlling an output time of an error-corrected first chunk based on a result of the determining.

Abstract: Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m1 and n1 are real numbers. The distribution transformer may transform the data into skewed data, wherein the skewed data has a distribution of m2:n2 ratio for bits having the first logic value and bits having the second logic value, where m2 and n2 are real numbers that are different from one another and respectively differ from m1 and n1. The distribution transformer may output the skewed data for storage in the memory. Other embodiments may be described and claimed.

Abstract: Data storage devices using a two-level ECC scheme are described. Embodiments of the invention allow the recovery of sectors in a squeezed group of tracks in a that includes both a single track level ECC scheme and a track band ECC scheme that functions across the set of tracks in the band. The track band ECC scheme uses additional parity information calculated using input data from multiple tracks to allow correction across tracks.

Abstract: A computer memory access method includes: receiving external data with a prefetching length; determining that the external data includes a masked data portion; at the time of a write enable signal being triggered, writing an unmasked data portion of the external data into a data storage unit of a computer memory by a writing unit; triggering a read enable signal at the time of the write enable signal being triggered and reading the unmasked data portion from the data storage unit by a reading unit while reading a third data portion corresponding to the masked data portion from the data storage unit; merging the unmasked data portion and the third data portion to a merged data and generating parity bits from the merged data by an error correction code encoding circuit; and writing the parity bits into a parity bit storage unit of the computer memory.

Abstract: A computing device writes data across storage devices in an erasure-coded system. The computing device computes data blocks and parity blocks from data and computes a portion of the data to be stored in the system. The computing is performed by one or more controllers included in a redundant array of an independent disks controller. The computing device provides the locations of the data blocks and the parity blocks in storage devices of an erasure-coded system. The location is determined using one or more placement nodes. The placement nodes are configured for managing placement schemes of data blocks and parity blocks on the storage devices.

Abstract: Methods, systems and apparatus for storing data by an ECC memory are provided. In one aspect, when an ECC memory configured to be used for data blocks with a first data length is used for data blocks with a reduced second data length, a method includes storing at least one data block with the second data length in a data bit storage part of a storage array and storing parity bits generated for only one data block of the at least one data block according to a relevant encoding rule in a parity bit storage part of the storage array. When the at least one data block is two or more data blocks, one or more judgment bits, which indicate that the stored parity bits correspond to the only one data block, are stored in one or more storage bits of the parity bit storage part that are not occupied.

Abstract: A computer memory access method includes: receiving external data with a prefetching length, the external data having an unmasked first data portion and a masked second data portion; writing the unmasked first data portion to a corresponding data storage unit of a computer memory by a writing unit and reading a third data portion corresponding to the masked second data portion from the data storage unit by a reading unit; producing modified external data by merging the unmasked first data portion and the third data portion in place of the masked second data portion; generating parity bits from the modified external data by an error correction code encoding circuit according to a given rule; and then writing the parity bits to a parity bit storage unit of the computer memory by the writing unit, in substitution of previous information in the parity bit storage unit.

Abstract: A method includes, in a memory that includes two or more memory units, storing a code word of an Error Correction Code (ECC) that is representable by a plurality of check equations, such that a first part of the code word is stored in a first memory unit and a second part of the code word is stored in a second memory unit. A subset of the check equations, which operate only on code word bits belonging to the first part stored in the first memory unit, is identified. The first part of the code word is retrieved from the first memory unit, and a count of the check equations in the identified subset that are not satisfied by the retrieved first part of the code word is evaluated. One or more readout parameters, for readout from the first memory unit, are set depending on the evaluated count.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Abstract: A memory device includes a memory array suitable for storing write data of the memory device and providing the stored data as read data of the memory device, a programmable storage unit suitable for storing information for the memory device, a command decoder suitable for storing decoding one or more command signals, and generating a write command for writing the write data, a read command for outputting the read data, and an information read command for outputting information stored in the programmable storage unit, a control unit suitable for controlling the information stored in the programmable storage unit to be sequentially read in response to activation of the information read command, and an output unit suitable for outputting the read information to an outside of the memory device in response to the information read command.

Abstract: A semiconductor device includes a memory region configured to include a plurality of banks and a redundancy region within each of the banks and an error check and correction (ECC) region configured to detect an address of the memory region at which an error has occurred and correct a defect of the memory region by replacing the address at which the error has occurred with a redundancy line of the redundancy region based on address information.

Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.

Abstract: A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault value to the stuck-at fault value. The control circuit is operable to generate encoded data bits by inverting each of the data bits having a different value than the stuck-at fault value of the corresponding one of the memory cells and by maintaining a digital value of each of the data bits having the stuck-at fault value of the corresponding one of the memory cells. The control circuit is operable to prevent any of the data bits from being stored in the memory cells determined to have unstable values. The control circuit is operable to generate redundant bits that indicate at least one operation to perform on the encoded data bits to regenerate the data bits.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.

Abstract: A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.

Abstract: An exemplary method for accessing a flash memory. The method comprising obtaining a first random sequence; utilizing the first random sequence as a first seed for generating a second random sequence, wherein the first random sequence is not equivalent to the second random sequence; scrambling data according to the second random sequence for generating scrambled data; performing an error correction encoding operation upon the first random sequence and the scrambled data for generating parity check code; and storing the scrambled data and the parity check code to the flash memory.

Abstract: A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.

Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.

Abstract: A semiconductor storage device according to the present embodiment comprises a memory cell array including a plurality of memory cells. An output part is configured to output data based on a strobe signal. An error correction part is configured to correct an error in first data read from the memory cell array. The output part fixes level of the strobe signal when outputting the first data, if the number of error bits of the first data exceeds a first number, he error correction part being capable of correcting error of the first number in the first data.

Abstract: A method begins by a processing module storing data files utilizing a dispersed storage error coding function that includes a pillar width parameter and a decode threshold parameter. The method continues with the processing module determining whether to adjust redundancy of the dispersed storage error coding function based on performance of the DSN. When the redundancy of the dispersed storage error coding function is to be adjusted, changing a ratio between the pillar width parameter and the decode threshold parameter and adjusting storage of one or more sets of the plurality of sets of encoded data slices based on the changing of the ratio.

Abstract: Methods and apparatus are provided for reading and writing data in q-level cells of solid-state memory, where q>2. Input data is encoded into codewords having N qary symbols, wherein the symbols of each codeword satisfy a single-parity-check condition. Each symbol is written in a respective cell of the solid state memory by setting the cell to a level dependent on the qary value of the symbol. Memory cells are read to obtain read signals corresponding to respective codewords. The codewords corresponding to respective read signals are detected by relating the read signals to a predetermined set of N-symbol vectors of one of which each possible codeword is a permutation.

Abstract: A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

Abstract: A method begins by a dispersed storage (DS) processing module of a dispersed storage network (DSN) sending a plurality of sets of encoded data slices to DSN memory for storage in accordance with a plurality of sets of DSN data addresses. The method continues with the DS processing module generating retrieval data that is based on a data object number and data storage information. The method continues with the DS processing module dispersed storage error encoding the retrieval data to produce a set of encoded retrieval data slices and generating a set of DSN retrieval data addresses based on the data name and on retrieval data storage information. The method continues with the DS processing module sending the set of encoded retrieval data slices to the DSN memory for storage in accordance with the set of DSN retrieval data addresses.