Abstract: A memory system according to the embodiment comprises a p-adic number converter unit operative to convert ?-digit, h-bit symbols to a k-digit, p-adic data word (p is a prime of 3 or more); an encoder unit operative to generate, from the p-adic data word, a code C composed of a residual field Zp of the prime p; a memory unit operative to store the code C as write data; an error correcting unit operative to apply an operation using a syndrome S generated from read data Y for error correcting the read data Y to regenerate the code C; a decoder unit operative to reverse-convert the code C to regenerate the p-adic data word; and a binary converter unit operative to convert the data word to a binary number to regenerate the binary data D.

Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in 16ASPK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.

Abstract: A stacked semiconductor memory device comprises an error correction code (ECC) controller that controls the number of bits in an ECC word and corrects errors in memory cell array layers using the ECC word.

Abstract: A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.

Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in 16ASPK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.

Abstract: A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K? is determined that is related to K?, where K? from a set of sizes; wherein the set of sizes comprise K?=ap×f, pmin?p?pmax; fmin?f?fmax, wherein a is an integer and f is a continuous integer between fmin and fmax, p takes integer values between pmin and pmax, a>1, pmax>pmin, pmin>1. The information block of size K is padded into an input block of size K? using filler bits, if needed. Encoding is performed using the original input block and the interleaved input block to obtain a codeword block using a turbo encoder. The codeword block is transmitted through the channel.

Abstract: A system and method for detecting and correcting errors in a memory in a device includes generating an error value of data stored at first predetermined locations in a first memory. The generated error value is compared to a corresponding error value stored in an error memory, each value in the error memory being calculated from at least two data values stored at predetermined locations in the first memory. The data stored in the first predetermined locations of the first memory is rewritten with data stored in first predetermined locations of a second memory if the generated error value is different than the corresponding error value stored in the error memory, the data stored in the second memory being the same as the data stored in the first memory.

Abstract: A concatenated channel decoding method wherein the bits of a set of N1 bits decoded using a first iterative block decoding algorithm and intended to be decoded using a second block decoding algorithm, are sent in parallel in at least one subset of P bits to a buffer for temporary storage. The decoding method comprises receiving in parallel at least one subset of Q bits belonging to the set of N1 bits sent to the buffer, detecting errors with the help of the second decoding algorithm, based on the bits decoded using the first decoding algorithm, and correcting the bits stored in the buffer as a function of possible errors detected. Detecting errors and/or the correcting the stored bits comprise a parallel processing of the bits of each subset of Q bits received.

Abstract: A method of communicating over an H1 Fieldbus network is provided. The communication over the H1 Fieldbus network employs an advanced form of error correction. In one embodiment, the advanced form of error correction utilizes low-density parity check codes; while in another embodiment, the advanced error correction employs turbo codes. The use of the advanced error correction with the H1 foundation Fieldbus network allows for higher data transmission speeds than 31.25 kbps and/or lower signaling levels than used currently.

Abstract: An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.

Abstract: Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.

Abstract: A semiconductor memory module comprises a control chip for driving ECC memory chips and further memory chips. The memory chips are arranged in two rows on a top side and a bottom side of the module circuit board. The ECC memory chips are arranged centrally on the module circuit board alongside the rows of the memory chips. A control bus connects the ECC memory chips and also the memory chips to the control chip. In a region remote from the control chip, the control bus branches in a contact-making hole into a first partial bus, to which a first group of memory chips are connected, and a second partial bus, to which a second group of memory chips are connected. The ECC memory chips are likewise connected to the control bus via the contact-making hole. Since the ECC memory chips are not arranged directly under the control chip, a bus branch directed backward is not required. As a result, space considerations on the module circuit board are eased and signal integrity on the control buses is improved.

Abstract: A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

Abstract: A memory controller, system, and methods are disclosed. The system comprises a memory controller interconnected to a plurality of memory chips. Each memory chip stores data at a plurality of locations. The memory controller performs a sparing transaction comprising reading data from a given location of one or more of the memory chips including a first memory chip, writing the data to a given location of one or more of the memory chips including a second memory chip, wherein during writing, data from the first memory chip is written to the second memory chip, and allowing additional memory transactions directed to the memory chips between the start of reading and the end of writing unless the additional memory transaction is targeted to the given location. In a further embodiment, the sparing transaction comprises correcting errors in the data before writing the data.

Abstract: Embodiments of the present invention provide techniques for detecting and correcting encoded data. In one embodiment, a system for detecting and correcting errors in a plurality of data bits comprises a static memory configured to store a plurality of data bits; a systematic encoder configured to convert the plurality of data bits into a codeword; a systematic parity check encoder configured to convert the codeword into a syndrome; and a syndrome decoder configured to evaluate the syndrome based on preset criteria used to determine whether the syndrome corresponds to an uncorrectable error. A binary [16, 8, 5] code is used to encode the plurality of data bits.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for using the same memory type for both error check and non-error check systems. In an embodiment, a memory device is capable of operating in an error check mode and in a non-error check mode. The memory device includes an output having N error check bit paths for every M data bit paths. In one embodiment, the memory device is to transfer N error check bits with a corresponding M data bits, if the memory device is operating in an error check mode. Other embodiments are described and claimed.

Abstract: A method for automatically calibrating intra-cycle timing relationships between command signals, data signals, and sampling signals for an integrated circuit device. The method includes generating command signals for accessing an integrated circuit component, accessing data signals for conveying data for the integrated circuit component, and accessing sampling signals for controlling the sampling of the data signals. A phase relationship between the command signals, the data signals, and the sampling signals is automatically adjusted to calibrate operation of the integrated circuit device.

Abstract: A device for storing blocks of bits intended to be decoded according to a block decoding algorithm. The blocks are likely to belong to a given category out of a first category and a second category. The first category corresponds to a first given block size, and the second category corresponds to at least one second given block size less than said first block size. The storage device comprises three storage elements having a size suitable for storing one block of the first category each, and at least two of which are structured to store either one block of the first category, or one block of the second category or a number of blocks of the second category simultaneously.

Abstract: Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses ×4 bit DRAM devices organized in a code word of 128 data bit words and 16 check bits. These 16 check bits are generated in such a way as to provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 128 bit word, with single bit correction across the word as well. Each device can be thought of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.

Abstract: A method for predicting and preventing uncorrectable errors that may occur while accessing memory in a computer system. The method involves detecting two or more correctable errors from two or more different physical addresses on each of two or more different bit positions from the same DIMM within a specified period of time, with all of the correctable errors occurring within the same checkword. The method also involves detecting two or more correctable errors from two or more different physical addresses on each of three or more different outputs from the same DRAM within a specified period of time, as long as the three outputs do not all correspond to the same relative bit position in their respective checkwords. This allows a computer system which encounters correctable errors to continue to reliably operate without the unnecessary replacement of functioning memory systems.

Abstract: A decoding apparatus includes a state variable calculation unit which calculates a second state variable based on a first context variable and a first state variable which are stored in a first memory unit and a second memory unit, respectively, and determines a selection signal representing a symbol as a result of arithmetic decoding processing. A context variable calculation unit calculates a second context variable based on the first context variable and the selection signal and updates the first memory unit. A re-normalization unit calculates a third state variable by using the coded data and the second state variable and updates the second memory unit. The state variable calculation unit outputs the determined selection signal that is usable in processing of a succeeding step without waiting for the operations of the context variable calculation unit and the re-normalization unit.

Abstract: A system and method for providing error correction and detection in a memory system. The memory system includes a plurality of memory devices, and error detection and correction logic. The error detection and correction logic includes instructions for generating an error correction code (ECC) word that includes bits from two more of the memory devices and from different memory device transfers.

Abstract: A method and apparatus for monitoring an electronic control system, where code of a memory is, in a context of ongoing instruction accesses, transferable via a word line out of the memory to a control unit having a specific word width encompassing code of a plurality of memory cells of the memory and where an additional datum is created in each case for the code of a word width and is storable in the memory, may include an arrangement that, outside the ongoing instruction accesses, checks an entire code of the memory by selecting for each word width a single memory cell to thereby activate a complete word line, that creates a check datum from code of the complete word line, and that compares the check datum with the stored additional datum.

Abstract: A method and a system for the detection and correction of errors in memory systems is disclosed. In one embodiment, a method of error detection in a memory system having a plurality (m>1) of memory devices includes generating check bits for each of a plurality of data sets, dividing each memory device into a plurality (n>1) of segments. The plurality of data sets are interleaved to form a plurality (p>1) of words. Each word includes at least one segment from two or more of the memory devices. Detection and correction may utilize oneor more parallel Reed-Solomon decoder and encoder. The system and method allow for the efficient detection and/or correction of memory device errors and bit errors in one or more memory devices.

Abstract: A method for controlling application of an erasure mode of an error correction code (ECC) algorithm in a memory subsystem includes detecting errors in cache lines retrieved from the memory subsystem using the ECC algorithm. The method also analyzes the errors to detect a repeated bit pattern of data corruption within the cache lines, correlates the detected repeated bit pattern of data corruption to one of a plurality of domains of the memory subsystem, and applies the ECC algorithm to erase bits associated with the detected repeated bit pattern from cache lines retrieved from the correlated domain of the memory subsystem.

Abstract: A server computer system receives error data including a physical memory address along with configuration data associated with the physical memory address, and may also include error syndrome data. The server computer system includes a memory error decoder component that is operable to process the physical memory address and configuration data to generate a memory bus address corresponding to the physical memory address. The memory error decoder also processes the error syndrome data to generate the location of an erroneous bit within a group of data bits and all possible electrical routes of the erroneous data bit within a failing computer system. The server system outputs the memory bus address and the location and electrical route of the erroneous data bit.

Abstract: Provided is a hybrid flash memory device, a memory system, and a method of controlling errors. The hybrid flash memory device includes a data storage block with first and second data storage regions of flash memory cells, and error control block implementing first and second error control schemes, such that a data access operation directed to data stored in the first data storage region selects the first error control scheme, and a data access operation directed to data stored in the second data storage region selects the second error control scheme.

Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

Abstract: A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.

Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

Abstract: This invention is a system and method for simulating performance of one or more data storage systems. This invention may be used in many useful ways including for configuring or modeling a data storage environment, problem isolation, and general design.

Abstract: A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

Abstract: A system having memory modules for storing nibbles of a word. The nibbles include an error correction/detection code. A memory controller is response to clock pulses to produce a read command. A synchronizer is responsive to the read nibbles and an associated read strobe signal for synchronizing the read nibbles and the read strobes to the clock pulses. A detection section is responsive to the clock pulses and the read command for producing a time window representative of a time duration during which each of the read strobes is expected. The detection system is responsive to each one of the read strobes and the produced time window for producing, for each one of the read strobes, a corresponding one of a plurality of NIBBLE ERROR signals. Each one of the NIBBLE ERROR signals indicates whether the corresponding one of the read strobes is within the produced window or is absent from such window.

Abstract: A method for hardening an extensible firmware framework and system in which the framework is implemented. In accordance with the method, a resource access policy that defines rules to allow or disallow access to designated system resources, such as memory and I/O, is defined. During execution of firmware-based event handlers, event handler code may seek to access a designated system resource. In response thereto, access to the system resource may be determined based on a security status of a firmware-based event handler in consideration of any applicable rules defined by the resource access policy. For example, a resource access policy may allow only secure event handlers to access selected portions of memory, while preventing non-secure event handlers from accessing the same. In this manner, errant and malicious event handlers are prevented from damaging critical resources.

Abstract: The invention relates to a data transmission method and a radio system that comprises a first (260) transceiver and a second transceiver (264) that are in radio contact with each other. The first transceiver (260) comprises means (500, 504) for forming data blocks for transmission in such a manner that the data blocks are given identifiers for identification. The second transceiver (264) comprises means (512) for receiving data blocks transmitted and retransmitted by the first transceiver, and means (524) for detecting a failure in receiving a data block. The second transceiver (264) comprises means (530) for maintaining information on the position of a window belonging to a finite identifier space, and means (524) for comparing the identifiers of the re-received data block and the earlier received data block with each other and for defining the data blocks as the same, and means (524) for combining the data blocks defined as the same.

Abstract: Reading and writing data from a plurality of memory devices. A code word having a plurality of bits is partitioned into nibbles. Adjacent nibbles are stored on a common physical medium. The failure of the common physical medium results in errors in adjacent nibbles of a reconstructed code word.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit, a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: A memory subsystem comprising: a command register in operable communication with a plurality of memory devices via a plurality of command buses. The plurality of memory devices is arranged into symbol slices and each symbol slice is configured to be part of a single error correction code packet. Each command bus of the plurality of command buses is configured to interface between the command register and each memory device in a particular symbol slice. A method of command bus redundancy comprising: configuring a plurality of memory devices into symbol slices, each symbol slice configured to be part of a single error correction code packet; establishing a plurality of command buses, each command bus configured to interface with each memory device in a particular symbol slice; and configuring a command register with sufficient command bus drivers to support each command bus of the plurality of command buses.

Abstract: A codeword for use in error correction of digital optical media, the codeword having a plurality of data symbols and a plurality of parity symbols, and includes an augmented channel word which can be read as either a first value or a second alternate value. The augmented channel word is one of the plurality of data and parity symbols, wherein the augmented channel word retains its value irrespective of any error correction performed.

Abstract: The invention concerns a data storage method enabling error detection and correction in an organized storage for reading and writing words of a first number (m) of bits and optionally for modifying only part of such a word, comprising the following steps which consist in: associating an error detection and correction code with a group of a second number (k?1) of words; and at each partial writing in the group of words, calculating a new code of the modified group of words; performing a verification operation and, if an error occurs, carrying out an error correction of the modified word and/or of the new code.

Abstract: Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The bits in the adjacent bit pair domain are processed by an error correction unit sequentially or in parallel, and then recombined to be written into memory or transmitted to a requestor.

Abstract: Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The adjacent bit pair domain data is transmitted over a bus having a plurality of data paths, such that data bits associated with a given memory device are transmitted over a same data path.

Abstract: A method and apparatus for performing parity bit generation. The apparatus of the present invention comprises a parity bit generator that multiplies words comprising message bits by a partial parity multiplication sub-matrix to generate intermediate parity values, and recursively adds (modulo-2) respective intermediate values together so that by the end of the recursive process, a final parity vector exists. This final parity vector can then be added to a message word to create a code word. By recursively using the partial parity multiplication sub-matrix in this way, the number of gates needed to perform parity bit generation is kept relatively small. Consequently the amount of power consumed by the parity bit generator during parity bit generation is relatively small. This is in contrast to typical parity bit generators, which multiply all of the message bits by a full parity multiplication matrix without recursion.

Abstract: A memory controller may include a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be written to memory, where the memory includes a plurality of memory devices arranged on a plurality of memory modules. Each of the plurality of memory modules includes a plurality of the plurality of memory devices. The check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block. The plurality of check bits are defined to provide at least detection of a failure of one of the plurality of memory modules. The check/correct circuit is coupled to receive the encoded data block from the memory, and is configured to detect the failure of one of the plurality of memory modules responsive to decoding the encoded data block.

Abstract: A semiconductor memory device is disclosed which comprises a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of the normal data section, a data buffer for temporal stage of read data from the cell array and write data into the cell array, and an ECC circuit for generating the check data to be stored in the parity data section from write data as input during data writing, and for performing error check and correction of data read out of the normal section based on the data read out of the normal data section and the check data read out of said parity data section during data reading. N-bit parallel data transfer is performed between the data buffer and normal data section whereas m-bit parallel data transfer is done between the data buffer and external input/output terminals (where m and n are integers satisfying m<n).

Abstract: A codeword and a method for generating a codeword is provided. The codeword may be used in error correction of digital optical media and DVDs, the codeword having a plurality of data symbols and a plurality of parity symbols, and includes an augmented channel word which can be read as either a first value or a second alternate value. The augmented channel word is one of the plurality of data and parity symbols, the augmented channel word retaining its value irrespective of any error correction performed.

Abstract: A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

Abstract: A technique for handling errors in a memory system. Specifically, a new dual mode ECC algorithm is provided to detect errors in memory devices. Further, an XOR memory engine is provided to correct the errors detected in the dual mode ECC algorithm. Depending on the mode of operation of the dual mode ECC algorithm and the error type (single-bit or multi-bit), errors may be corrected using ECC techniques. If X16 or X32 memory devices are implemented, a technique for striping the data from each memory device is implemented to detect errors in the X16 and X32 devices.

Abstract: A system and method for efficient parity mirroring between controllers of an active-active controller pair in a redundant array of inexpensive disks (RAID) system is disclosed. When a second controller in an active-active controller pair receives new data to be written to a disk array, it mirrors the new data to a first controller in the active-active controller pair. The second controller then computes new parity for the data stripe associated with the new data. The second controller then opens a parity log and mirrors logical block address (LBA) information for the new data to a first controller in the active-active controller pair. In the event of a failure of the second controller after mirroring the LBA information and prior to completing the write operation, the first controller uses the LBA information to complete the write operation, assuring that the new data and new parity are properly stored on the disk array.

Abstract: A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.