Abstract: The invention describes a method and an arrangement for an arithmetic encoding and decoding of binary states and a corresponding computer program and a corresponding computer-readable storage medium, which may in particular be used in digital data compression.

Abstract: A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this (146,130) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.

Abstract: The invention relates to an error-correction method for use in a process of decoding cross-interleaved Reed-Solomon code (CIRC) that corrects errors in data stored as C1 code words and C2 code words in a memory with several locations, each of said locations containing a data byte of said data, and an apparatus performing said method. The new method implies specific regulations for defining which data words are to be used for C1 and C2 decoding and for the processing order. The system memory for a deinterleaver implementation can be of a smaller size as compared to conventional memories. In addition, only a single CIRC decoder needs to be used for performing the process of decoding cross-interleaved Reed-Solomon code.

Abstract: According to one embodiment, a method is disclosed. The method includes interleaving a first error correction code with a second error correction code to generate a third error correction code that provides chip-kill capabilities for a memory system.

Abstract: A system for building checksums efficiently builds a checksum of various data values that are stored in different memory units of a computer system. During the checksum build process, data stores to the memory locations storing the various data values are enabled, thereby enabling the checksum to be built without significantly impacting the performance of the computer system.

Abstract: A shared error correcting circuit reduces memory overhead by sharing a fixed number of ECC bits among two or more memory units in a semiconductor memory. A single ECC block is used to generate check bits and syndrome bits. The ECC block tests each of the memory units by using the total number of ECC bits available in the ECC cells. Thus, the memory overhead is reduced from that in standard ECC designs.

Abstract: A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than 1 and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits.

Abstract: The memory array of a server device organizes conventional desktop memory so as to be able to perform error correction. Each one of several Rambus Direct Random Access Memory (“RDRAM™”) devices transfers one group of bits of a data word across a corresponding channel. An additional RDRAM™ device transfers data used for performing error correction, including chip kill, for on the data stored in the RDRAM™ devices.

Abstract: An improved chip sparing system and method of operation are provided in which a failed chip is detected even if there are multiple errors on a single chip and one or more spare chips are provided within the system; and in which spare chips or space chip I/Os are dynamically inserted into the system upon detection of a failed chip or chip I/O without the necessity of shutting down and rebooting the system or even without the necessity of re-initializing the memory.

Abstract: A semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m×n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks.

Abstract: According to one embodiment, a method is disclosed. The method includes interleaving a first error correction code with a second error correction code to generate a third error correction code that provides chip-kill capabilities for a memory system.

Abstract: A method of checking for errors in a set associative cache array, by comparing a requested value to values loaded in the cache blocks and determining, concurrently with this comparison, whether the cache blocks collectively contain at least one error (such as a soft error caused by stray radiation). Separate parity checks are performed on each cache block and if a parity error occurs, an error correction code (ECC) is executed for the entire congruence class, i.e., only one set of ECC bits are used for the combined cache blocks forming the congruence class. The cache operation is retried after ECC execution. The present invention can be applied to a cache directory containing address tags, or to a cache entry array containing the actual instruction and data values. This novel method allows the ECC to perform double-bit error as well, but a smaller number of error checking bits is required as compared with the prior art, due to the provision of a single ECC field for the entire congruence class.

Abstract: A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits.

Abstract: A system for accessing a memory comprising memorization subsystems (100-1 to 100-10), e.g. standard Dual In-line Memory Modules, wherein the words to be stored are split so that several memorization subsystems are used to store one word and its associated Block Error Code (BEC) bits includes logical insulation means (145-1 to 145-10) that are associated to each memorization subsystem further comprising a backup memorization subsystem (100-11) associated to logical insulation means (145-11).

Abstract: Briefly, in accordance with one embodiment of the invention, a method of encoding data signals for storage to tolerate failure of a storage unit of a storage medium includes the following. For N+2 storage units, N being a positive integer, each of the storage units being divided into N storage blocks, 2N blocks of priority signals are produced from (N)(N) blocks of data signals. The N(N+2) blocks of parity and data signals are allocated over the N+2 storage units of the storage medium so that the 2N blocks of parity signals are not exclusively stored in two of the N+2 storage units.

Abstract: A microprocessor for executing exact branch targeting is disclosed. A microprocessor contains a fetch stage for fetching and receiving instructions from memory at a memory address specified by a program counter. The instructions received by the fetch state include conditional branch instructions and conditional branch calculation instructions. The conditional branch calculation instructions underlie the conditional branch instructions in that the conditional branch is taken or not depending upon the results of the conditional branch calculation instructions. An execution stage within the microprocessor executes the conditional branch calculation instructions once decoded by a decode stage. Once executed, the execution stage writes the results thereof into a branch FIFO buffer contained within a branch target circuit coupled to the fetch stage. Subsequent thereto, the fetch stage receives a conditional branch instruction.

Abstract: The bits of a data block are logically partitioned into an array that includes a number of columns equal to a number of memory devices and a number of rows equal to a number of bits of the data block stored in each memory device. Each memory device contributes one bit to each row. In one embodiment, the bits from a memory device are stored in the same column position of all the rows. One check bit is associated with each row. The check bit is computed by taking the parity of the row associated with the check bit and zero or one column. Each column is assigned to at least four check bits. If a check bit has a column assigned to it, then the check bit is generated by computing the parity of the associated row and the column assigned to the check bit. Alternatively, if the check bit does not have a column assigned to it, the check bit is generated by computing the parity of the row assigned to the check bit only. Each column is assigned to at least four check bits and is assigned to an even number of check bits.

Abstract: A system with a ferroelectric memory has a low probability of soft error thereby decreasing the possibility of serious damage to the system that might result from soft errors. The ferroelectric memory is provided with an overwrite-inhibited memory block 122 for storing the OS (Operating System) and applications, and an overwrite-free memory block 123 which is a work area. The overwrite-inhibited memory block 122 includes a parity bit storage 125. A process for checking and correcting error performed about once a day. A command for starting the error checking and correcting procedures is triggered by a switch such as power source switch. When an error occurs in the ferroelectric memory 120, it is possible to recover the function of the system.

Abstract: The bits transmitted are coded according to the product of at least two systematic block codes. Iterative decoding is applied in order to determine, at each code word search step, a data matrix ({R}) and a decision matrix ({D}) used for the following step. The new decision matrix is determined at each step by decoding the lines or columns of the input matrix, and the new data matrix is determined taking into account the correction terms which increase the reliability of the decoding on each iteration. The coding and decoding circuits (17) are rendered programmable by a shortening technique allowing selection of the number k-X of non-redundant information bits per block to be coded. Known values are assigned to the other bits, the positions of which are uniformly distributed according to each dimension of the matrices.

Abstract: Apparatus and methods for storing predefined information with error correcting code (ECC) in a direct access storage device are provided. Predetermined information is identified and loaded to an ECC generator for customer data to be read and written. The identified predetermined information includes an address for customer data to be read and written. The customer data is written and loaded in parallel to the ECC generator. Then the generated ECC that reflects the pre-loaded predetermined information is written at the end of the written customer data. The customer data and ECC is read and loaded in parallel to the ECC generator. Errors in the predetermined information that is not written to the disk surface, can be detected from the read ECC.

Abstract: The bits transmitted are coded according to the product of at least two systematic block codes. Iterative decoding is applied in order to determine, at each code word search step, a data matrix ({R}) and a decision matrix ({D}) used for the following step. The new decision matrix is determined at each step by decoding the rows or columns of the input matrix, and the new data matrix is determined taking into account the correction terms which increase the reliability of the decoding on each iteration. The coding and decoding circuits (17) are rendered programmable by a puncturing technique allowing selection of the number of bits transmitted per coded block, the punctured bits preferably having uniformly distributed positions according to each dimension of the matrices.

Abstract: A semiconductor storage unit includes: a first PROM; a second PROM for storing parity data based on data stored in the first PROM; an error detecting circuit for detecting an error in read data outputted from the first PROM on the basis of the parity data outputted from the second PROM to generate an error detection signal; an error correcting circuit for outputting the data read out from the first PROM as it is when no error detection signal is supplied thereto, and for outputting error corrected data when the error detection signal is supplied thereto; a specific-mode detecting circuit for generating a specific-mode detection signal when detecting a specific mode; and a different-data generating means for generating data different from data outputted from the error correcting circuit as output data when both of the error detection signal and the specific-mode detection signal are generated.

Abstract: Memory read circuit and method for reducing the number of the memory read cycles required for ECC. The memory read method for ECC of a data memory, which stores sector data reproduced from a compact disc in a decoding device of a compact disc-ROM drive, includes the step of reading the data memory in a page mode read cycle having a page length which corresponds to a physical address where symbols for ECC are stored at the data memory.

Abstract: A system for N-bit part failure detection using n-bit error detecting codes where n is less than N is disclosed. In a computer system having storage devices N bits wide and an error detection and correction capability of less than N bits, bit assignments are made so that storage device failures will be detectable because of the manner the effect of a part failure is distributed among multiple codewords. Consequently 8 and 16 bit wide DRAMs may be used in a memory system using error detection and correction codes which are not capable of detecting 8 or 16 bit errors in a codeword, and still preserve the ability to detect the worst errors possibly caused by a part failure.

Abstract: A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and includes memory check bits, memory address bits, and memory data bits, and an error detection and correction device for detecting an error in the memory address bits using the memory check bits and for detecting an error in the memory data bits using the memory check bits. The CPU can include a processor from the Pentium.RTM. Pro family of processors. The error detection and correction device generates a syndrome table which includes a plurality of entries mapped to correctable or uncorrectable errors, in which a detected multiple-bit error in the memory data bits is mapped to an uncorrectable error entry and a detected error in the memory address bits is mapped to an uncorrectable error entry.

Abstract: A memory card includes an error-correction-code (ECC) controller for generating ECCs, an ECC memory for storing ECCs generated by the ECC controller and an address converter for converting between addresses of the ECC memory and those of a main memory for storing data. The ECC controller generates an ECC to be stored in the ECC memory when a control data is input and the address converter fetches a relationship between an address of the ECC memory at which the generated ECC is stored and that of the main memory at which the control data is stored. Upon reading data stored in the main memory, error check and error correction operations are executed for the control data.

Abstract: A memory system for performing error detection and correction including a memory device that stores a plurality of data words, where each data word has a plurality of data bits and at least one associated check bit. The memory system further includes memory control circuitry that reads a plurality of data words in multiple cycles to form a block word that includes a sufficient number of check bits to perform detection of double bit errors and correction of single bit errors. A 72-bit block word is formed by grouping smaller data words retrieved from the memory device. For a 9-bit device with eight data bits and one check bit, eight burst cycles may be used to retrieve a 72-bit data block. Similarly, for 18-bit devices, four burst cycles may be used to retrieve the data block and for 36-bit devices, two burst cycles may be used to retrieve the data block. The memory system further includes error logic that receives and performs error detection and correction upon the block word.