Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.

Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.

Abstract: Provided is a method for decoding a staircase code. The method includes following steps: soft information updating is performed on S initial encoding blocks in a staircase code to obtain a first information block, and last S?T encoding blocks in the first information block and T newly-added encoding blocks are updated to obtain a second information block; decoding is performed on first T encoding blocks in the first information block and first S?T encoding blocks in the second information block to obtain a third information block; and following operations are repeatedly performed: S?T information blocks are selected, the soft information updating is performed to obtain S updated information blocks, and the S updated information blocks are used as a new second information block; and decoding is performed to obtain a new third information block, and information of first T blocks is outputted as the output of the decoder.

Abstract: A transmitter generates determiners from data vectors representing payload information, each determiner representing parity information dependent on the payload information. The transmitter encodes the determiners to generate a nub vector representing compressed parity information dependent on the parity information, wherein the encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the determiners and then calculating the nub vector from the codewords, at least one of the codewords being calculated from at least one recursion of a mathematical operation, and at least one of the codewords comprising more than 6 terms. The transmitter transmits signals representing the data vectors and the nub vector to a receiver, where recovery of the data vectors at the receiver involves sequential decoding of the FEC codewords, wherein at least one codeword decoded earlier in the decoding enhances an estimate of at least one codeword decoded later in the decoding.

Abstract: Disclosed are devices, systems and methods for reducing the latency of a quasi-cyclic linear code decoder. An example method includes receiving a noisy codeword, the codeword having been generated from a quasi-cyclic linear code and provided to a communication channel prior to reception by the decoder; computing a syndrome based on the noisy codeword; generating a plurality of memory cell addresses, a first memory cell address being a function of the syndrome and subsequent memory cell addresses being within a predetermined address range of the function of the syndrome; reading, in a parallel manner to reduce the latency of the decoder, a plurality of error patterns from the plurality of memory cell addresses and computing a checksum for each of the plurality of error patterns; and determining, based on the checksum for each of the plurality of error patterns, a candidate version of the transmitted codeword.

Abstract: Systems and methods for secure communication between a vehicle and a portable communication device. One system includes a vehicle access system included in the vehicle. The vehicle access system is configured to wirelessly receive a shuffled message from the portable communication device, de-shuffle the shuffled message at a bit level to obtain a message, wherein de-shuffling the shuffled message at a bit level includes exchanging one bit at a first indexed position within the shuffled message with one bit at a second indexed position within the shuffled message, and initiate a vehicle operation based on the message.

Abstract: Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels.

Abstract: A decoder configured to decode a representation of the codeword includes an error locator polynomial generator circuit. The error locator polynomial circuit is configured to generate an error locator polynomial based on a decode operation that includes iteratively adjusting values of a first polynomial, a second polynomial, a third polynomial, and a fourth polynomial. The error locator polynomial circuit is also configured to initialize the third polynomial based on even-indexed coefficients of a syndrome polynomial and initialize the fourth polynomial based on odd-indexed coefficients of the syndrome polynomial.

Abstract: A system for implementing variable T BCH encoders includes: a polynomial multiplier for multiplying a message polynomial by a difference polynomial to achieve a first value, wherein the message polynomial comprises data bits as coefficients and the difference polynomial comprises minimal polynomials that are present in a T error correcting code and are absent from a T??T error correcting BCH code; a shifter/zero-padder coupled with the BCH encoder, the shifter/zero-padder for multiplying the first value by xN-{tilde over (K)} to achieve a second value; a BCH encoder coupled with the polynomial multiplier, the BCH encoder for dividing the second value by a generator polynomial of the T error correcting BCH code and calculating a remainder based on the dividing to achieve a third value; and a polynomial divider for dividing the third value by the difference polynomial to achieve a fourth value comprising parity of the T??T error correcting BCH code.

Abstract: In one embodiment, a method includes reading a codeword stored to a memory, computing a syndrome word based on a product of the codeword and a parity check matrix derived from a linear block code, setting a flag to a first value indicating that the codeword includes no errors in response to a first determination requiring that the syndrome word is an all-zero vector, setting the flag to a second value indicating that the codeword includes exactly one single-bit error in response to a second determination requiring that the syndrome word equals a column of the parity check matrix, setting the flag to a third value indicating that the codeword includes an odd number of multiple bit errors in response to a third determination, and setting the flag to a fourth value indicating that the codeword includes an even number of multiple bit errors in response to a fourth determination.

Abstract: At least one example embodiment discloses a method of soft-decision Wu decoding a code. The code is one of a generalized Reed-Solomon type and an alternant type. The method includes obtaining a module of the code. The module is a sub-module of at least a first extension module and a second extension module. The first extension module is defined by a set of first type constraints and the second extension module is defined by a set of second type constraints. The first type constraints are applicable to a first interpolation algorithm and a second interpolation algorithm and the second type constraints are applicable to the first interpolation algorithm. The method further includes determining a basis for the first extension module and converting the basis for the first extension module to a basis for the module.

Abstract: Error-correcting circuit includes: component generating a first output from first and second inputs; error detector generating an error flag indicative of whether or not an error is detected in the first output, based on the first output, and the first and second inputs; correction generator generating a correcting output after a first time period beginning with a timing event, based on the first output, and the first and second inputs; and output generator generating an output after a second time period beginning with the timing event. If the error flag indicates a detected error then the second time period may be longer than the first time period, otherwise it may be not longer, and the error-correcting circuit output may include a combination of the first output and the correcting output whereby the detected error is corrected, otherwise the error-correcting circuit output may correspond directly to the first output.

Abstract: A method includes decoding, by a receiver device, a spread spectrum coded stream of information including a multiple codeword blocks. The decoding includes determining a number of invalid codewords in a particular block of codewords. Based on a first particular number of invalid codewords in the particular block of codewords, the particular block of codewords is demapped, and parity codewords of the particular block of codewords are discarded. Based on a second particular number of invalid codewords in the particular block of codewords, a subset of syndrome components is computed using one or more coding enumerations with an update procedure for the subset of syndrome components, if all of the subset components are zero an erroneous bit is found, otherwise coding enumerations continue, the particular block of codewords is demapped, and parity codewords of the particular block of codewords are discarded.

Abstract: A method for error correction, the method comprises receiving a codeword that comprises a payload and a redundancy section; error-correction decoding the codeword by applying a syndrome-based error correction process to provide an amended payload and an error-correction decoding success indicator; wherein the amended payload comprises an amended CRC signature and an amended payload data; calculating, using the amended payload CRC signature, a validity of the amended payload to provide a CRC validity result; estimating a number of errors in the redundancy section; and determining that the error-correction succeeded when the number of errors in the redundancy section did not exceed a threshold, the error correction success indicator indicates that the error-correction decoding failed, and the CRC validity result indicates that the amended payload is valid.

Abstract: A method begins by a processing module of a dispersed storage network (DSN) concatenating a plurality of independent data objects into a concatenated data object and performing a dispersed storage error encoding function on the concatenated data object to produce a set of data-based encoded data slices and a set of redundancy-based encoded data slices. The method continues with the processing module outputting the set of data-based encoded data slices to a first set of storage units for storage and outputting the set of redundancy-based encoded data slices to a second set of storage units for storage.

Abstract: The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2m). The circuit includes: a combined matrix unit, a number of first multiplexers, a number of registers and a number of second multiplexers. By designing the Chien's search circuit having several Chien's search matrices, with peripheral components, it is able to achieve applications for different code rates, different code lengths and even different m in GF(2m).

Abstract: A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.

Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.

Abstract: An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of XR, XG and XS according to p parallel computations and 2t syndromes; building up FP; building up F?; building up F?; building up matrix of [XSRG F?]; and designing a circuit which fulfills the operation of [XSRG F?].

Abstract: Methods and circuits are disclosed for forward-error-correction (FEC) decoding. A plurality of symbols are received in an interleaved format of rows and columns of the symbols. A plurality of FEC decoding iterations are performed on the plurality of symbols. Each decoding iteration performs FEC decoding of the rows of the plurality of symbols and performs FEC decoding of the columns of the plurality of symbols. After performing the decoding iterations, rows in error and columns in error of the plurality of symbols are determined. In response to the determined rows in error and the determined columns in error matching a deadlock pattern, symbols at intersections of the determined rows and columns in error are determined. Bits of one or more symbols of the determined symbols are inverted. After the inverting of the bits, one or more of the FEC decoding iterations are performed.

Abstract: A method for shortening latency of Chien's search and related circuit are disclosed. The method includes the steps of: determining a shifted factor, p; receiving a BCH codeword; computing a syndrome from the BCH codeword; finding an error-location polynomial based on the syndrome; and processing Chien's search for the error-location polynomial to find out roots thereof. p is a number of successive zeroes from the first bit of the BCH codeword, the Chien's search starts iterative calculations by substituting a variable of the error-location polynomial with a nonzero element in Galois Field, GF(2m), and the nonzero element ranges from ?p+1 to ?n, wherein n is a codelength of the BCH codeword and equals 2m?1, and m is a positive integer.

Abstract: A circuitry is proposed for the correction of errors in a possibly erroneous binary word v?=v?1, . . . , v?n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n? column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.

Abstract: A method of encoding user data into codevectors of an error correcting code, includes generating a first block of data symbols including user data symbols and dummy data symbols; encoding the first block using an ECC encoder to obtain a codeword comprising the first block of data symbols and a second block of parity symbols; and generating a codevector by selecting a user data portion of the user data symbols from the first block and a parity portion of the parity symbols from the second block. The sum of a number of the user data portion and a number of the parity portion is smaller than the sum of a number of the user data symbols and a number of the parity symbols of the second block.

Abstract: In one embodiment, a device is provided. The device includes a first formatting circuit configured to add zero padding bits to a received data block. An FEC encoder circuit is coupled to the first formatting circuit and is configured to determine parity bits for the data block at a first code rate. A second formatting circuit is coupled to the FEC encoder circuit and is configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate. The second code rate is less than the first code rate.

Abstract: Polynomial circuitry for calculating a polynomial having terms including powers of an input variable, where the input variable is represented by a mantissa and an exponent, includes at least one respective coefficient table for each respective term, each respective coefficient table being loaded with a plurality of respective instances of a coefficient for said respective term, each respective instance being shifted by a different number of bits. The circuitry also includes decoder circuitry for selecting one of the respective instances of the coefficient for each respective term based on the exponent and on a range, from among a plurality of ranges, of values into which that input variable falls.

Abstract: Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.

Abstract: A decoding circuit is disclosed that includes a decoding pipeline configured to receive a data block that includes a plurality of data symbols, encoded with a Reed-Solomon (RS) FEC coding thereafter further encoded by a second FEC coding. The data block also includes a first and second sets of FEC datagrams for correcting received words of the plurality of data symbols encoded with the RS FEC coding and second FEC coding, respectively. Each decoding stage of the pipeline is configured to decode the plurality of data symbols using the first and second sets of FEC datagrams. A post-processing circuit connected to an output of the pipelines is configured to perform bitwise RS decoding of ones of the plurality of data symbols in error.

Abstract: A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·?3ji+Zw2·?2ji+Zw1·?ji+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)?(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value ?vi= for the bit position i may then be determined on the basis of the error correction expression evaluated for ?ji.

Abstract: Techniques and mechanisms for handling data faults in a memory system which includes multiple integrated circuit (IC) dies, each die including a respective one of multiple memory arrays. In an embodiment, control logic monitors for a die failure of the multiple dies, and further monitors for a request to perform error correction for the multiple memory arrays. Each of the multiple memory arrays may store a respective vertical error correction code specific to data of that memory array. Another IC die may store a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code of a horizontal codeword which spans the multiple memory arrays. In another embodiment, the BCH code is available to decode logic for data recovery operations in response to a die failure, where the BCH code is further available to the decode logic for error correction operations when all of the memory arrays are operative.

Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.

Abstract: Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=pk, k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage by ensuring that q and s are uth and vth powers respectively of a common base r, where u and v are positive integers and k f u, whereby p(k/u)v=s.

Abstract: An error control decoding system decodes a codeword that includes a data word and two or more parity segments. The system includes a first decoder to decode the codeword by utilizing one or more first parity segments and the data word included in the codeword, and a second decoder to decode the codeword by utilizing one or more second parity segments and the data word included in the codeword, wherein the one or more first parity segments are different from the one or more second parity segments. An error estimation module estimates the number of errors in the codeword, and a controller selects which of the first decoder and second decoder to start decoding the codeword, wherein the selection is based on the estimate of the number of errors in the codeword provided by the error estimation module.

Abstract: Systems and methods are provided for recovering data stored in memory. A group of data is encoded using a first layer of code to form a first encoded group of data. Individual portions of the first encoded group of data are then encoded using a second layer of code to form a second encoded group of data. A processor may request access to an individual portion of the group of data. The encoded version of the requested individual portion is retrieved from memory and decoded using the second layer of code to recover the requested individual portion. If the recovery of the requested individual portion fails, the remaining encoded portions of the group are retrieved from memory and decoded using the first layer of code to recover the requested individual portion.

Abstract: The present disclosure relates to methods, systems, and computer-readable media for varying a memory size in a data stream processing while improving a connection degree sketch. Embodiments of the present disclosure may encode an input data by using an error coding technique to produce an encoded data, wherein the encoded data results in a modified memory size; generate a host connectivity using a set of parameters and applying a reverse sketching technique over the encoded data in order to obtain estimated encoded data; and decode the encoded data after the host connectivity is established using a decoding technique and obtaining an output data. The memory size of the output data may be proportional to the memory size of the input data.

Abstract: Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.

Abstract: Modulation and coding schemes are provided for improved performance of wireless communications systems to support services and applications for terminals with operational requirements at relatively low Es/N0 ratios and terminals at relatively high Es/N0 ratios. The new modulation and coding schemes provide new BCH codes, low density parity check (LDPC) codes and interleaving methods. The modulation and coding schemes also provide new modulation signal constellations.

Abstract: A set of one or more component syndromes associated with a turbo product code (TPC) codeword is obtained from a component syndrome buffer. Component decoding is performed on the set of one or more component syndromes.

Abstract: In one embodiment, a Chien search circuit includes a plurality of evaluation circuits, each configured to sequentially evaluate possible roots ?i in a respective subset of possible roots of an error location polynomial (?(x)). Each evaluation circuit includes a respective sub-circuit for each of a plurality of coefficients ?i (0?i?T) of the error location polynomial ?(x) having T+1 coefficients. Each sub-circuit is configured to calculate one term of the error location polynomial for each possible root ?i in the respective subset of possible roots. Each evaluation circuit is configured to evaluate the error location polynomial for each possible root in the respective subset of possible roots, as a sum of the terms calculated by the plurality of sub-circuits.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: In one embodiment, an encoder circuit is provided. The encoder includes an input circuit having a plurality of finite field subtraction circuits, each configured to receive a respective one of the sequence of symbols and subtract the symbol from a respective symbol of an intermediate polynomial to produce a respective feedback symbol. For each coefficient of a code generation polynomial, a first circuit is configured to multiply each feedback symbol by a respective constant corresponding to the coefficient to produce a first set of intermediate results. Each first set of intermediate results is summed to produce a second intermediate result. A buffer circuit of the encoder is configured and arranged to store the second intermediate results produced by the first circuit as the intermediate polynomial.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of symbols and (ii) a plurality of decision values both in response to detecting an encoded codeword. The second circuit may be configured to (i) generate a plurality of probabilities to flip one or more of the symbols based on the decision values, (ii) generate a modified probability by merging two or more of the probabilities of an unreliable position in the symbols and (iii) generate a decoded codeword by decoding the symbols using an algebraic soft-decision technique in response to the modified probability.

Abstract: An apparatus and a method for performing shortening and puncturing in case of performing encoding and decoding using a parity test matrix in a communication/broadcasting system are provided. The method includes determining a number of zero-padding bits, determining a number Npad of bit groups in which all bits are padded with zeros, padding the all bits within 0th to (Npad?1)th bit groups with zeros based on a shortening pattern, encoding information bits including the zero-padded bits to generate a codeword. Here, the shortening pattern is defined in a sequence of bit groups defined as 9, 8, 15, 10, 0, 12, 5, 27, 6, 7, 19, 22, 1, 16, 26, 20, 21, 18, 11, 3, 17, 24, 2, 23, 25, 14, 28, 4, 13, 29.

Abstract: Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.

Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.

Abstract: Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

Abstract: An embodiment of the invention relates to a BCH encoder formed with linear feedback shift registers (LFSRs) to form quotients and products of input polynomials with irreducible polynomials of a generator polynomial g(x) of the BCH encoder, with and without pre-multiplication by a factor xm. The BCH encoder includes multiplexers that couple LFSR inputs and outputs to other LFSRs depending on a data input or parity generation state. The BCH encoder can correct up to a selectable maximum number of errors in the input polynomials. The BCH encoder further includes LFSR output polynomial exponentiation processes to produce partial syndromes for the input data in a syndrome generation state. In the syndrome generation state the LFSRs perform polynomial division without pre-multiplication by the factor xm. The exponentiation processes produce partial syndromes from the resulting remainder polynomials of the input data block.

Abstract: New and useful methods and systems for providing improved performance of a Viterbi device are disclosed. For example, in an embodiment a Viterbi device includes metric circuitry configured to determine branch metrics using at least one of a variance signal based on both received data and detected data of the Viterbi device and a priori probabilities of available state transitions within a trellis of the Viterbi device.

Abstract: A decoder for decoding a set of bits encoded using a Bose-Chaudhuri-Hocquenghem (BCH) error-correcting code (ECC) includes a syndrome generator, a key equation solver, and an error bit locator. The syndrome generator receives the set of encoded bits and generates a set of syndromes. The key equation solver generates an error location polynomial based on the set of syndromes. The error bit locator generates an error match bit using the error location polynomial, and the error match bit is used to identify and correct errors in the set of encoded bits.

Abstract: Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.