Code Based On Generator Polynomial Patents (Class 714/781)
  • Patent number: 11387848
    Abstract: Embodiments of the present disclosure provide a controller hierarchical decoding architecture. For instance, multiple decoder hierarchies are implemented along with use of hierarchies of codes with locality (e.g., larger code length of a hierarchy is composed of local codes from a lower hierarchy). The hierarchical Error Correction Code (ECC) decoding includes multiple hierarchies such as a first hierarchy, a second hierarchy, and additional hierarchies as needed. A first hierarchy includes low-complexity ECC engines, each connected to a NAND channel for computing local codes of low code lengths. A second hierarchy includes higher complexity ECC engines that shares several NAND channels for correcting corrupt data using relatively larger code length (e.g., and the higher complexity ECC engines of the second hierarchy performs decoding operations using more complex decoding algorithms). The larger code length is composed of local codes from a previous hierarchy.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: July 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Amit Berman, Ariel Doubchak
  • Patent number: 11294697
    Abstract: A computing device may include a memory and a processor cooperating with the memory to generate data to correct errors in transmission of packets to a client device based upon a ratio of a first bandwidth in which to transfer content of a buffer and a second bandwidth in which to transfer the generated data, the packets to transfer the content and the generated data to the client device via a channel. The processor may further adjust the ratio based upon a parameter of the channel, and send the content of the buffer and the generated data via packets and through the channel to the client device based on the adjusted ratio.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: April 5, 2022
    Assignee: CITRIX SYSTEMS, INC.
    Inventor: Georgy Momchilov
  • Patent number: 11269561
    Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell
  • Patent number: 11237903
    Abstract: Technologies for provisioning error-corrected data for use in in-memory compute operations include a memory that includes a memory media having multiple memory partitions and media access circuitry coupled to the memory media. The media access circuitry is to receive a request to perform an in-memory compute operation on data from the memory media. The request specifies a memory partition of the memory media in which the data is located. The media access circuitry reads the data from the memory partition. The media access circuitry performs error correction on the read data to produce error-corrected read data and stores the error-corrected read data in a temporary buffer for access by one or more in-memory compute operations, in addition to the requested in-memory compute operation.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Rajesh Sundaram, Wei Wu, Chetan Chauhan, Srikanth Srinivasan, Shigeki Tomishima
  • Patent number: 11233532
    Abstract: There is provided mechanisms for decoding an encoded sequence into a decoded sequence. A method is performed by an information decoder. The method comprises obtaining the encoded sequence. The encoded sequence has been encoded using a polar code. The method comprises successively decoding the encoded sequence into the decoded sequence. The decoding is performed for a given list size, LS, where LS>1, defining how many candidate decoded sequences in total the thus far decoded sequence is allowed to branch into during the decoding. The encoded sequence is decoded, until its first branching, by at least as many processing units in parallel as a factor, f, of the given list size. The factor is at least half the given list size, f?LS/2.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: January 25, 2022
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Mirsad Cirkic, Niclas Wiberg
  • Patent number: 11218174
    Abstract: Provided are methods and systems for storing data using locally repairable multiple encoding. A data storage method may include generating n N×M encoding matrices, each including an M×M first matrix, an 1×M second matrix in which all of elements have a value of 1, and an M×M third matrix that is a symmetric matrix in which respective columns are configured by changing a sequence of elements from an element set; arranging the encoding matrices into a plurality of groups; generating a data block through the first matrix, a local parity block through the second matrix, and a global parity block through the third matrix by encoding source data of a first group with a first encoding matrix among the encoding matrices arranged into the first group; and merging the global parity block with a global parity block of a second encoding matrix that is different than the first encoding matrix.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 4, 2022
    Assignees: Naver Corporation, Industry-University Cooperation Foundation Hanyang University Erica Campus
    Inventors: Chanyoung Park, Jiwoong Won, Junhee Ryu, Kyungtae Kang, Yun-cheol Choo, Sung-Won Jun, Taewoong Kim
  • Patent number: 11218249
    Abstract: For example, a wireless communication device may be configured to determine a count of one or more unreliable data symbols in a received wireless communication packet having a valid Cyclic Redundancy Check (CRC) result; based on the count of the unreliable data symbols, to determine whether to classify the valid CRC result as a false-positive CRC result; and, based on classification of the valid CRC result as a false-positive CRC result, to handle the received wireless communication packet as having a non-valid CRC result.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 4, 2022
    Assignee: INTEL CORPORATION
    Inventors: Yuwei Zhang, Prasanna Desai
  • Patent number: 11190340
    Abstract: A method for creating unified, efficient hardware implementations for multiple symmetric ciphers is described. For a chosen set of two or more distinct types of symmetric ciphers, a unified substitution box (SBOX) is designed that can implement most of the operations in a single hardware block, with small hardware blocks added before and after the unified SBOX for unique operations of each distinct symmetric cipher. Optimization techniques can also be applied to the linear operations and SBOX operations for the chosen set, rather than individually for each symmetric cipher, of the two or more distinct types of symmetric ciphers.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 30, 2021
    Assignee: ARM LIMITED
    Inventors: Leonid Dorrendorf, Ruvein Itskhak Levin, Ury Kreimer
  • Patent number: 11184029
    Abstract: Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Avner Dor, Amit Berman, Ariel Doubchak
  • Patent number: 11171739
    Abstract: Methods, systems, and devices for wireless communications are described. An encoder of a wireless device may receive a transport block (TB) for transmission and segment the transport block into a set of multiple, smaller data segments that respectively In correspond to a plurality of code blocks of the TB. The encoder may generate a code block level (CB-level) error detection code (EDC) for a subset of the data segments. The encoder may generate a transport block-level (TB-level) EDC for the TB using the data segments. Each of the code blocks (CBs) may be of the same size and may include one of the data segments. A subset of the CBs may include a data segment from the subset of the data segments and one of the CB-level EDCs. The remaining CBs that are not part of the subset may include a remaining data segments and the TB-level EDC.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: November 9, 2021
    Assignee: Qualcomm Incorproated
    Inventors: Changlong Xu, Liangming Wu, Jian Li, Kai Chen, Jing Jiang, Gabi Sarkis, Hao Xu
  • Patent number: 11163634
    Abstract: An H matrix generating circuit for generating an H matrix of a QC-LDPC code may include: a conversion value calculation unit calculating conversion values corresponding to column sections of an original H matrix including a plurality of circulant matrices; and a shift unit generating an advanced H matrix by circularly shifting circulant matrices positioned in column sections of the original H matrix by amounts of the conversion values, respectively.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Chol Su Chae, Jang Seob Kim
  • Patent number: 11153334
    Abstract: A method of detecting patterns in network traffic is provided. The method includes receiving packets of network traffic, performing a frequency analysis per field of the packets as a function of frequency of the occurrence of the same data in the corresponding field, and selecting top values which are values associated with each field of the set of fields that satisfy a criterion as having occurred most frequently in the packets as a function of a result of the frequency analysis.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: October 19, 2021
    Assignee: Arbor Networks, Inc.
    Inventors: Steinthor Bjarnason, Andrew Ralph Beard, David Turnbull
  • Patent number: 11146356
    Abstract: According to some embodiments, a method for use in a wireless transmitter of adaptive cyclic redundancy check (CRC) length selection comprises: obtaining a system parameter related to a number of beam sweeps used by the wireless transmitter for transmitting a wireless signal; selecting a CRC length based on the obtained system parameter; selecting a CRC polynomial of the selected length; generating CRC bits from time-dependent or time-independent information bits using the CRC polynomial; concatenating the generated CRC bits with the time-dependent or time-independent information bits; encoding the concatenated bits; and transmitting the encoded bits to a wireless receiver. The system parameter may comprise: a carrier frequency; a number of transmit antenna elements; a number of receive antenna elements; a transmitter antenna azimuth configuration; a transmitter antenna elevation configuration; an antenna polarization type; a beam scanning algorithm; and a cell type.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: October 12, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Dennis Hui, Yufei Blankenship, Anders Wesslén
  • Patent number: 11133895
    Abstract: A method may include: dividing, by a sending device into k code blocks CBs, a TB into which a cyclic redundancy check bit is loaded; then separately performing channel coding on the k CBs, to obtain a bit sequence Sj, where j=1, 2, . . . , and k, and a set S={S1, S2, . . . , Sk}; and mapping, by the sending device, some or all bit sequences in all elements in S to transmission resources in N basic transmission time units, where some or all bit sequences in the Sj are mapped to transmission resources in Mj basic transmission time units, and a last bit in the Sj mapped to an mth basic transmission time unit in the Mj basic transmission time units and a first bit in the Sj mapped to an (m+1)th basic transmission time unit are contiguous in the Sj.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 28, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ruixiang Ma, Yongxia Lyu
  • Patent number: 11086561
    Abstract: An integrated circuit device includes a nonvolatile memory, first and second buffer memories, and a controller. Each of the first and second buffer memories is configured to buffer write data to be written to the nonvolatile memory in response to a write request and also buffer read data received from the nonvolatile memory in response to a read request. A controller is provided, which evaluates the first buffer memory against at least one criterion relating to data accuracy. The controller is configured to: redirect at least some of the write data from the first buffer memory to the second buffer memory in response to the write request when the evaluation demonstrates the criterion has been exceeded, and redirect at least some of the read data from the first buffer memory to the second buffer memory in response to the read request when the evaluation demonstrates the criterion has been exceeded.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: August 10, 2021
    Inventors: Eung-Jun Youn, Bum-Jun Kim
  • Patent number: 11010650
    Abstract: Software tools disclosed herein may allow a user to enter design choices that alter an aesthetic appearance of a machine-readable label such that modules included in the label deviate from a standardized definition for the modules. Such alterations may include changes in size, color and orientation of modules. The alterations may allow a user to create machine-readable labels having unique aesthetic appearances. A software engine may ensure that, despite the aesthetic design choices entered by a user, the generated machine-readable label is reliably scannable.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 18, 2021
    Assignee: The DTX Company
    Inventors: Patrik Andrew Devlin, Corey Benjamin Daugherty, Ahmad Askarian, David Shing, Neil Wayne Cohen, Saul Lewis Stetson, Richard Przekop
  • Patent number: 10986218
    Abstract: A system for broadcasting that includes a watermark payload. The system includes a method for receiving a set of message fragments, receiving a 32 bit Cyclic Redundancy Check for each message fragment, identifying whether a last fragment is more than zero, and receiving the 32 bit Cyclic Redundancy Check included in the last fragment, if the value of the last fragment is more than zero, in which the 32 bit Cyclic Redundancy Check contains a CRC value represented by CRC(x), in which x is obtained by concatenating the message fragments and the 32 bit Cyclic Redundancy Check is sent using an unsigned integer most significant bit first format.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 20, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kiran M. Misra, Sachin G. Deshpande
  • Patent number: 10949302
    Abstract: One embodiment provides a system that facilitates efficient storage and retrieval using erasure coding. During operation, the system determines a finite field solution that conforms to both locality and maximum distance separable (MDS) properties of an erasure-coding system. The system determines a generator matrix of the erasure-coding system based on the finite field solution and generates, from a data element, a plurality of coded fragments based on the generator matrix of the erasure-coding system. The plurality of coded fragments includes a set of enhanced coded fragments that allows reconstruction of the data element and a set of regular coded fragments. The number of the enhanced coded fragments can be fewer than a threshold number of coded fragments for the erasure-coding system.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 16, 2021
    Assignee: PhazrIO Inc.
    Inventors: Chi-Kwan Jim Cheung, Lara Dolecek, Gary N. Jin, Juo-Yu Lee
  • Patent number: 10915667
    Abstract: Systems and methods for protecting from external monitoring attacks cryptographic data processing operations involving universal polynomial hash functions computation.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 9, 2021
    Assignee: Cryptography Research, Inc.
    Inventors: Guilherme Ozari de Almeida, Elena Trichina, Elke De Mulder
  • Patent number: 10883834
    Abstract: Disclosed is a feature for a vehicle that enables taking precautionary actions in response to conditions on the road network around or ahead of the vehicle, in particular, a curved portion of a road with insufficient superelevation. A database that represents the road network is used to determine locations where curved sections of roads have insufficient superelevation (banking), i.e., where the superelevation is below a threshold. Then, precautionary action data is added to the database to indicate a location at which a precautionary action is to be taken about the location of insufficient superelevation. A precautionary action system installed in a vehicle uses this database, or a database derived therefrom, in combination with a positioning system to determine when the vehicle is at a location that corresponds to the location of a precautionary action.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: January 5, 2021
    Assignee: HERE Global B.V.
    Inventor: Robert Denaro
  • Patent number: 10873394
    Abstract: A free-space optical (FSO) retransmission device includes a memory bank partitioned into at least a source buffer indexed by segment identifications (IDs), an interface in communication with an optical terminal and an Ethernet network, and a programmable circuit configured to execute data process operations. The data process operations include receiving data from the Ethernet network, generating an FSO segment including the data received from the Ethernet network and a segment ID, generating and transmitting an outgoing FSO frame to the optical terminal, the outgoing FSO frame including an outgoing FSO segment, and storing the outgoing FSO segment in the source buffer until a corresponding acknowledgement is received in an inbound FSO frame from the optical terminal.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: December 22, 2020
    Assignee: The Johns Hopkins University
    Inventors: James L. Riggins, II, David D. Nicholes, Joseph E. Sluz, Juan C. Juarez
  • Patent number: 10855443
    Abstract: Systems and methods for protecting from external monitoring attacks cryptographic data processing operations involving computation of a universal polynomial hash function, such as GHASH function. An example method may comprise: receiving an input data block, an iteration result value, and a mask value; performing a non-linear operation to produce a masked result value, wherein a first operand of the non-linear operation is represented by a combination of the iteration result value and the input data block, and the second operand of the non-linear operation is represented by a secret hash value, and wherein one of the first operand or the second operand is masked using a mask value; determining, based on the mask value, a mask correction value; and producing a new iteration result value by applying the mask correction value to the masked result value.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 1, 2020
    Assignee: Cryptography Research Inc.
    Inventors: Elena Trichina, Guilherme Ozari de Almeida, Elke De Mulder
  • Patent number: 10824504
    Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James A. O'Connor, Jr., Barry M. Trager, Warren E. Maule, Marc A. Gollub, Brad W. Michael, Patrick J. Meaney
  • Patent number: 10819374
    Abstract: Disclosed apparatus and method improve the computational efficiency of encoding and decoding data having erasures according to a maximum distance separable (MDS) code based on a Reed-Solomon code. Thus, n encoded fragments are formed by multiplying k data fragments by an n×k generator matrix for the MDS code. The code is formed by reducing, in the generator matrix to the extent possible, the size of the finite field to which entries belong—in some cases to the base field having only two elements. In this way, unlike codes known in the art, the generator matrix has more than one column whose entries each take values in the finite field having two elements. In some cases, the generator matrix has a column whose entries each take values in one or more intermediate fields between the finite field having two elements and the encoding field.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: October 27, 2020
    Assignee: AALBORG UNIVERSITET
    Inventors: Diego Ruano, Daniel E. Lucani, Olav Geil
  • Patent number: 10812258
    Abstract: Systems, apparatuses, methods, and computer program products are disclosed for session authentication. An example method includes receiving, by decoding circuitry and over a quantum line, a set of qbits generated based on a first set of quantum bases. The example method further includes decoding, by the decoding circuitry and based on a second set of quantum bases, the set of qbits to generate a decoded set of bits. The example method further includes generating, by session authentication circuitry, a session key based on the decoded set of bits.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 20, 2020
    Assignee: WELLS FARGO BANK, N.A.
    Inventor: Masoud Vakili
  • Patent number: 10812223
    Abstract: Techniques to reduce the transmission overheads in a communication system are disclosed. In an embodiment, a method described herein relates to the elimination of redundant padding to realize an integer number of FEC code-words during the FEC-encoding process of transmission as well as the reduction/elimination of redundant padding to realize an integer number of transmission symbols during the subcarrier modulation mapping process of transmitting OFDM/ACMT/DMT symbols. The techniques are described in the context of a communication system based on the MoCA specification. Furthermore, techniques for channel-profiling, channel-estimation and bandwidth request/grant signaling that facilitate the realization of the method of reduction of transmission overheads in a MoCA system are also described.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 20, 2020
    Assignee: Entropic Communication, LLC
    Inventors: Rahul Malik, Vipin Aggarwal
  • Patent number: 10700813
    Abstract: Various embodiments disclosed herein provide for a transmitter that can adjust the size of an information block or segment the information block based on a forward error correction (FEC) code optimum efficiency. Certain FEC codes are more efficient at encoding and decoding longer information blocks and if an information block is shorter than a predetermined length, the transmitter can pad the information block with a group of null bits to lengthen the information block to increase the performance of encoding and decoding the information block. In some embodiments, the transmitter can segment the information block into a set of segments, and if the last segment is below the predetermined length, the transmitter can pad the last segment.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: June 30, 2020
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Xiaoyi Wang, Arunabha Ghosh
  • Patent number: 10694177
    Abstract: A TDR technique for performing in-service distance-to-fault measurements in cable TV networks is disclosed. Using a cable network tester configured to generate chirped probe pulses and to perform pulse-matched filtering and averaging of received echoes, network faults may be detected without interfering with the downstream reception. The probe pulse transmission may be timed to take advantage of the error correction coding in the network.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 23, 2020
    Assignee: VIAVI SOLUTIONS INC
    Inventors: Kyle Harris, Daniel K. Chappell
  • Patent number: 10627240
    Abstract: Disclosed is a feature for a vehicle that enables taking precautionary actions in response to conditions on the road network around or ahead of the vehicle, in particular, a curved portion of a road where the curvature increases between adjacent curved sections. A database that represents the road network is used to determine locations where curvature between adjacent curved sections increases. Then, precautionary action data is added to the database to indicate a location at which a precautionary action is to be taken about the location where curvature increases. A precautionary action system installed in a vehicle uses this database, or a database derived therefrom, in combination with a positioning system to determine when the vehicle is at a location that corresponds to the location of a precautionary action. When the vehicle is at such a location, a precautionary action is taken by a vehicle system as the vehicle is approaching a location where the curvature increases.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: April 21, 2020
    Assignee: HERE Global B.V.
    Inventor: Robert Denaro
  • Patent number: 10630424
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; and when the reception error is occurred, disabling the descrambler of the lowest layer and issuing a first request to the second side for directing the second side to disable a scrambler, thereby disabling the second side to protect second data to be transmitted to the first side by using a data scrambling technique.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Fu-Jen Shih
  • Patent number: 10630425
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; sending a NAC (negative acknowledgement control) frame to the second side to inform the second side that the reception error is occurred for the first data each time the reception error is determined for the first descrambled data; and when a total number of occurrences of the reception errors reaches a predefined threshold, disabling the descrambler of the lowest layer.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Yu-Da Chen
  • Patent number: 10581465
    Abstract: An apparatus for constituent code processing in polar successive cancellation list (SCL) decoding and a method thereof. The apparatus includes a processor configured to determine an activation value I and a number r of the candidate paths, where I is a binary value and r is an integer, (I, r)=ƒ(R, k, m), ƒ is a function, R is a number indicating node reliability, k is an integer indicating a number of information nodes, and m is an integer indicating a number of leaf nodes; determine min1, min2, . . . , minq, wherein q is a number of least reliable bits; determine r candidate paths; determine path metrics PMtj of a codeword j for each candidate path t; and select r most probable paths based on PMtj.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hsien-Ping Lin, Jung Hyun Bae
  • Patent number: 10546640
    Abstract: A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string; performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units; inputting the block information to an error checking and correcting (ECC) circuit of the memory storage device to generate a second string; and storing the second string into the rewritable non-volatile memory module.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 28, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Tsung-Lin Wu, Te-Chang Tsui, Chien-Fu Lee
  • Patent number: 10439654
    Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data components via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 8, 2019
    Assignee: Primos Storage Technology, LLC
    Inventor: Robert E. Cousins
  • Patent number: 10404283
    Abstract: A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 3, 2019
    Assignee: Silicon Motion Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10379938
    Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Steven R. King, Frank L. Berry, Michael E. Kounavis
  • Patent number: 10382069
    Abstract: A method for data encoding includes receiving a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H. An intermediate vector s is produced by multiplying the data vector by a data sub-matrix Hs of the parity-check matrix H. A parity part of the code word is derived by applying a sequence of operations to the intermediate vector s based on a decomposition of a parity sub-matrix Hp of the matrix H using matrices A, C, U and V, in which decomposition A is a block triangular matrix that has the same size as Hp, C is matrix that is smaller than Hp, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation Hp=A+UCV.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 13, 2019
    Assignee: APPLE INC.
    Inventors: Moti Teitel, Tomer Ish-Shalom, Yonathan Tate
  • Patent number: 10374759
    Abstract: A high throughput communication apparatus which provides low frame error rates (FER). Error checking encoder and decoders which each comprise a plurality of short blocklength error checking encoders or decoders, respectively, in parallel, coupled through common incremental redundancy. Short-blocklength codes are utilized to achieve communication capacity with incremental redundancy. The system can transmit and decode a large number of short-blocklength codewords in parallel, while it delivers incremental redundancy, without feedback, only to the decoders that need incremental redundancy.
    Type: Grant
    Filed: May 13, 2018
    Date of Patent: August 6, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Richard Wesel, Kasra Vakilinia, Sudarsan V S Ranganathan, Dariush Divsalar, Haobo Wang
  • Patent number: 10360098
    Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson, Robert J. Safranek
  • Patent number: 10314027
    Abstract: A method for transmitting a downlink message on a downlink between an access network and a plurality of terminals. The downlink message includes main data to be transmitted to a receiving terminal. Error detection data is generated from the main data. Main data and/or error-detection data are modified on the basis of an identifier of the receiving terminal, using a predefined reversible modification function. The modification is performed at a constant spectral width and for a constant duration with respect to the aforementioned main data and/or error-detection data. A downlink message including the main data and the error-detection data obtained after modification are transmitted. Also, a method for receiving the downlink messages.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 4, 2019
    Assignee: SIGFOX
    Inventor: Lionel Zirphile
  • Patent number: 10268374
    Abstract: Systems and method for accessing data in a storage network include a processing module receives redundant array of independent disks (RAID) data to store determining which memories to utilize (e.g., a RAID memory, local and/or remote dispersed storage network (DSN) memory) based on one or more of the metadata, the RAID data, a vault lookup, a command, a message, a performance indicator, a predetermination, local DSN memory capabilities, remote DSN memory capabilities, RAID memory capabilities, and a comparison of requirements to capabilities of the RAID memory and local and/or DSN memory. The processing module saves the determination choice in a memory indicator that is stored in one or more of the RAID memory, the local DSN memory, the remote DSN memory, and a DSN user vault.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gary W. Grube, Jason K. Resch
  • Patent number: 10243588
    Abstract: An error correction code (ECC) decoder includes a finite state machine (FSM) controller and a shared logic circuit. The FSM controller generates a first control signal and a second control signal each corresponding to a certain state. The shared logic circuit includes a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation and an error correction operation, in response to the first and second control signals.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: March 26, 2019
    Assignee: SK hynix Inc.
    Inventor: Soojin Kim
  • Patent number: 10218494
    Abstract: In a general aspect, a cryptography process performs modular operations, where the modulus is a non-Mersenne prime. In some aspects, an integer is obtained during execution of a cryptography protocol defined by a cryptosystem. A prime modulus is defined by the cryptosystem in terms of a set of constants. The set of constants includes at least a first constant and a second, distinct constant. A set of block coefficients is computed to represent the integer in a block form. The plurality of block coefficients includes a first block coefficient obtained by a first modular reduction modulo the first constant, and a second block coefficient obtained by a second modular reduction modulo the second constant. A reduced representation of the integer is computed based on the plurality of block coefficients, such that the reduced representation is less than the prime modulus.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 26, 2019
    Assignee: ISARA Corporation
    Inventors: Victoria de Quehen, Shane Daniel Kelly
  • Patent number: 10164660
    Abstract: An integrated circuit may include a Reed-Solomon decoder that receives a transmitted code word and an associated bit mask and that generates a corresponding corrected message. The bit mask indicates an erasure pattern for the received code word. The Reed-Solomon decoder may include a syndrome generator, a multiplication circuit, a read-only memory (ROM) circuit, an address compressor, and an aggregation circuit. The syndrome generator may receive the transmitted code word and generate a corresponding syndrome. The address compressor may receive the bit mask and generate a corresponding unique address for accessing the ROM circuit. The ROM circuit may then output an inverse parity matrix based on the unique address. The multiplication circuit may multiply the syndrome by the retrieved inverse parity matrix to output corrected symbols. The aggregation circuit may then path the received code word with the corrected symbols to obtain the corrected message.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Simon Finn, Martin Langhammer, Sami Mumtaz
  • Patent number: 10073735
    Abstract: Systems and methods are disclosed for a seeding mechanism for error detection codes. An error detection code may be generated using specifically modified seed input and stored to data sectors not containing valid data. A data storage device may determine if read attempts are directed to an invalid sector by analysis of the stored error detection code. In some embodiments, an apparatus may determine a first error detection code stored to a target data storage sector does not match a second error detection code calculated for the target data storage sector, compare the first error detection code to a modified error code value to determine whether the target data storage sector contains valid data, and return an indication that the target data storage sector does not contain valid data when the error detection code matches the modified error code value.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: September 11, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jun Cai, Jeetandra Kella, ChuanPeng Ong, Brian T Edgar
  • Patent number: 10033484
    Abstract: Techniques to reduce the transmission overheads in a communication system are disclosed. In an embodiment, a method described herein relates to the elimination of redundant padding to realize an integer number of FEC code-words during the FEC-encoding process of transmission as well as the reduction/elimination of redundant padding to realize an integer number of transmission symbols during the subcarrier modulation mapping process of transmitting OFDM/ACMT/DMT symbols. The techniques are described in the context of a communication system based on the MoCA specification. Furthermore, techniques for channel-profiling, channel-estimation and bandwidth request/grant signaling that facilitate the realization of the method of reduction of transmission overheads in a MoCA system are also described.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 24, 2018
    Assignee: Entropic Communications, LLC
    Inventors: Rahul Malik, Vipin Aggarwal
  • Patent number: 9934841
    Abstract: A memory refreshing circuit implemented on an integrated circuit comprising a memory circuit that stores original data and an algorithmic data generation circuit that generates write addresses and correct data such that the correct data is stored in the memory circuit at locations that are indicated by the write addresses to correct errors in the original data by overwriting the original data with the correct data during a random access mode of operation of the memory circuit.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 3, 2018
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Sami Mumtaz
  • Patent number: 9852809
    Abstract: Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. The control circuit further provides the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and suppresses providing the error signal when the number of bit errors detected is less than the predetermined number.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 26, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Toru Ishikawa
  • Patent number: 9722636
    Abstract: An arrangement for decoding a data word using a Reed-Muller code, has: (1) N input terminals, (2) a first level of E>>D summing modules, each summing module being linked with F different input terminals and each input terminal being linked with E summing modules, (3) a first level of E decision modules, each of the D inputs of each decision module being linked respectively with an output from D different summing modules, (4) a second level of H summing modules, (5) a second level of G decision modules, (6) a third level of G summing modules, and (7) G output terminals. N signifies the code length and D signifies the minimum spacing of the code, E is equal to D-2, F is equal to N/D, G is the number of symbols of the data word that need to be corrected and is a natural number between 1 and E<<D.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: August 1, 2017
    Assignee: Eberhard Karls Universitaet Tuebingen
    Inventors: Juliane Bertram, Michael Huber, Peter Hauck
  • Patent number: 9716606
    Abstract: In a WLAN, a device generates a short training field and a long training field following the short training field. The device generates a first signal field following the long training field, and the first signal field includes a mode field for indicating a transmission mode of a frame to be transmitted and a check bit for protecting at least the mode field. The device transmits the frame including the short training field, the long training field, and the first signal field.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 25, 2017
    Assignee: NEWRACOM, INC.
    Inventors: Ilgu Lee, Jeongchul Shin, Kyeongpyo Kim, Jongee Oh, Dae Kyun Lee