Abstract: Aspects of the disclosure are directed to a cross-lane processing unit (XPU) for performing data-dependent operations across multiple data processing lanes of a processor. Rather than implementing operation-specific circuits for each data-dependent operation, the XPU can be configured to perform different operations in response to input signals configuring individual operations performed by processing cells and crossbars arranged as a stacked network in the XPU. Each processing cell can receive and process data across multiple data processing lanes. Aspects of the disclosure include configuring the XPU to use a vector sort network to perform a duplicate count eliminating the need to configure the XPU separately for sorting and duplicate counting.

Abstract: A data processing method and apparatus. The data process method includes: determining, by a transmitting node, a code block length N0 for encoding an information bit sequence to be transmitted according to a data characteristic for representing the information bit sequence to be transmitted and a preset parameter corresponding to the data characteristic; performing, by the transmitting node, polar encoding on the information bit sequence to be transmitted according to the code block length N0; and transmitting, by the transmitting node, a code block obtained through the polar encoding to a receiving node.

Abstract: Methods and apparatus for constructing polar codes are provided. A transmitter determines at least one set of parameters corresponding to data to be transmitted, and a set of sorting indices corresponding to bits of the data to be transmitted based on the set of parameters, the set of sorting indices indicating a position set of the bits to be transmitted. The transmitter polar encodes the data based at least on the set of parameters and the set of sorting indices to generate a coded block of the data, and transmits the coded block of the data.

Abstract: The present disclosure relates to a system and a method for data protection. In some embodiments, an exemplary method for data encoding includes: receiving a data bulk; performing an erasure coding (EC) encoding on the data bulk to generate one or more EC codewords; distributing a plurality of portions of each EC codeword of the one or more EC codewords across a plurality of solid-state drives (SSDs); performing, at each SSD of the plurality of SSDs, an error correction coding (ECC) encoding on portions of the one or more EC codewords distributed to the SSD to generate an ECC codeword; and storing, in each SSD of the plurality of SSDs, the ECC codeword.

Abstract: An apparatus may be configured to receive a polar-encoded transmission comprising at least one intermediate node associated with a first configuration of frozen leaf nodes and information leaf nodes. The apparatus may further be configured to apply an FHT to a first set of values associated with a first intermediate node of the at least one intermediate node to generate a second set of values associated with the first intermediate node. The apparatus may also be configured to select, based on the second set of values, one or more paths associated with the first intermediate node for a SSCL decoding. The apparatus may further be configured to calculate a path metric for each of the selected one or more paths associated with the first intermediate node.

Abstract: Methods are proposed herein to perform rate matching for polar codes via circular buffering of the polar encoded bits. Embodiments are directed to methods of operation of a transmitting node in a wireless system including performing polar encoding of a set of information bits in accordance with a polar sequence of length NB to thereby generate NB coded bits. The method can further include interleaving the coded bits to thereby provide an interleaved coded bit sequence, and storing the interleaved coded bit sequence into a circular buffer of length NB. According to certain embodiments, the method can further include extracting N coded bits for transmission from the circular buffer. N can be greater than, equal to, or less than NB.

Abstract: A method and a system for correcting cyclic redundancy check (CRC) for a frame with last bytes changed are provided. The method includes acquiring a data frame, calculating a CRC of a modified data frame, and determining a corrected CRC for the data frame based on at least the CRC of the modified data frame and a CRC correction field calculated on the bytes to be replaced at the end of the frame. An altered data frame includes the data frame with a number of last bytes of the data frame replaced with new bytes.

Abstract: Various embodiments relate to a method for securely comparing a first polynomial represented by a plurality of arithmetic shares and a second compressed polynomial represented by a bitstring where the bits in the bitstring correspond to coefficients of the second polynomial, including: performing a first masked shift of the shares of the coefficients of the first polynomial based upon the start of the interval corresponding to the compressed coefficient of the second polynomial and a modulus value; performing a second masked shift of the shares of the coefficients of the first polynomial based upon the end of the interval corresponding to the compressed coefficient of the second polynomial; bitslicing the most significant bit of the first masked shift of the shares coefficients of the first polynomial; bitslicing the most significant bit of the second masked shift of the shares coefficients of the first polynomial; and combining the first bitsliced bits and the second bitsliced bits using an AND function to p

Abstract: A circuit for generating an N-bit cyclic redundancy code of a k-bit digit d, the code based on a reconfigurable generator polynomial P of degree N, the circuit including a dynamic table comprising a multiplication sub-table storing products resulting from multiplication by the polynomial P of each element definable over k bits, in the order of the scalar values of the k-bit elements; a division sub-table storing quotients resulting from Euclidean division by the polynomial P of each k-bit element shifted by N bits to the left, in the order of the scalar values of the k-bit elements; and a group of first multiplexers, each multiplexer connected to be indexed by a respective cell of the division table to transmit the contents of a corresponding cell of the multiplication table to an output of the dynamic table, of same rank as the respective cell of the division table.

Abstract: Aspects of the present disclosure provide techniques for physical broadcast channel (PBCH) and master information block (MIB) design. An example method is provided for operations which may be performed by a user equipment (UE). The example method generally comprises receiving, a first number of symbols within a first subframe on a physical channel, performing a first blind decode on the first number of symbols to obtain a first set of bits, performing one or more cyclic shifts on the first set of bits, calculating a redundancy check value for the first set of bits, and decoding an information block based on the whether the redundancy check value passes. Aspects of the present disclosure provide techniques for transmission configurations. An example method is provided for operations which may be performed by a base station (BS).

Abstract: The present technology includes an electronic device and a method of operating the same using an artificial neural network. The electronic device according to the present technology includes a decoding controller inputting a primary syndrome vector generated based on a read vector and a parity check matrix to a trained artificial neural, and selecting any one of a first error correction decoding algorithm and a second error correction decoding algorithm based on an output of the trained artificial neural network corresponding to the input, and an error correction decoder performing error correction decoding on a read vector using the selected error correction decoding algorithm. The output of the trained artificial neural network includes a first predicted value indicating a probability that a first error correction decoding using the first error correction decoding algorithm is successful.

Abstract: Embodiments of the present disclosure provide a controller hierarchical decoding architecture. For instance, multiple decoder hierarchies are implemented along with use of hierarchies of codes with locality (e.g., larger code length of a hierarchy is composed of local codes from a lower hierarchy). The hierarchical Error Correction Code (ECC) decoding includes multiple hierarchies such as a first hierarchy, a second hierarchy, and additional hierarchies as needed. A first hierarchy includes low-complexity ECC engines, each connected to a NAND channel for computing local codes of low code lengths. A second hierarchy includes higher complexity ECC engines that shares several NAND channels for correcting corrupt data using relatively larger code length (e.g., and the higher complexity ECC engines of the second hierarchy performs decoding operations using more complex decoding algorithms). The larger code length is composed of local codes from a previous hierarchy.

Abstract: A computing device may include a memory and a processor cooperating with the memory to generate data to correct errors in transmission of packets to a client device based upon a ratio of a first bandwidth in which to transfer content of a buffer and a second bandwidth in which to transfer the generated data, the packets to transfer the content and the generated data to the client device via a channel. The processor may further adjust the ratio based upon a parameter of the channel, and send the content of the buffer and the generated data via packets and through the channel to the client device based on the adjusted ratio.

Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.

Abstract: Technologies for provisioning error-corrected data for use in in-memory compute operations include a memory that includes a memory media having multiple memory partitions and media access circuitry coupled to the memory media. The media access circuitry is to receive a request to perform an in-memory compute operation on data from the memory media. The request specifies a memory partition of the memory media in which the data is located. The media access circuitry reads the data from the memory partition. The media access circuitry performs error correction on the read data to produce error-corrected read data and stores the error-corrected read data in a temporary buffer for access by one or more in-memory compute operations, in addition to the requested in-memory compute operation.

Abstract: There is provided mechanisms for decoding an encoded sequence into a decoded sequence. A method is performed by an information decoder. The method comprises obtaining the encoded sequence. The encoded sequence has been encoded using a polar code. The method comprises successively decoding the encoded sequence into the decoded sequence. The decoding is performed for a given list size, LS, where LS>1, defining how many candidate decoded sequences in total the thus far decoded sequence is allowed to branch into during the decoding. The encoded sequence is decoded, until its first branching, by at least as many processing units in parallel as a factor, f, of the given list size. The factor is at least half the given list size, f?LS/2.

Abstract: Provided are methods and systems for storing data using locally repairable multiple encoding. A data storage method may include generating n N×M encoding matrices, each including an M×M first matrix, an 1×M second matrix in which all of elements have a value of 1, and an M×M third matrix that is a symmetric matrix in which respective columns are configured by changing a sequence of elements from an element set; arranging the encoding matrices into a plurality of groups; generating a data block through the first matrix, a local parity block through the second matrix, and a global parity block through the third matrix by encoding source data of a first group with a first encoding matrix among the encoding matrices arranged into the first group; and merging the global parity block with a global parity block of a second encoding matrix that is different than the first encoding matrix.

Abstract: For example, a wireless communication device may be configured to determine a count of one or more unreliable data symbols in a received wireless communication packet having a valid Cyclic Redundancy Check (CRC) result; based on the count of the unreliable data symbols, to determine whether to classify the valid CRC result as a false-positive CRC result; and, based on classification of the valid CRC result as a false-positive CRC result, to handle the received wireless communication packet as having a non-valid CRC result.

Abstract: A method for creating unified, efficient hardware implementations for multiple symmetric ciphers is described. For a chosen set of two or more distinct types of symmetric ciphers, a unified substitution box (SBOX) is designed that can implement most of the operations in a single hardware block, with small hardware blocks added before and after the unified SBOX for unique operations of each distinct symmetric cipher. Optimization techniques can also be applied to the linear operations and SBOX operations for the chosen set, rather than individually for each symmetric cipher, of the two or more distinct types of symmetric ciphers.

Abstract: Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.

Abstract: Methods, systems, and devices for wireless communications are described. An encoder of a wireless device may receive a transport block (TB) for transmission and segment the transport block into a set of multiple, smaller data segments that respectively In correspond to a plurality of code blocks of the TB. The encoder may generate a code block level (CB-level) error detection code (EDC) for a subset of the data segments. The encoder may generate a transport block-level (TB-level) EDC for the TB using the data segments. Each of the code blocks (CBs) may be of the same size and may include one of the data segments. A subset of the CBs may include a data segment from the subset of the data segments and one of the CB-level EDCs. The remaining CBs that are not part of the subset may include a remaining data segments and the TB-level EDC.

Abstract: An H matrix generating circuit for generating an H matrix of a QC-LDPC code may include: a conversion value calculation unit calculating conversion values corresponding to column sections of an original H matrix including a plurality of circulant matrices; and a shift unit generating an advanced H matrix by circularly shifting circulant matrices positioned in column sections of the original H matrix by amounts of the conversion values, respectively.

Abstract: A method of detecting patterns in network traffic is provided. The method includes receiving packets of network traffic, performing a frequency analysis per field of the packets as a function of frequency of the occurrence of the same data in the corresponding field, and selecting top values which are values associated with each field of the set of fields that satisfy a criterion as having occurred most frequently in the packets as a function of a result of the frequency analysis.

Abstract: According to some embodiments, a method for use in a wireless transmitter of adaptive cyclic redundancy check (CRC) length selection comprises: obtaining a system parameter related to a number of beam sweeps used by the wireless transmitter for transmitting a wireless signal; selecting a CRC length based on the obtained system parameter; selecting a CRC polynomial of the selected length; generating CRC bits from time-dependent or time-independent information bits using the CRC polynomial; concatenating the generated CRC bits with the time-dependent or time-independent information bits; encoding the concatenated bits; and transmitting the encoded bits to a wireless receiver. The system parameter may comprise: a carrier frequency; a number of transmit antenna elements; a number of receive antenna elements; a transmitter antenna azimuth configuration; a transmitter antenna elevation configuration; an antenna polarization type; a beam scanning algorithm; and a cell type.

Abstract: A method may include: dividing, by a sending device into k code blocks CBs, a TB into which a cyclic redundancy check bit is loaded; then separately performing channel coding on the k CBs, to obtain a bit sequence Sj, where j=1, 2, . . . , and k, and a set S={S1, S2, . . . , Sk}; and mapping, by the sending device, some or all bit sequences in all elements in S to transmission resources in N basic transmission time units, where some or all bit sequences in the Sj are mapped to transmission resources in Mj basic transmission time units, and a last bit in the Sj mapped to an mth basic transmission time unit in the Mj basic transmission time units and a first bit in the Sj mapped to an (m+1)th basic transmission time unit are contiguous in the Sj.

Abstract: An integrated circuit device includes a nonvolatile memory, first and second buffer memories, and a controller. Each of the first and second buffer memories is configured to buffer write data to be written to the nonvolatile memory in response to a write request and also buffer read data received from the nonvolatile memory in response to a read request. A controller is provided, which evaluates the first buffer memory against at least one criterion relating to data accuracy. The controller is configured to: redirect at least some of the write data from the first buffer memory to the second buffer memory in response to the write request when the evaluation demonstrates the criterion has been exceeded, and redirect at least some of the read data from the first buffer memory to the second buffer memory in response to the read request when the evaluation demonstrates the criterion has been exceeded.

Abstract: Software tools disclosed herein may allow a user to enter design choices that alter an aesthetic appearance of a machine-readable label such that modules included in the label deviate from a standardized definition for the modules. Such alterations may include changes in size, color and orientation of modules. The alterations may allow a user to create machine-readable labels having unique aesthetic appearances. A software engine may ensure that, despite the aesthetic design choices entered by a user, the generated machine-readable label is reliably scannable.

Abstract: A system for broadcasting that includes a watermark payload. The system includes a method for receiving a set of message fragments, receiving a 32 bit Cyclic Redundancy Check for each message fragment, identifying whether a last fragment is more than zero, and receiving the 32 bit Cyclic Redundancy Check included in the last fragment, if the value of the last fragment is more than zero, in which the 32 bit Cyclic Redundancy Check contains a CRC value represented by CRC(x), in which x is obtained by concatenating the message fragments and the 32 bit Cyclic Redundancy Check is sent using an unsigned integer most significant bit first format.

Abstract: One embodiment provides a system that facilitates efficient storage and retrieval using erasure coding. During operation, the system determines a finite field solution that conforms to both locality and maximum distance separable (MDS) properties of an erasure-coding system. The system determines a generator matrix of the erasure-coding system based on the finite field solution and generates, from a data element, a plurality of coded fragments based on the generator matrix of the erasure-coding system. The plurality of coded fragments includes a set of enhanced coded fragments that allows reconstruction of the data element and a set of regular coded fragments. The number of the enhanced coded fragments can be fewer than a threshold number of coded fragments for the erasure-coding system.

Abstract: Systems and methods for protecting from external monitoring attacks cryptographic data processing operations involving universal polynomial hash functions computation.

Abstract: Disclosed is a feature for a vehicle that enables taking precautionary actions in response to conditions on the road network around or ahead of the vehicle, in particular, a curved portion of a road with insufficient superelevation. A database that represents the road network is used to determine locations where curved sections of roads have insufficient superelevation (banking), i.e., where the superelevation is below a threshold. Then, precautionary action data is added to the database to indicate a location at which a precautionary action is to be taken about the location of insufficient superelevation. A precautionary action system installed in a vehicle uses this database, or a database derived therefrom, in combination with a positioning system to determine when the vehicle is at a location that corresponds to the location of a precautionary action.

Abstract: A free-space optical (FSO) retransmission device includes a memory bank partitioned into at least a source buffer indexed by segment identifications (IDs), an interface in communication with an optical terminal and an Ethernet network, and a programmable circuit configured to execute data process operations. The data process operations include receiving data from the Ethernet network, generating an FSO segment including the data received from the Ethernet network and a segment ID, generating and transmitting an outgoing FSO frame to the optical terminal, the outgoing FSO frame including an outgoing FSO segment, and storing the outgoing FSO segment in the source buffer until a corresponding acknowledgement is received in an inbound FSO frame from the optical terminal.

Abstract: Systems and methods for protecting from external monitoring attacks cryptographic data processing operations involving computation of a universal polynomial hash function, such as GHASH function. An example method may comprise: receiving an input data block, an iteration result value, and a mask value; performing a non-linear operation to produce a masked result value, wherein a first operand of the non-linear operation is represented by a combination of the iteration result value and the input data block, and the second operand of the non-linear operation is represented by a secret hash value, and wherein one of the first operand or the second operand is masked using a mask value; determining, based on the mask value, a mask correction value; and producing a new iteration result value by applying the mask correction value to the masked result value.

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.

Abstract: Disclosed apparatus and method improve the computational efficiency of encoding and decoding data having erasures according to a maximum distance separable (MDS) code based on a Reed-Solomon code. Thus, n encoded fragments are formed by multiplying k data fragments by an n×k generator matrix for the MDS code. The code is formed by reducing, in the generator matrix to the extent possible, the size of the finite field to which entries belong—in some cases to the base field having only two elements. In this way, unlike codes known in the art, the generator matrix has more than one column whose entries each take values in the finite field having two elements. In some cases, the generator matrix has a column whose entries each take values in one or more intermediate fields between the finite field having two elements and the encoding field.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for session authentication. An example method includes receiving, by decoding circuitry and over a quantum line, a set of qbits generated based on a first set of quantum bases. The example method further includes decoding, by the decoding circuitry and based on a second set of quantum bases, the set of qbits to generate a decoded set of bits. The example method further includes generating, by session authentication circuitry, a session key based on the decoded set of bits.

Abstract: Techniques to reduce the transmission overheads in a communication system are disclosed. In an embodiment, a method described herein relates to the elimination of redundant padding to realize an integer number of FEC code-words during the FEC-encoding process of transmission as well as the reduction/elimination of redundant padding to realize an integer number of transmission symbols during the subcarrier modulation mapping process of transmitting OFDM/ACMT/DMT symbols. The techniques are described in the context of a communication system based on the MoCA specification. Furthermore, techniques for channel-profiling, channel-estimation and bandwidth request/grant signaling that facilitate the realization of the method of reduction of transmission overheads in a MoCA system are also described.

Abstract: Various embodiments disclosed herein provide for a transmitter that can adjust the size of an information block or segment the information block based on a forward error correction (FEC) code optimum efficiency. Certain FEC codes are more efficient at encoding and decoding longer information blocks and if an information block is shorter than a predetermined length, the transmitter can pad the information block with a group of null bits to lengthen the information block to increase the performance of encoding and decoding the information block. In some embodiments, the transmitter can segment the information block into a set of segments, and if the last segment is below the predetermined length, the transmitter can pad the last segment.

Abstract: A TDR technique for performing in-service distance-to-fault measurements in cable TV networks is disclosed. Using a cable network tester configured to generate chirped probe pulses and to perform pulse-matched filtering and averaging of received echoes, network faults may be detected without interfering with the downstream reception. The probe pulse transmission may be timed to take advantage of the error correction coding in the network.

Abstract: Disclosed is a feature for a vehicle that enables taking precautionary actions in response to conditions on the road network around or ahead of the vehicle, in particular, a curved portion of a road where the curvature increases between adjacent curved sections. A database that represents the road network is used to determine locations where curvature between adjacent curved sections increases. Then, precautionary action data is added to the database to indicate a location at which a precautionary action is to be taken about the location where curvature increases. A precautionary action system installed in a vehicle uses this database, or a database derived therefrom, in combination with a positioning system to determine when the vehicle is at a location that corresponds to the location of a precautionary action. When the vehicle is at such a location, a precautionary action is taken by a vehicle system as the vehicle is approaching a location where the curvature increases.

Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; sending a NAC (negative acknowledgement control) frame to the second side to inform the second side that the reception error is occurred for the first data each time the reception error is determined for the first descrambled data; and when a total number of occurrences of the reception errors reaches a predefined threshold, disabling the descrambler of the lowest layer.

Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; and when the reception error is occurred, disabling the descrambler of the lowest layer and issuing a first request to the second side for directing the second side to disable a scrambler, thereby disabling the second side to protect second data to be transmitted to the first side by using a data scrambling technique.

Abstract: An apparatus for constituent code processing in polar successive cancellation list (SCL) decoding and a method thereof. The apparatus includes a processor configured to determine an activation value I and a number r of the candidate paths, where I is a binary value and r is an integer, (I, r)=ƒ(R, k, m), ƒ is a function, R is a number indicating node reliability, k is an integer indicating a number of information nodes, and m is an integer indicating a number of leaf nodes; determine min1, min2, . . . , minq, wherein q is a number of least reliable bits; determine r candidate paths; determine path metrics PMtj of a codeword j for each candidate path t; and select r most probable paths based on PMtj.

Abstract: A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string; performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units; inputting the block information to an error checking and correcting (ECC) circuit of the memory storage device to generate a second string; and storing the second string into the rewritable non-volatile memory module.

Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data components via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams.

Abstract: A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: A method for data encoding includes receiving a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H. An intermediate vector s is produced by multiplying the data vector by a data sub-matrix Hs of the parity-check matrix H. A parity part of the code word is derived by applying a sequence of operations to the intermediate vector s based on a decomposition of a parity sub-matrix Hp of the matrix H using matrices A, C, U and V, in which decomposition A is a block triangular matrix that has the same size as Hp, C is matrix that is smaller than Hp, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation Hp=A+UCV.

Abstract: A high throughput communication apparatus which provides low frame error rates (FER). Error checking encoder and decoders which each comprise a plurality of short blocklength error checking encoders or decoders, respectively, in parallel, coupled through common incremental redundancy. Short-blocklength codes are utilized to achieve communication capacity with incremental redundancy. The system can transmit and decode a large number of short-blocklength codewords in parallel, while it delivers incremental redundancy, without feedback, only to the decoders that need incremental redundancy.

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.