Code Based On Generator Polynomial Patents (Class 714/781)
  • Patent number: 10986218
    Abstract: A system for broadcasting that includes a watermark payload. The system includes a method for receiving a set of message fragments, receiving a 32 bit Cyclic Redundancy Check for each message fragment, identifying whether a last fragment is more than zero, and receiving the 32 bit Cyclic Redundancy Check included in the last fragment, if the value of the last fragment is more than zero, in which the 32 bit Cyclic Redundancy Check contains a CRC value represented by CRC(x), in which x is obtained by concatenating the message fragments and the 32 bit Cyclic Redundancy Check is sent using an unsigned integer most significant bit first format.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 20, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kiran M. Misra, Sachin G. Deshpande
  • Patent number: 10949302
    Abstract: One embodiment provides a system that facilitates efficient storage and retrieval using erasure coding. During operation, the system determines a finite field solution that conforms to both locality and maximum distance separable (MDS) properties of an erasure-coding system. The system determines a generator matrix of the erasure-coding system based on the finite field solution and generates, from a data element, a plurality of coded fragments based on the generator matrix of the erasure-coding system. The plurality of coded fragments includes a set of enhanced coded fragments that allows reconstruction of the data element and a set of regular coded fragments. The number of the enhanced coded fragments can be fewer than a threshold number of coded fragments for the erasure-coding system.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 16, 2021
    Assignee: PhazrIO Inc.
    Inventors: Chi-Kwan Jim Cheung, Lara Dolecek, Gary N. Jin, Juo-Yu Lee
  • Patent number: 10915667
    Abstract: Systems and methods for protecting from external monitoring attacks cryptographic data processing operations involving universal polynomial hash functions computation.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 9, 2021
    Assignee: Cryptography Research, Inc.
    Inventors: Guilherme Ozari de Almeida, Elena Trichina, Elke De Mulder
  • Patent number: 10883834
    Abstract: Disclosed is a feature for a vehicle that enables taking precautionary actions in response to conditions on the road network around or ahead of the vehicle, in particular, a curved portion of a road with insufficient superelevation. A database that represents the road network is used to determine locations where curved sections of roads have insufficient superelevation (banking), i.e., where the superelevation is below a threshold. Then, precautionary action data is added to the database to indicate a location at which a precautionary action is to be taken about the location of insufficient superelevation. A precautionary action system installed in a vehicle uses this database, or a database derived therefrom, in combination with a positioning system to determine when the vehicle is at a location that corresponds to the location of a precautionary action.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: January 5, 2021
    Assignee: HERE Global B.V.
    Inventor: Robert Denaro
  • Patent number: 10873394
    Abstract: A free-space optical (FSO) retransmission device includes a memory bank partitioned into at least a source buffer indexed by segment identifications (IDs), an interface in communication with an optical terminal and an Ethernet network, and a programmable circuit configured to execute data process operations. The data process operations include receiving data from the Ethernet network, generating an FSO segment including the data received from the Ethernet network and a segment ID, generating and transmitting an outgoing FSO frame to the optical terminal, the outgoing FSO frame including an outgoing FSO segment, and storing the outgoing FSO segment in the source buffer until a corresponding acknowledgement is received in an inbound FSO frame from the optical terminal.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: December 22, 2020
    Assignee: The Johns Hopkins University
    Inventors: James L. Riggins, II, David D. Nicholes, Joseph E. Sluz, Juan C. Juarez
  • Patent number: 10855443
    Abstract: Systems and methods for protecting from external monitoring attacks cryptographic data processing operations involving computation of a universal polynomial hash function, such as GHASH function. An example method may comprise: receiving an input data block, an iteration result value, and a mask value; performing a non-linear operation to produce a masked result value, wherein a first operand of the non-linear operation is represented by a combination of the iteration result value and the input data block, and the second operand of the non-linear operation is represented by a secret hash value, and wherein one of the first operand or the second operand is masked using a mask value; determining, based on the mask value, a mask correction value; and producing a new iteration result value by applying the mask correction value to the masked result value.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 1, 2020
    Assignee: Cryptography Research Inc.
    Inventors: Elena Trichina, Guilherme Ozari de Almeida, Elke De Mulder
  • Patent number: 10824504
    Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James A. O'Connor, Jr., Barry M. Trager, Warren E. Maule, Marc A. Gollub, Brad W. Michael, Patrick J. Meaney
  • Patent number: 10819374
    Abstract: Disclosed apparatus and method improve the computational efficiency of encoding and decoding data having erasures according to a maximum distance separable (MDS) code based on a Reed-Solomon code. Thus, n encoded fragments are formed by multiplying k data fragments by an n×k generator matrix for the MDS code. The code is formed by reducing, in the generator matrix to the extent possible, the size of the finite field to which entries belong—in some cases to the base field having only two elements. In this way, unlike codes known in the art, the generator matrix has more than one column whose entries each take values in the finite field having two elements. In some cases, the generator matrix has a column whose entries each take values in one or more intermediate fields between the finite field having two elements and the encoding field.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: October 27, 2020
    Assignee: AALBORG UNIVERSITET
    Inventors: Diego Ruano, Daniel E. Lucani, Olav Geil
  • Patent number: 10812223
    Abstract: Techniques to reduce the transmission overheads in a communication system are disclosed. In an embodiment, a method described herein relates to the elimination of redundant padding to realize an integer number of FEC code-words during the FEC-encoding process of transmission as well as the reduction/elimination of redundant padding to realize an integer number of transmission symbols during the subcarrier modulation mapping process of transmitting OFDM/ACMT/DMT symbols. The techniques are described in the context of a communication system based on the MoCA specification. Furthermore, techniques for channel-profiling, channel-estimation and bandwidth request/grant signaling that facilitate the realization of the method of reduction of transmission overheads in a MoCA system are also described.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 20, 2020
    Assignee: Entropic Communication, LLC
    Inventors: Rahul Malik, Vipin Aggarwal
  • Patent number: 10812258
    Abstract: Systems, apparatuses, methods, and computer program products are disclosed for session authentication. An example method includes receiving, by decoding circuitry and over a quantum line, a set of qbits generated based on a first set of quantum bases. The example method further includes decoding, by the decoding circuitry and based on a second set of quantum bases, the set of qbits to generate a decoded set of bits. The example method further includes generating, by session authentication circuitry, a session key based on the decoded set of bits.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 20, 2020
    Assignee: WELLS FARGO BANK, N.A.
    Inventor: Masoud Vakili
  • Patent number: 10700813
    Abstract: Various embodiments disclosed herein provide for a transmitter that can adjust the size of an information block or segment the information block based on a forward error correction (FEC) code optimum efficiency. Certain FEC codes are more efficient at encoding and decoding longer information blocks and if an information block is shorter than a predetermined length, the transmitter can pad the information block with a group of null bits to lengthen the information block to increase the performance of encoding and decoding the information block. In some embodiments, the transmitter can segment the information block into a set of segments, and if the last segment is below the predetermined length, the transmitter can pad the last segment.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: June 30, 2020
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Xiaoyi Wang, Arunabha Ghosh
  • Patent number: 10694177
    Abstract: A TDR technique for performing in-service distance-to-fault measurements in cable TV networks is disclosed. Using a cable network tester configured to generate chirped probe pulses and to perform pulse-matched filtering and averaging of received echoes, network faults may be detected without interfering with the downstream reception. The probe pulse transmission may be timed to take advantage of the error correction coding in the network.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 23, 2020
    Assignee: VIAVI SOLUTIONS INC
    Inventors: Kyle Harris, Daniel K. Chappell
  • Patent number: 10627240
    Abstract: Disclosed is a feature for a vehicle that enables taking precautionary actions in response to conditions on the road network around or ahead of the vehicle, in particular, a curved portion of a road where the curvature increases between adjacent curved sections. A database that represents the road network is used to determine locations where curvature between adjacent curved sections increases. Then, precautionary action data is added to the database to indicate a location at which a precautionary action is to be taken about the location where curvature increases. A precautionary action system installed in a vehicle uses this database, or a database derived therefrom, in combination with a positioning system to determine when the vehicle is at a location that corresponds to the location of a precautionary action. When the vehicle is at such a location, a precautionary action is taken by a vehicle system as the vehicle is approaching a location where the curvature increases.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: April 21, 2020
    Assignee: HERE Global B.V.
    Inventor: Robert Denaro
  • Patent number: 10630424
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; and when the reception error is occurred, disabling the descrambler of the lowest layer and issuing a first request to the second side for directing the second side to disable a scrambler, thereby disabling the second side to protect second data to be transmitted to the first side by using a data scrambling technique.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Fu-Jen Shih
  • Patent number: 10630425
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; sending a NAC (negative acknowledgement control) frame to the second side to inform the second side that the reception error is occurred for the first data each time the reception error is determined for the first descrambled data; and when a total number of occurrences of the reception errors reaches a predefined threshold, disabling the descrambler of the lowest layer.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Yu-Da Chen
  • Patent number: 10581465
    Abstract: An apparatus for constituent code processing in polar successive cancellation list (SCL) decoding and a method thereof. The apparatus includes a processor configured to determine an activation value I and a number r of the candidate paths, where I is a binary value and r is an integer, (I, r)=ƒ(R, k, m), ƒ is a function, R is a number indicating node reliability, k is an integer indicating a number of information nodes, and m is an integer indicating a number of leaf nodes; determine min1, min2, . . . , minq, wherein q is a number of least reliable bits; determine r candidate paths; determine path metrics PMtj of a codeword j for each candidate path t; and select r most probable paths based on PMtj.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hsien-Ping Lin, Jung Hyun Bae
  • Patent number: 10546640
    Abstract: A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string; performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units; inputting the block information to an error checking and correcting (ECC) circuit of the memory storage device to generate a second string; and storing the second string into the rewritable non-volatile memory module.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 28, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Tsung-Lin Wu, Te-Chang Tsui, Chien-Fu Lee
  • Patent number: 10439654
    Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data components via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 8, 2019
    Assignee: Primos Storage Technology, LLC
    Inventor: Robert E. Cousins
  • Patent number: 10404283
    Abstract: A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 3, 2019
    Assignee: Silicon Motion Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10382069
    Abstract: A method for data encoding includes receiving a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H. An intermediate vector s is produced by multiplying the data vector by a data sub-matrix Hs of the parity-check matrix H. A parity part of the code word is derived by applying a sequence of operations to the intermediate vector s based on a decomposition of a parity sub-matrix Hp of the matrix H using matrices A, C, U and V, in which decomposition A is a block triangular matrix that has the same size as Hp, C is matrix that is smaller than Hp, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation Hp=A+UCV.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 13, 2019
    Assignee: APPLE INC.
    Inventors: Moti Teitel, Tomer Ish-Shalom, Yonathan Tate
  • Patent number: 10379938
    Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Steven R. King, Frank L. Berry, Michael E. Kounavis
  • Patent number: 10374759
    Abstract: A high throughput communication apparatus which provides low frame error rates (FER). Error checking encoder and decoders which each comprise a plurality of short blocklength error checking encoders or decoders, respectively, in parallel, coupled through common incremental redundancy. Short-blocklength codes are utilized to achieve communication capacity with incremental redundancy. The system can transmit and decode a large number of short-blocklength codewords in parallel, while it delivers incremental redundancy, without feedback, only to the decoders that need incremental redundancy.
    Type: Grant
    Filed: May 13, 2018
    Date of Patent: August 6, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Richard Wesel, Kasra Vakilinia, Sudarsan V S Ranganathan, Dariush Divsalar, Haobo Wang
  • Patent number: 10360098
    Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson, Robert J. Safranek
  • Patent number: 10314027
    Abstract: A method for transmitting a downlink message on a downlink between an access network and a plurality of terminals. The downlink message includes main data to be transmitted to a receiving terminal. Error detection data is generated from the main data. Main data and/or error-detection data are modified on the basis of an identifier of the receiving terminal, using a predefined reversible modification function. The modification is performed at a constant spectral width and for a constant duration with respect to the aforementioned main data and/or error-detection data. A downlink message including the main data and the error-detection data obtained after modification are transmitted. Also, a method for receiving the downlink messages.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 4, 2019
    Assignee: SIGFOX
    Inventor: Lionel Zirphile
  • Patent number: 10268374
    Abstract: Systems and method for accessing data in a storage network include a processing module receives redundant array of independent disks (RAID) data to store determining which memories to utilize (e.g., a RAID memory, local and/or remote dispersed storage network (DSN) memory) based on one or more of the metadata, the RAID data, a vault lookup, a command, a message, a performance indicator, a predetermination, local DSN memory capabilities, remote DSN memory capabilities, RAID memory capabilities, and a comparison of requirements to capabilities of the RAID memory and local and/or DSN memory. The processing module saves the determination choice in a memory indicator that is stored in one or more of the RAID memory, the local DSN memory, the remote DSN memory, and a DSN user vault.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gary W. Grube, Jason K. Resch
  • Patent number: 10243588
    Abstract: An error correction code (ECC) decoder includes a finite state machine (FSM) controller and a shared logic circuit. The FSM controller generates a first control signal and a second control signal each corresponding to a certain state. The shared logic circuit includes a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation and an error correction operation, in response to the first and second control signals.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: March 26, 2019
    Assignee: SK hynix Inc.
    Inventor: Soojin Kim
  • Patent number: 10218494
    Abstract: In a general aspect, a cryptography process performs modular operations, where the modulus is a non-Mersenne prime. In some aspects, an integer is obtained during execution of a cryptography protocol defined by a cryptosystem. A prime modulus is defined by the cryptosystem in terms of a set of constants. The set of constants includes at least a first constant and a second, distinct constant. A set of block coefficients is computed to represent the integer in a block form. The plurality of block coefficients includes a first block coefficient obtained by a first modular reduction modulo the first constant, and a second block coefficient obtained by a second modular reduction modulo the second constant. A reduced representation of the integer is computed based on the plurality of block coefficients, such that the reduced representation is less than the prime modulus.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 26, 2019
    Assignee: ISARA Corporation
    Inventors: Victoria de Quehen, Shane Daniel Kelly
  • Patent number: 10164660
    Abstract: An integrated circuit may include a Reed-Solomon decoder that receives a transmitted code word and an associated bit mask and that generates a corresponding corrected message. The bit mask indicates an erasure pattern for the received code word. The Reed-Solomon decoder may include a syndrome generator, a multiplication circuit, a read-only memory (ROM) circuit, an address compressor, and an aggregation circuit. The syndrome generator may receive the transmitted code word and generate a corresponding syndrome. The address compressor may receive the bit mask and generate a corresponding unique address for accessing the ROM circuit. The ROM circuit may then output an inverse parity matrix based on the unique address. The multiplication circuit may multiply the syndrome by the retrieved inverse parity matrix to output corrected symbols. The aggregation circuit may then path the received code word with the corrected symbols to obtain the corrected message.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Simon Finn, Martin Langhammer, Sami Mumtaz
  • Patent number: 10073735
    Abstract: Systems and methods are disclosed for a seeding mechanism for error detection codes. An error detection code may be generated using specifically modified seed input and stored to data sectors not containing valid data. A data storage device may determine if read attempts are directed to an invalid sector by analysis of the stored error detection code. In some embodiments, an apparatus may determine a first error detection code stored to a target data storage sector does not match a second error detection code calculated for the target data storage sector, compare the first error detection code to a modified error code value to determine whether the target data storage sector contains valid data, and return an indication that the target data storage sector does not contain valid data when the error detection code matches the modified error code value.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: September 11, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jun Cai, Jeetandra Kella, ChuanPeng Ong, Brian T Edgar
  • Patent number: 10033484
    Abstract: Techniques to reduce the transmission overheads in a communication system are disclosed. In an embodiment, a method described herein relates to the elimination of redundant padding to realize an integer number of FEC code-words during the FEC-encoding process of transmission as well as the reduction/elimination of redundant padding to realize an integer number of transmission symbols during the subcarrier modulation mapping process of transmitting OFDM/ACMT/DMT symbols. The techniques are described in the context of a communication system based on the MoCA specification. Furthermore, techniques for channel-profiling, channel-estimation and bandwidth request/grant signaling that facilitate the realization of the method of reduction of transmission overheads in a MoCA system are also described.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 24, 2018
    Assignee: Entropic Communications, LLC
    Inventors: Rahul Malik, Vipin Aggarwal
  • Patent number: 9934841
    Abstract: A memory refreshing circuit implemented on an integrated circuit comprising a memory circuit that stores original data and an algorithmic data generation circuit that generates write addresses and correct data such that the correct data is stored in the memory circuit at locations that are indicated by the write addresses to correct errors in the original data by overwriting the original data with the correct data during a random access mode of operation of the memory circuit.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 3, 2018
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Sami Mumtaz
  • Patent number: 9852809
    Abstract: Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. The control circuit further provides the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and suppresses providing the error signal when the number of bit errors detected is less than the predetermined number.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 26, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Toru Ishikawa
  • Patent number: 9722636
    Abstract: An arrangement for decoding a data word using a Reed-Muller code, has: (1) N input terminals, (2) a first level of E>>D summing modules, each summing module being linked with F different input terminals and each input terminal being linked with E summing modules, (3) a first level of E decision modules, each of the D inputs of each decision module being linked respectively with an output from D different summing modules, (4) a second level of H summing modules, (5) a second level of G decision modules, (6) a third level of G summing modules, and (7) G output terminals. N signifies the code length and D signifies the minimum spacing of the code, E is equal to D-2, F is equal to N/D, G is the number of symbols of the data word that need to be corrected and is a natural number between 1 and E<<D.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: August 1, 2017
    Assignee: Eberhard Karls Universitaet Tuebingen
    Inventors: Juliane Bertram, Michael Huber, Peter Hauck
  • Patent number: 9716606
    Abstract: In a WLAN, a device generates a short training field and a long training field following the short training field. The device generates a first signal field following the long training field, and the first signal field includes a mode field for indicating a transmission mode of a frame to be transmitted and a check bit for protecting at least the mode field. The device transmits the frame including the short training field, the long training field, and the first signal field.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 25, 2017
    Assignee: NEWRACOM, INC.
    Inventors: Ilgu Lee, Jeongchul Shin, Kyeongpyo Kim, Jongee Oh, Dae Kyun Lee
  • Patent number: 9699578
    Abstract: A wireless interface device for at least one of wireless transmission from an electric analog audio device or wireless reception at an electric analog audio device of an audio signal, comprises an audio connector jack plug or jack socket in communication with a system that is at least one of a wireless internet system or a WLAN-enabled system and connectable to at least one of an audio connector jack plug of the electric analog audio device, or an audio connector jack socket of the electric analog audio device.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: July 4, 2017
    Assignee: INGENIOUS AUDIO LIMITED
    Inventor: John Crawford
  • Patent number: 9628944
    Abstract: An embodiment takes the form of a method carried out by a communication device. A binary data sequence is obtained at a communication device for transmission via a Bluetooth data link configured according to an audio-codec-based Bluetooth profile, wherein an audio codec is configured to receive a multi-bit data byte and output a single bit indicating whether the received multi-bit data byte is larger or smaller than a prior output reference byte, a multi-bit data byte sequence is generated based on the binary data sequence, the multi-bit data byte sequence is provided to the audio codec to induce the codec to generate a one-bit per-sample binary sequence representative of the binary data sequence, and, the generated one-bit per-sample binary sequence is transmitted via the Bluetooth data link.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: April 18, 2017
    Assignee: NAGRAVISION S.A.
    Inventor: Steven Seltzer
  • Patent number: 9594629
    Abstract: A computing device for correcting data errors may receive data stored by a memory device; calculate a syndrome associated with the data; initiate a calculation of error correction information for the data based on the syndrome; search for the error correction information in a cache based on the syndrome; discontinue the calculation of the error correction information when the error correction information is found in the cache before the error correction information is calculated; and correct an error associated with the data using the error correction information from the cache.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: March 14, 2017
    Assignee: KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
    Inventors: Abdullah Alawi AlJuffri, Mohammed Sulaiman BenSaleh, Abdulfattah Mohammad Obeid, Syed Manzoor Qasim
  • Patent number: 9559810
    Abstract: According to various aspects of the present disclosure, medium access control (MAC) sublayer logic of a device or a system may generate and implement a preamble structure of a data unit including a signal field which includes a four-bit cyclic redundancy check sequence providing a Hamming distance of two. The signal field portion of the preamble structure may include information related to a plurality of physical layer parameters used for wireless communication of the data unit. The preamble structure may be stored on a machine-accessible medium. The preamble may be generated by a data unit builder of the device, which may further receive a frame including a data payload, and encapsulate the frame with the preamble portion to generate the data unit. A transmitter coupled with the data unit builder may then wirelessly transmit the data unit using an antenna array.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Thomas Tetzlaff, Minyoung Park
  • Patent number: 9543980
    Abstract: An encoder generates a compressed data sequence from an original data sequence using many-to-one mapping independently of a source model associated with the original data sequence and without extracting the source model. A decoder uses both the source model associated with the original data sequence and the mapping applied during compression that is devoid of, in substance, the source model, to regenerate, at least in part, the original uncompressed data sequence from the compressed data sequence that does not include a significant portion of the source model.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: January 10, 2017
    Assignee: Massachusettes Institute of Technology
    Inventors: Ying-Zong Huang, Gregory W. Wornell
  • Patent number: 9544401
    Abstract: A data communication device includes a storage unit configured to store transmission data in a transmission ring buffer area; a read-out processing unit configured to read out the transmission data from the storage unit; and a transmission and reception processing unit configured to transmit the read-out transmission data to an external network and receive a reception confirming notification for the transmitted transmission data. The transmission and reception processing unit is configured to control the read-out processing unit so that the transmission data to be transmitted is read out based on a storage position of last data of the transmission data stored in the transmission ring buffer area and a storage position of last data of the transmitted transmission data indicated by the reception confirming notification.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: January 10, 2017
    Assignee: Ricoh Company, Ltd.
    Inventor: Hiroshi Satoh
  • Patent number: 9536120
    Abstract: The invention discloses a method for enhancing stability of communication between a contactless card and a card reader, relating to communication field.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: January 3, 2017
    Assignee: Feitian Technologies Co., Ltd.
    Inventors: Zhou Lu, Huazhang Yu
  • Patent number: 9529665
    Abstract: Double consecutive error correction is described. An integrated circuit with double consecutive error correction logic includes a data storage structure operative to store a set of data and a first error correction code that corresponds to the set of data. The set of data includes multiple data bits. The first error correction code was generated using a generator matrix having multiple bit groups, each bit group including a unique set of bit positions. The integrated circuit also includes an error correction code generator operative to generate, using the generator matrix, a second error correction code that corresponds to the set of data. The integrated circuit further includes a comparator operative to generate a comparison result of the first error correction code and the second error correction code. The integrated circuit includes a data corrector operative to correct two consecutive data bits of the set of data.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Gilad Cohen
  • Patent number: 9489252
    Abstract: Diverse erasure encoded fragments, that is, fragments produced by different erasure encoding schemes, may be used to reconstruct a data file. The diverse erasure encoded fragments for the data file are collected and the erasure encoding schemes used to generate the fragments are identified. A fragment matrix is generated from these fragments. An expanded encoding matrix is generated based upon the identified erasure encoding schemes. One or more rows may be removed from the expanded matrix to generate a square matrix. If the square matrix is invertible then it is inverted to provide a decoding matrix. One or more corresponding rows may be removed from the collected fragment matrix. The decoding matrix and the collected fragment matrix are multiplied to recover the data file. Padding symbols may be added to one or more fragments so that all fragments have the same number of symbols per fragment.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: November 8, 2016
    Assignee: Amazon Technologies, Inc.
    Inventor: Bryan James Donlan
  • Patent number: 9473176
    Abstract: A method, including factoring an order of a multiplicative group of a Galois Field to produce a first integer factor p and a second integer factor q, wherein the multiplicative group includes (2m?1) elements, m a non-negative integer, so that 2m?1=pq. The method further includes receiving an element x of the Galois Field expressible as ?(qi+j), where ? is a primitive element of the group, i is a first non-negative integer less than p, and j is a second integer less than q. An inverse or a logarithm of the element x is calculated as a function of qi and j.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: October 18, 2016
    Assignee: APPLE INC.
    Inventors: Moti Teitel, Micha Anholt
  • Patent number: 9419652
    Abstract: The present disclosure illustrates a BCH decoding method and a decoder thereof. In this BCH decoding method, the BCH decoder receives an encode data at first, then calculates a syndrome of the encode data. After calculating the syndrome of the encode data, the BCH decoder calculates at least one error location of the encode data in response to the syndrome. Next, the BCH decoder detects at least one determining bit which a first bit string of the encode data comprises. The determining bit is configured for operatively determining whether to continue decoding the encode data. Finally, when the determining bit is detected, an error correction is then performed based upon the error location, such that the BCH decoder outputs decode data.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 16, 2016
    Assignee: STORART TECHNOLOGY CO., LTD.
    Inventor: Jui-Hui Hung
  • Patent number: 9397706
    Abstract: A method for non-uniform multiple dimensional decoding, the method may include receiving or generating a multiple dimensional encoded data unit; and decoding by a processor the multiple dimensional encoded data unit to provide a decoded data unit; wherein the multiple dimensional encoded data unit comprises multiple component codes associated with multiple dimensions; wherein the multiple dimensions comprise a plurality of non-uniform dimensions; wherein at least two component codes of each non-uniform dimension differ from each other by encoding rate; wherein the decoding is responsive to encoding rates of component codes of the plurality of non-uniform dimensions.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: July 19, 2016
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 9362953
    Abstract: A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·?3ji+Zw2·?2ji+Zw1·?ji+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)?(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value ?vi= for the bit position i may then be determined on the basis of the error correction expression evaluated for ?ji.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Michael Goessel, Christian Badack
  • Patent number: 9350385
    Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 24, 2016
    Assignee: XILINX, INC.
    Inventors: Weirong Jiang, Gordon J. Brebner, Mark B. Carson
  • Patent number: 9342271
    Abstract: According to one embodiment, a processing device for multiplying a first polynomial with a second polynomial is described including a first memory storing a representation of the first polynomial, a controller configured to separate the first polynomial into parts, a second memory storing pre-determined results of the multiplications of the second polynomial with possible forms of the parts of the first polynomial, a third memory for storing the result of the multiplication, an address logic, configured to determine, for each part of the first polynomial, a start address of a memory block of the second memory based on the form of the part and the location of the part within the first polynomial and an adder configured to add, for each determined address of the memory block of the second memory, the content of the memory block of the second memory at least partially to the contents of the third memory, wherein the data element of the third memory to which the content of a data element of the memory block of th
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 17, 2016
    Assignee: Infineon Technologies AG
    Inventors: Andrea Hoeller, Tomaz Felicijan
  • Patent number: 9312883
    Abstract: Cyclic redundancy check (CRC) circuitry of a given input data path width is provided to perform CRC on data packets with fixed/variable word length where either the start of packet or the end of packet or both don't need to be aligned with the last and first word or bit of the CRC circuitry's input data path. The CRC circuitry is organized in a hierarchical configuration. A first level performs partial cyclic redundancy checks which are then combined in a second level to perform the cyclic redundancy check from all received data words or bits independent of the start of packet and end of packet positions. The hierarchical configuration enables the increase of the input data path width without incurring the significant increase in area observed for conventional CRC circuitry. This also decreases the number and length of interconnects compared to conventional CRC circuitry, and thus facilitates timing closure.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: April 12, 2016
    Assignee: Altera Corporation
    Inventors: David W. Mendel, Gregg William Baeckler