Abstract: A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.

Abstract: A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.

Abstract: Received communication signals may be decoded according to a combined, iterative inner code-outer code decoding technique. The inner code decoding is based on information produced by the outer code decoding.

Abstract: The present disclosure is directed to a system and method of correcting video data errors. In a particular embodiment, the method includes receiving a stream of data packets at a re-generator of an Internet Protocol (IP) video transport stream. The stream of data packets includes a plurality of IP media packets and a plurality of forward error correction (FEC) packets. The method also includes determining an error profile of an error within the plurality of IP media packets. The method includes identifying one of the plurality of FEC packets, where the identified FEC packet is associated with an error correction code corresponding to the error profile. The method also includes selecting an inverse FEC function from a plurality of inverse FEC functions. The selected inverse FEC function corresponds to the identified FEC packet.

Abstract: The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.

Abstract: An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the nonvolatile memory include an error beyond an error correcting capability of the error correcting device. When the determining unit has determined that an error beyond the error correcting capability exists, the error correcting device does not perform the correction of the error.

Abstract: Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.

Abstract: A Euclid processing module for binary BCH code which have been encoded with multidimensional Galois fields, and which correct a large number of word errors. The coefficients of polynomials Ri(z) and Bi(z) are stored in registers, and they are subjected to Galois field calculations by a processing module. The results of the calculations and the data of the registers are shifted by a shifter and a zero insertion unit, or some of the coefficients are erased and are stored in a register group again by finally controlling selectors with a sequencer. A necessary polynomial ?(z) is calculated by repeating the processing. The Euclid processing module decreases a logic scale and simplifies controlling logic in a state of small latency and high operating frequency.

Abstract: An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one Values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.

Abstract: A method for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. The method includes generating a plurality of column groups by grouping (categorizing) columns corresponding to an information word in a parity-check matrix of the LDPC code, and ordering the column groups; determining a range of an information word desired to be obtained by performing shortening; based on the determined range of the information word, performing column group-by-column group shortening on the column groups in order according to a predetermined shortening pattern; and LDPC encoding the shortened information word.

Abstract: The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only “1s”, the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof “0”, followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.

Abstract: A coding system comprises pre-multiply the message u(x) by Xn?k. Obtain the remainder b(x), i.e. the parity check digits. And combine b(x) and Xn?ku(x) to obtain the code polynomial. A decoding method comprises calculating a syndrome; finding an error-location polynomial; and computing a set of error location numbers.

Abstract: A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

Abstract: A present invention discloses a method for performing forward error correction (FEC) in long-haul submarine transmission systems. Data is encoded at a transmitter by serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting codes. The invention encodes a stream of data employing a plurality of serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting codes, arranging said data into a frame of parallel data blocks (the outer frame) with redundancy bits appended by a BCH(3896, 3824) code; the outer frame is then interleaved to produce a frame of serial data blocks (the intermediate frame); and the final frame (the inner frame) is produced by appending the redundancy bits of the BCH(2040, 1952) code to the intermediate frame. The data, once encoded, is transmitted across a datapath and decoded at the receiver.

Abstract: There is disclosed a memory device with an error detection and correction system formed therein, the error detection and correction system being configured to detect and correct errors in read out data by use of a BCH code, wherein the error detection and correction system is 4-bit error correctable, and searches error locations in such a way as to: divide an error location searching biquadratic equation into two or more factor equations; convert the factor equations to have unknown parts and syndrome parts separated from each other for solving them; and compare indexes of the solution candidates with those of the syndromes, the corresponding relationships being previously obtained as a table, thereby obtaining error locations.

Abstract: An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.

Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.

Abstract: A forward error correcton coding method comprises a generalized concatenated code comprising a plurality of outer component codes and a plurality of inner component codes. The outer components codes comprise Reed-Solomon codes and a plurality of binary codes of equal length but varying rates. The inner component codes have a nested structure and are defined by the sum of disjoint Bose-Chaudhuri-Hocquenghem (BCH) codes. The inner and outer component codes are selected such that the product of the minimum Hamming distances of the inner and outer component codes are as equal as possible. Moreover, the component codes are selected by matching cyclotomic cosets of inner BCH codes and type and multiplicity of outer codes.

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract: A method and apparatus for increasing the data rate and providing antenna diversity using multiple transmit antennas is disclosed. A set of bits of a digital signal are used to generate a codeword. Codewords are provided according to a channel code. Delay elements may be provided in antenna output channels, or with suitable code construction delay may be omitted. n signals represent n symbols of a codeword are transmitted with n different transmit antennas. At the receiver MLSE or other decoding is used to decode the noisy received sequence. The parallel transmission and channel coding enables an increase the data rate over previous techniques, and recovery even under fading conditions. The channel coding may be concatenated with error correction codes under appropriate conditions.

Abstract: Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of data locations, and an error detection module coupled to the quantizing circuit. In some embodiments, the error detection module includes an encoder configured to encode incoming data with redundant data derived from the incoming data and a decoder configured to detect errors in stored data based on the redundant data.

Abstract: A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency. Parallel syndrome evaluations with a parallel multiplier.

Abstract: A first demultiplexer and a second demultiplexer receive and demultiplex STM-64 data to generate parallel data. A FEC frame generating encoder carries out error correction encoding operation in a column direction of the parallel data that constitutes a matrix, adds a resulting error correcting code to the parallel data, carries out error correction encoding operation in a row direction of the parallel data, and further adds a resulting error-correcting code to the parallel data. A first multiplexer and a second multiplexer multiplex the error-correction-encoded parallel data, and output the data as a FEC frame.

Abstract: The present invention presents a non-volatile memory and method for its operation that allows instant and accurate detection of erased sectors when the sectors contain a low number of zero bits, due to malfunctioning cells or other problems, and the sector can still be used as the number of corrupted bits is under the ECC correction limit. This method allows the storage system to become tolerant to erased sectors corruption, as such sectors can be used for further data storage if the system can correct this error later in the written data by ECC correction means.

Abstract: Determination of the location of an error condition or a failure includes receiving at a network interface a first framed digital signal from customer premises equipment, and determining whether the first framed digital signal indicates a failure. Overhead bits are modified in the first framed digital signal to generate a second framed digital signal, such that the modification is equivalent to insertion of errors into the first framed digital signal at a bit error ratio (BER) of not greater than a predetermined ratio, if the first framed digital signal indicates a failure. The second framed digital signal is then sent from the network interface in place of the first framed digital signal to indicate that the failure reported by the first framed digital signal is located in the customer premises equipment. Otherwise, if no failure is indicated, the first framed digital signal is transmitted without any modifications.

Abstract: A Bose-Chaudhuri-Hocquenghem (BCH) error correction circuit and method including storing normal data and first parity data in a memory cell array, the normal data and first parity data forming BCH encoded data; generating second parity data from the stored normal data; comparing the first parity data with the second parity data; and checking for an error in the normal data in response to the comparing.

Abstract: An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one Values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.

Abstract: Provided is a hybrid flash memory device, a memory system, and a method of controlling errors. The hybrid flash memory device includes a data storage block with first and second data storage regions of flash memory cells, and error control block implementing first and second error control schemes, such that a data access operation directed to data stored in the first data storage region selects the first error control scheme, and a data access operation directed to data stored in the second data storage region selects the second error control scheme.

Abstract: The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.

Abstract: An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t?1)/(codeword_len?3)?X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

Abstract: A method, apparatus, and computer-readable media comprises receiving a detected sequence representing a signal on a channel, wherein the detected sequence comprises data bits and one or more error detection code bits; receiving one or more error indications for the detected sequence, each of the one or more error indications identifying one of the data bits of the detected sequence that may have an erroneous value; detecting errors in the detected sequence based on the error detection code bits in the detected sequence; and generating a candidate sequence based on the detected sequence and the one or more error indications when errors are detected in the detected sequence.

Abstract: An apparatus for random parity check and correction with BCH code is provided, including a BCH parity check code encoder, a channel, a BCH parity check code decoder, and a static RAM (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in writing to flash memory. The channel is connected to the BCH parity check code encoder to compute the parity check code and the message polynomial into receiving data. The BCH parity check code decoder is connected to the channel for inputting the receiving data and using BCH decoding to compute the eigen value and error address. The SRAM is connected to the BCH parity check code decoder so as to read error address from static RAM, correct the data and restores the corrected data to the SRAM. Therefore, this achieves the object of random parity check and correction with BCH code.

Abstract: A system that produces one or more non-repeating randomizer sequences of up to 2m?1 or more m-bit symbols includes a randomizer circuit that is set up in accordance with a polynomial with primitive elements of GF(2m) as coefficients. The system combines the randomizer sequence with all the symbols of ECC code words that are encoded using a BCH code over GF(2m) to produce a randomized code word. The particular primitive elements used and/or an initial state of one or more registers in the system specifies the particular sequence produced by the system. The initial state of each of the one or more registers is a selected one of the 2m?1 elements of GF(2m), and thus, 2m?1 different sequences may be produced by selecting a different initial state for a given one of the registers. If the coefficients are also selected from, for example, a set of “p” possible values, the system produces p*(2m?1) different sequences.

Abstract: A method and structure of processing soft information in a block code decoder, includes a soft-input soft-output decoder receiving a length n soft input vector, creating a binary vector Y corresponding to the soft input vector, hard decoding each linear function Xi of Y and a test pattern Zi of one or more test patterns, wherein if the hard decoding is successful a codeword produced by the hard decoding of Xi is added to a set S, removing redundant codewords in S to form a reduced set S? based on processing a number of errors found during the hard decoding and a guaranteed error correcting capability of the block code decode, and an extrinsic value estimator generating n soft outputs based on c estimated soft output values and (n-c) non-estimated soft output values wherein the c estimated soft output values are computed from one or more positions of soft input vector and one or more codewords in S?.

Abstract: A semiconductor memory device including an error detection and correction system, wherein the error detection and correction system has a first operation mode for correcting one number-bit (for example 2) errors and a second operation mode for correcting another number-bit (for example 1) error(s), which are exchangeable to be set with a main portion of the system used in common.

Abstract: Stopping or reducing oscillations in Low Density Parity Check (LDPC) codes. A novel solution is presented that completely eliminates and/or substantially reduces the oscillations that are oftentimes encountered with the various iterative decoding approaches that are employed to decode LDPC coded signals. This novel approach may be implemented in any one of the following three ways. One way involves combining the Sum-Product (SP) soft decision decoding approach with the Bit-Flip (BF) hard decision decoding approach in an intelligent manner that may adaptively select the number of iterations performed during the SP soft decoding process. The other two ways involve modification of the manner in which the SP soft decoding approach and the BF hard decision decoding approach are implemented. One modification involves changing the initialization of the SP soft decoding process, and another modification involves the updating procedure employed during the SP soft decoding approach process.

Abstract: One set of syndromes is calculated from a first data string from among a plurality thereof including at least 2t+1 pieces of symbols as a parity string, and coefficients of an error locator polynomial from the one set of the syndromes. Whether or not a correction is successful is judged by using the coefficients of the error locator polynomial and the same calculation is performed for a second data string if a correction failure is judged. Contrarily, if a correction success is judged, an error of the first data string is corrected by using the aforementioned set of the syndromes and the coefficients of the error locator polynomial.

Abstract: Disclosed is a method for controlling the peak power of a filtered signal in a single carrier data transmission system. The method comprises the steps of receiving a digital sequence (13) from a data source; generating a new digital sequence (a(k)); shaping filtering (34) the new digital sequence (a(k)) and producing a filtered digital sequence (y(k)) Characterized in that the step of generating a new digital sequence (a(k)) comprises the steps of: encoding data by an algebraic error correcting code (28); and performing a bit modification (30) by deliberately adding errors in such a way that the peak power of the filter signal affected by the deliberately introduced errors is lower than the peak power of the signal unaffected by errors. Disclosed is also a circuit for performing the method.

Abstract: A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method used in a computing system comprising reading a codeword comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP) from the codeword, determining a total number of codeword errors from the ELP, and preventing access to the data within the codeword if the total number of codeword errors exceeds a maximum number of correctable errors.

Abstract: A method that measures a skew between a data signal and a clock signal at a receiving end of a serial link and then adjusts a phase relationship between the data signal and the clock signal to reduce the skew.

Abstract: Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8×8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.

Abstract: Binary data representing a code word of an error-correcting code is used for calculating a syndrome, wherein a given portion of the binary data comprises k groups of data bits and represents a field element of the finite field GF(pk), p being an odd prime number, the field element comprising k coefficients in accordance with a polynomial basis representation, each group of data bits of the given portion representing a corresponding one of the k coefficients. The given portion, is stored in a first general purpose register and is processed such that the k groups of data bits of the given portion are processed in parallel; determining whether the syndrome is equal to zero; and detecting and correcting errors in the binary data if the syndrome is not equal to zero.

Abstract: A logical data block in a MRAM is disclosed. The logical data block comprises magnetic memory cells formed at intersections of hard-axis generating conductors and an easy-axis generating conductor. The logical data block may further be configured in size by a preselected, block-based error correction code. A magnetic memory module and computer system including a MRAM having a logical data block according to embodiments of the present invention are also disclosed. Additionally, a method embodiment of reducing half-select write errors within a MRAM is disclosed.

Abstract: A method or apparatus for error identification of a BCH encoded signal includes processing that begins by receiving a BCH encoded signal in a binary polynomial format to produce a received polynomial. The processing then continues by converting the received polynomial into a plurality of error identifying polynomials. The processing then continues by recursively processing the plurality of binary error identifying polynomials to produce a plurality of error identifying values. The processing then continues by processing the plurality of error identifying values to produce an error locator polynomial that represents error in the received polynomial. The processing then continues by evaluating the error locator polynomial to identify the bit location of the error in the BCH encoded signal. The processing then continues by correcting the BCH encoded signal based on the bit location of the error.

Abstract: A method or apparatus for decoding of a BCH encoded signal begins by determining whether the received BCH encoded signal includes error. The decoding process continues when the received BCH encoded signal includes error by determining whether the error is correctable. This may be done by determining a number of errors of the received BCH encoded signal, identifying bit locations of the received BCH encoded signal having the error; counting the number of bit locations of the received BCH encoded signal having the error, comparing the number of errors to the number of bit locations of the received BCH encoded signal having the error, when the number of bit locations of the received BCH encoded signal having the error equals the number of errors, ceasing the identifying of the bit locations of the received BCH encoded signal having the error, and correcting information contained in the bit locations of the received BCH encoded signal having the error when the identifying of the bit locations is ceased.

Abstract: An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.

Abstract: A data buffer receives and temporarily stores data including a product code enabling error correction in first and second directions. An exclusive-OR operation circuit uses an error amount detected by error correction in the first direction and data stored in a storage element to calculate a first error check result. A PI direction error-checking circuit according to the first error check result performs error check after error correction in the first direction. A PO direction partial error-checking circuit and a PO direction aggregate error-checking circuit use an error amount detected in error correction in the second direction and calculate a second error check result. The first and second error check results are used to generate a final error check result by an exclusive-OR operation circuit.

Abstract: The invention relates to a method of storing a number of data bits of a secondary channel (30) in the frame of a main channel (20) and to a method of decoding a stream of bits relating to a secondary channel (30) embedded in the frames of a main channel (20) into a stream of data bits (62). In order to enable a certain synchronization and to guarantee a fixed amount of storage capacity in the secondary channel as well as to be able to correct deletions or insertions of bits in the secondary channel it is proposed according to the invention to form a secondary frame (11) having a fixed number of frame bits, to fill a fixed part of the secondary frame (11) with data bits (113), an end-bit (114) set to a first bit-value and, if necessary, with filling bits (115) set to a second bit-value, to encode the secondary frame (11) producing encoded data bits (113) and parity bits (112), which are finally embedded in the frame of the main channel (20).

Abstract: An enhanced forward error correction system is disclosed. Transmitted data is encoded into codewords in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes in each dimension, with corrected data provided as an output from each pass into another decoder for the next decode pass. The encoder in one embodiment comprises a parallel inner RS(247,239) encoder or encoders and parallel outer BCH(255,247) encoder or encoders. Additional steps are added for error multiplication reduction. The system provides an approach to detect generally uncorrectable patterns for concatenated codes and provides a correction mechanism for improving error correction performance.

Abstract: A method of turbo decoding using soft input-soft output information. A vector of data is sampled from a channel of data. The vector of data is then processed to output a final code word of bits. A final reliability vector of reliability values associated with the final code word is generated, such that each bit of the final code word of bits has a corresponding reliability value in the final reliability vector. Corresponding reliability values for one or more bit positions of the final code word are determined by a difference of distance metrics, and corresponding reliability values for one or more bit positions of the final code word are determined utilizing a numerical approximation.