Syndrome Computed Patents (Class 714/785)
  • Patent number: 11520853
    Abstract: A processor system comprises two groups of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate matrix for each channel. Each register stores at least one data element from each matrix. The hardware channel convolution processor unit is configured to multiply each data element in a first and second portion of the first group of registers with a corresponding data element in the second group of registers to determine corresponding multiplication results and sum together the multiplication results for each specific channel to determine two corresponding channel convolution result data elements in a corresponding channel convolution result matrix.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: December 6, 2022
    Assignee: Meta Platforms, Inc.
    Inventors: Krishnakumar Narayanan Nair, Rakesh Komuravelli, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
  • Patent number: 11513888
    Abstract: A data processing device includes a plurality of variable nodes configured to receive and store a plurality of target bits; a plurality of check nodes each configured to receive stored target bits from one or more corresponding variable nodes of the plurality of variable nodes, check whether received target bits have an error bit, and transmit a check result to the corresponding variable nodes; and a group state value manager configured to determine group state values of variable node groups into which the plurality of variable nodes are grouped.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Bo Seok Jeong, Soon Young Kang
  • Patent number: 11392454
    Abstract: A memory controller to control a memory module includes an error correction code (ECC) engine, a central processing unit to control the ECC engine and an error managing circuit. The ECC engine performs an ECC decoding on a read codeword set from the memory module to generate a first syndrome and a second syndrome in a read operation, corrects correctable error in a user data set based on the first syndrome and the second syndrome and provides the error management circuit with the second syndrome associated with the correctable error. The error managing circuit counts error addresses associated with correctable errors detected through read operations, stores second syndromes associated with the correctable errors by accumulating the second syndromes, determines attribute of the correctable errors based on the counting and the accumulated second syndromes, and determine an error management policy on a memory region associated with the correctable errors.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoyoun Kim, Kijun Lee, Chanki Kim, Myungkyu Lee
  • Patent number: 11386956
    Abstract: An optical mechanism and an optical system for optical-medium storage. The mechanism includes an optical-medium storage device, and an optical-medium transmission device. The optical-medium storage device is provided with an optical-medium storage module, configured to store an optical medium, and an optical-medium input-output end, configured to receive and transmit the optical medium to the optical-medium storage module and read data from the optical-medium storage module. The optical-medium receiving module is configured to receive the optical medium transmitted from outside and transmit the optical medium to the optical-medium storage module via the optical-medium input-output end, according to a receiving instruction. The optical-medium storing module is configured to form a storage path for the optical medium with the optical-medium storage module.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 12, 2022
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Dong Zhou
  • Patent number: 11368170
    Abstract: The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: June 21, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Benjamin P. Smith, Jamal Riani
  • Patent number: 11348658
    Abstract: A memory controller and a storage device including the same are provided. The memory controller performs decoding by selecting a decoder of a level enough to correct bit errors in a codeword from among a plurality of error correction code (ECC) decoders based on a bit error history of a non-volatile memory device.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 31, 2022
    Assignee: FADU Inc.
    Inventors: Hongseok Kim, Sang Hyun Park, Sunggil Hong, Hayoung Lim, EHyun Nam
  • Patent number: 11336302
    Abstract: Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: May 17, 2022
    Assignee: KANDOU LABS, S.A.
    Inventors: Amin Shokrollahi, Dario Carnelli
  • Patent number: 11334693
    Abstract: Computer systems and methods for constructing a model of the noise afflicting a quantum computer comprising a plurality of qubits are provided. A graph G that describes a conditional independence structure of the noise is obtained. The graph G includes a node for each qubit in the plurality of qubits. The noise afflicting the quantum computer is logically reduced to Pauli noise. The graph G is broken into a plurality of sets. Each respective set Cj in the plurality of sets (i) corresponds a respective qubit j in the plurality of qubits and (ii) comprises a representation of the respective qubit j and the parent qubits ?+j in the graph G. For each respective set Cj in the plurality of sets, a corresponding local conditional probability distribution Pr(ej|e?+j) is characterized in which ej?j is a Pauli error on the jth qubit.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 17, 2022
    Assignee: Keysight Technologies Canada Inc.
    Inventor: Steven T. Flammia
  • Patent number: 11334429
    Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: May 17, 2022
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen, Ying-Che Chung
  • Patent number: 11329764
    Abstract: An error correction device includes a first correction unit which performs error correction decoding of data by a repetitive operation, having a full operation state in which the error correction decoding is repeated until convergence is obtained and a save operation state in which the number of times of the repetitive operation is restricted to a predetermined number. An error information estimation unit estimates an input error rate or an output error rate of the first correction unit using a decoding result of the first correction unit, and a control unit which controls transition between the full operation state and the save operation state based on at least one piece of information of the input error rate, the output error rate, and an operation time of the first correction unit. It is thus possible to provide an error correction device that can improve a transmission characteristic while suppressing power consumption.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 10, 2022
    Assignees: NTT ELECTRONICS CORPORATION, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Fumiaki Nakagawa, Yasuharu Onuma, Katsuichi Oyama, Yasuyuki Endoh, Etsushi Yamazaki, Yoshiaki Kisaka, Masahito Tomizawa
  • Patent number: 11314592
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t?2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: April 26, 2022
    Inventors: Yeonggeol Song, Sungrae Kim, Kijun Lee
  • Patent number: 11275524
    Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system may transmit, to a host, target data, and, upon receiving, from the host, information indicating that at least one bit-flip has occurred in the target data, may perform an error handling operation on the at least one bit-flip in the target data. Accordingly, the memory system is able to reduce resource used in checking the bit-flip and to alleviate the constraints of the algorithms used in checking for the bit-flip.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11265021
    Abstract: A memory controller performs an error recovery operation. The controller performs a read operation on a select block using a select read level; decodes data associated with the read operation to generate a syndrome value; determines whether to stop, before a maximum number of iterations, the read operation and the decoding at the select read level, using the syndrome value; when it is determined to stop the read operation and the decoding at the select read level, selects a next read level in a sequence of read levels; and uses the next read level for a subsequent read operation.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyungjin Kim, Jaedeog Cho
  • Patent number: 11265022
    Abstract: A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Mun Seon Jang, Hoiju Chung, Tae Kyun Kim
  • Patent number: 11265012
    Abstract: A method of transmitting a message includes, for each data block, generating a root matrix using a generator, generating a quasi-cyclic matrix H using the root matrix, encoding the block using H to create a codeword, and transmitting the codeword. The root matrix includes three submatrices: an identity matrix in an upper-left-hand portion of the root matrix, an identity matrix in a lower-left-hand portion of the root matrix, and a circulant matrix in a right-hand portion of the root matrix. The circulant matrix equals the sum of an identity matrix and an identity matrix with rows shifted once to the right. Generating H includes expanding the root matrix by replacing 0 elements in the root matrix by a square matrix of 0 elements and replacing 1 elements in the root matrix by a shifted diagonal matrix. Non-zero elements of the diagonal matrix are selected from GF(q) based on the generator.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 1, 2022
    Assignee: U.S. Government as represented by the Director, National Security Agency
    Inventor: Bradley B. Comar
  • Patent number: 11203526
    Abstract: A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: December 21, 2021
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11169876
    Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Minari Arai
  • Patent number: 11099804
    Abstract: Aspects of the subject technology relate to electronic device display circuitry and methods of operating the display. The display circuitry a panel driver interface that decodes digital display data, for each display frame, received from host circuitry of the electronic device. The digital display data includes error correction and detection information for frame and line configuration information distributed in a frame packet and multiple line packets for each display frame. The frame and line configuration information facilitates, efficient, low-error, digital control of various display operational features.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: August 24, 2021
    Assignee: Apple Inc.
    Inventors: Fenghua Zheng, David S. Zalatimo, James E. Brown, Sachiko Oda, Johan L. Piper
  • Patent number: 11095310
    Abstract: An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Won Gyu Shin
  • Patent number: 11030043
    Abstract: An error correction circuit includes a syndrome calculator to calculate syndrome information of input data, an error position calculator to calculate error position information of the input data, a holder to hold the syndrome information or the error position information at a predetermined timing, an input switch to select one of error-corrected data of the input data, and the input data, and to input the selected data to the syndrome calculator, an error detection determiner to determine whether an error of the input data has been correctly detected, and an error corrector to correct the error of the input data based on information held by the holder and to output error-corrected input data when it is determined by the error detection determiner that the error has been correctly detected whereas to output the input data with no error correction when it is determined by the error detection determiner.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kosuke Hatsuda
  • Patent number: 11005499
    Abstract: A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae-Sung Kim, Soon-Young Kang, Bo-Seok Jeong
  • Patent number: 10931308
    Abstract: Described herein is an error correction circuit that includes a syndrome check history manager configured to maintain a history of syndrome checks corresponding to one or more iterations of the iterative decoding scheme. The error correction circuit also includes a trapping set detector configured to compare a trapping set determination policy with the history of syndrome checks to determine whether the history of syndrome checks meets criteria of the trapping set determination policy, while error correction decoding is performed, and determine that a trapping set exists when the history of syndrome checks satisfies the trapping set determination policy. The trapping set determination policy is related to at least one of a change in a syndrome vector, a number of UCNs, and a change in the number of UCNs.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Jang Seob Kim
  • Patent number: 10915337
    Abstract: A device that includes a node engine configured to determine a core distance for a correlithm object core. The core distance identifies a maximum number of hops away from a root correlithm object. The node engine is further configured to select a correlithm object in an n-dimensional space and set the selected correlithm object as the root correlithm object. The node engine is further configured to identify a plurality of correlithm objects within the core distance from the root correlithm object and link the identified plurality of correlithm objects with the root correlithm object to generate the correlithm object core.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: February 9, 2021
    Assignee: Bank of America Corporation
    Inventor: Patrick N. Lawrence
  • Patent number: 10903860
    Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak
  • Patent number: 10868570
    Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Ye-Sin Ryu, Young-Sik Kim, Su-Yeon Doo
  • Patent number: 10848182
    Abstract: An apparatus includes an interface and a decoder. The interface is configured to receive a code word, produced in accordance with an Error Correction Code (ECC) represented by a set of parity check equations. The code word includes a data part and a redundancy part, and contains one or more errors. The decoder is configured to hold a definition of a partial subgroup of the parity check equations that, when satisfied, indicate that the data part is error-free with a likelihood of at least a predefined threshold, to decode the code word by performing an iterative decoding process on the parity check equations, so as to correct the errors, and during the iterative decoding process, to estimate whether the data part is error-free based only on the partial subgroup of the parity check equations, and if the data part is estimated to be error-free, terminate the iterative decoding process.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: November 24, 2020
    Assignee: APPLE INC.
    Inventors: Yonathan Tate, Naftali Sommer, Asaf Landau, Armand Chocron
  • Patent number: 10824452
    Abstract: A device that includes a node engine configured to determine a core distance for a correlithm object core. The node engine is further configured to select a correlithm object in an n-dimensional space and set the selected correlithm object as the root correlithm object. The node engine is further configured to identify a plurality of correlithm objects within the core distance from the root correlithm object and determine one or more correlithm objects from among the identified plurality of correlithm objects is within a core distance of a second root correlithm object. The node engine is further configured to reduce the core distance for the correlithm object core, identify a second plurality of correlithm objects within the reduced core distance from the root correlithm object, and link the second identified plurality of correlithm objects with the root correlithm object to generate the correlithm object core.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 3, 2020
    Assignee: Bank of America Corporation
    Inventor: Patrick N. Lawrence
  • Patent number: 10810028
    Abstract: A device that includes a node engine configured to determine a core distance for a correlithm object core. The node engine is further configured to select a first correlithm object in an n-dimensional space and set the first correlithm object as the root correlithm object. The node engine is further configured to receive a second correlithm object and determine the distance between the root correlithm object and the second correlithm object. The node engine is further configured to determine whether the distance between the root correlithm object and the second correlithm object is less than core distance for the correlithm object core. The node engine is further configured to identify the second correlithm object as a member of the correlithm object core in response to determining the distance between the root correlithm object and the second correlithm object is less than core distance for the correlithm object core.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 20, 2020
    Assignee: Bank of America Corporation
    Inventor: Patrick N. Lawrence
  • Patent number: 10810026
    Abstract: A device that includes a node engine configured to define a number of child correlithm objects for a string correlithm object. The node engine is further configured to select a correlithm object from an n-dimensional space and set the selected correlithm object as a parent correlithm object. The node engine is further configured to iteratively identify the defined number of child correlithm objects, where identifying the defined number of child correlithm objects involves randomly selecting correlithm objects less than the standard distance away from the parent correlithm object and defining the selected correlithm objects as a child correlithm object. The node engine is further configured to link the defined child correlithm objects with the parent correlithm object in the node table to generate the string correlithm object.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 20, 2020
    Assignee: Bank of America Corporation
    Inventor: Patrick N. Lawrence
  • Patent number: 10789081
    Abstract: A device that includes a node engine configured to define a number of child correlithm objects for a string correlithm object. The node engine is further configured to set a starting correlithm object as a first parent correlithm object and set an ending correlithm object as a second parent correlithm object. The node engine is further configured to randomly select a correlithm object less than the standard distance away from the first parent correlithm object, define the selected correlithm object as a child correlithm object, and link the child correlithm objects with the first parent correlithm object. The node engine is further configured to randomly select a correlithm object less than the standard distance away from the second parent correlithm object, define the selected correlithm object as a child correlithm object, and link the child correlithm objects with the second parent correlithm object.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 29, 2020
    Assignee: Bank of America Corporation
    Inventor: Patrick N. Lawrence
  • Patent number: 10727867
    Abstract: Enhanced error correction for data stored in storage devices are presented herein. A storage controller retrieves an initial encoded data segment stored on a storage media, computes information relating to errors resultant from decoding the initial encoded data segment, and stores the information in a cache. The storage controller retrieves subsequent encoded data segments stored on the storage media, augments a decoder using at least the information retrieved from the cache, and decodes the subsequent encoded data with the decoder to produce resultant data.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Refael Ben-Rubi, Eran Sharon
  • Patent number: 10705627
    Abstract: A method for generating a signal includes: encoding, by an active stylus, transmission information into n-bit q-ary codes; performing, by the active stylus, frequency modulation on the n-bit q-ary codes, respectively, to generate a plurality of encoded frequency-modulated signals; and combining, by the active stylus, a preset fixed-frequency signal for detecting a stylus tip position with the plurality of encoded frequency-modulated signals to form an encoded signal. A method for analyzing a signal, an active stylus, and a touchscreen are also provided. The method for generating a signal, the method for analyzing a signal, the active stylus, and the touchscreen transmit more coding information within a relatively short time, thereby solving a problem of low efficiency of information transmission between an active stylus and a touch screen.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 7, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Shili Dai
  • Patent number: 10608676
    Abstract: Methods and apparatus disclosed herein may be used to establish framing more efficiently in communication protocols with block-coded forward error correction. Such protocols generally involve the check of different bit-alignments searching for positions that yield zero syndromes. The search can be undesirably slow, particularly in the presence of received errors. The presently-disclosed bit-alignment testing technique reduces this search time by checking the syndrome at each data word as if that data word was the last of a code. In other words, the word positions are effectively checked without a prior assumption as to which words are the first and last of the code. This reduces the task to the number of different bit-alignments possible within a single data word, rather than the number of bit-alignments possible in a complete FEC code. In one implementation, the lock time is reduced by approximately 50 times when compared to a straightforward solution.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventor: Soren Laursen
  • Patent number: 10552242
    Abstract: Systems and methods for managing and repairing errors occurring on a plurality of servers in an automated server build process is provided. Systems may include a first error code from a plurality of error codes. The first error code may be associated with a failure. The system may further include a plurality of sets of action codes. When the failure occurs on a server, included in the plurality of servers, during the server build process, the system may be configured to receive an error code from the server that may correspond to the failure and check the error code against previously recorded error codes recorded on an error code table. When the error code is included in the error code table, the system may retrieve the corresponding action code, assign the action code to the failure and execute the action code on the server.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: February 4, 2020
    Assignee: Bank of America Corporation
    Inventor: Sasidhar Purushothaman
  • Patent number: 10530358
    Abstract: A switching circuit includes: a main switch array including multiple main switch elements respectively arranged on multiple main signal paths configured in a parallel connection, wherein the multiple main signal paths are coupled with a first circuit node; a main switch control circuit for controlling the multiple main switch elements; an auxiliary switch array including multiple auxiliary switch elements respectively arranged on multiple auxiliary signal paths configured in a parallel connection, wherein the multiple auxiliary signal paths are also coupled with the first circuit node; and an auxiliary switch control circuit for controlling the multiple auxiliary switch elements so as to maintain a total number of turned-on switch elements in the main switch array and the auxiliary switch array to be equal to or more than a threshold quantity.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Cheng-Pang Chan, Liang-Huan Lei
  • Patent number: 10459783
    Abstract: A decoder includes a syndrome calculator, a Key Equation Solver (KES) and an error corrector. The syndrome calculator receives an n-symbol code word encoded using a Reed Solomon (RS) code to include (n?k) redundancy symbols, calculates for the code word 2t syndromes Si, t=(n?k)/2 is a maximal number of correctable erroneous symbols. The KES derives an error locator polynomial {circumflex over (?)}(x) whose roots identify locations of erroneous symbols, by applying to the syndromes a number of t iterations. In each iteration the KES calculates two discrepancies between {circumflex over (?)}(x) and respective two candidates of {circumflex over (?)}(x), and derives from the two candidates an updated candidate of {circumflex over (?)}(x). The error corrector recovers the code word by correcting the erroneous symbols using the derived error locator polynomial {circumflex over (?)}(x).
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 29, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Jing Fang, Kok-Wui Cheong
  • Patent number: 10387341
    Abstract: Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dean Gans, Bruce Schober, Moo Sung Chae
  • Patent number: 10367529
    Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: July 30, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Chris Michael Brueggen, Ron M. Roth
  • Patent number: 10339004
    Abstract: A controller including: an initialization unit initializing values and states of variable nodes and initializing values of check nodes; a variable node update unit updating the values and states of the variable nodes; a check node update unit updating the values of the check nodes based on the updated values and states of the variable nodes; and a syndrome check unit deciding iteration of the operation of the variable node update unit and the check node update unit when the values of the check nodes are not all in a satisfied state, the variable node update unit calculates reliability values of the variable nodes and a reference flip value based on a result of a previous iteration, and the variable node update unit updates the values and states of the variable nodes based on the reference flip value and the reliability values and states of the variable nodes.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 2, 2019
    Assignee: SK hynix Inc.
    Inventor: Soon-Young Kang
  • Patent number: 10243589
    Abstract: Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yufei Li, Yong Lu, Yi Wang, Hao Yang
  • Patent number: 10237162
    Abstract: The invention relates to a device, in particular a router, for bundling a plurality of Internet access lines into a virtual Internet access line for the purpose of providing the sum of the bandwidths of the plurality of Internet access lines for a transmission of data via the virtual Internet access line, wherein the device divides a data packet to be transmitted among a plurality of data packets for separate transmission via the plurality of Internet access lines, wherein the device is designed to calculate redundancy information and to transmit said redundancy information along, from which redundancy information lost data packets can be restored, such that packet losses on an Internet access line do not lead to packet losses on the bundled virtual line.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: March 19, 2019
    Assignee: Viprinet Europe GmbH
    Inventor: Simon Kissel
  • Patent number: 10200064
    Abstract: Systems and methods for performing a parity check on encoded data are disclosed. Encoded data is received. A parity check is performed based on a parity check matrix. In response to determining the first parity check is successful, a parity check number is incremented. Additional parity checks are selectively performed on subsequent portions of the array based on comparing the incremented parity check number to a threshold.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 5, 2019
    Assignee: Marvell International Ltd.
    Inventors: Nedeljko Varnica, Viet-Dzung Nguyen, Shashi Kiran Chilappagari
  • Patent number: 10177794
    Abstract: An integrated circuit (IC) includes an encoder configured to receive input data including a plurality of data bits. The encoder includes a parity computation matrix circuit configured to arrange the data bits according to a matrix format to generate a parity computation matrix. A parity computation circuit is configured to compute a plurality of parity computation row terms corresponding to rows of the parity computation matrix respectively, compute a plurality of parity computation column terms corresponding to columns of the parity computation matrix respectively, and compute parity bits using the parity computation row terms and parity computation column terms. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory cell array in a memory.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 8, 2019
    Assignee: XILINX, INC.
    Inventors: Kumar Rahul, Amarnath Perla, Santosh Yachareni
  • Patent number: 10002086
    Abstract: In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 19, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Stella Achtenberg, Eran Sharon, Ran Zamir, Amir Shaharabany
  • Patent number: 9996419
    Abstract: Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.
    Type: Grant
    Filed: May 9, 2015
    Date of Patent: June 12, 2018
    Assignee: BitMICRO LLC
    Inventors: Rey H. Bruce, Joey B. Climaco, Noeme P. Mateo
  • Patent number: 9985654
    Abstract: An example method of erasure error correction in an IC includes receiving input data from a channel coupled to the IC, determining a bit pattern indicating survived blocks and erased blocks of a plurality of blocks in the input data and determining a number of integers, in a finite set of integers, greater than or less than an integer representing the bit pattern, the finite set of integers representing a finite set of possible values of the bit pattern based on an (m, k) erasure coding scheme. The method further includes generating an address for a memory, which stores a plurality of pre-computed decoding matrices based on the (m, k) erasure coding scheme, from the determined number of integers to obtain a pre-computed decoding matrix associated with the bit pattern. The method further includes recovering the erased blocks through matrix multiplication using the pre-computed decoding matrix and the survived blocks as parametric input.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: May 29, 2018
    Assignee: XILINX, INC.
    Inventor: Ming Ruan
  • Patent number: 9985661
    Abstract: Techniques for decoding potentially corrupted Reed-Solomon encoded messages are provided. To decode a message, an incoming message is classified into a group based on which symbols of the message have survived (a “survival pattern”). The same inversion matrix may be used for each survival pattern associated with a single group. This reduces the amount of work required and data that is to be stored in order to perform the matrix multiplication that decodes the message.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: May 29, 2018
    Assignee: XILINX, INC.
    Inventor: Hong Qiang Wang
  • Patent number: 9842494
    Abstract: A device, method, and computer-readable medium for correcting at least one error in readings of electricity meters, the method including receiving first readings of regular meters measuring electric energy delivered in each of a group of cables fed from a same distribution node in an electric grid during a period of time, receiving second readings of check meters measuring electric energy delivered in each of combinations of cables in the group of cables during the period of time, the combinations of cables being formed based on a redundant matrix in a generator matrix of a linear systematic block code, and correcting, in response to determining that at least one error been detected, the at least one error in the first readings of the regular meters and the second readings of the check meters.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: December 12, 2017
    Assignee: King Fahd University of Petroleum and Minerals
    Inventor: Wessam Ali Mesbah
  • Patent number: 9792812
    Abstract: A device, method, and computer-readable medium for correcting at least one error in readings of electricity meters, the method including receiving first readings of regular meters measuring electric energy delivered in each of a group of cables fed from a same distribution node in an electric grid during a period of time, receiving second readings of check meters measuring electric energy delivered in each of combinations of cables in the group of cables during the period of time, the combinations of cables being formed based on a redundant matrix in a generator matrix of a linear systematic block code, and correcting, in response to determining that at least one error been detected, the at least one error in the first readings of the regular meters and the second readings of the check meters.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: October 17, 2017
    Assignee: King Fahd University of Petroleum and Minerals
    Inventor: Wessam Ali Mesbah
  • Patent number: 9786387
    Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: October 10, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung, Jong-Pil Son, Kwang-Il Park, Seong-Jin Jang