Abstract: A technique for merging, via lattice surgery, a color code and a surface code, and subsequentially decoding one or more rounds of stabilizer measurements of the merged code is disclosed. Such a technique can be applied to bottom-up fault-tolerant magic state preparation protocol such that an encoded magic state can be teleported from a color code to a surface code. Decoding the stabilizer measurements of the merged code requires a decoding algorithm specific to the merged code in which error correction involving qubits at the border between the surface and color code portions of the merged code is performed. Error correction involving qubits within the surface code portion and within color code portion, respectively, may additionally be performed. In some cases, the magic state is prepared in a color code via a technique for encoding a Clifford circuit design problem as an SMT decision problem.

Abstract: Systems and methods herein provide for error correction via Low Density Parity Check (LDPC) coding. In one embodiment, a system includes a data buffer operable to receive a block of Low Density Parity Check (LDPC) encoded data. The system also includes a processor operable to reduce a belief propagation algorithm used to encode the LDPC encoded data into a quadratic polynomial, to embed the quadratic polynomial onto a plurality of quantum bits (qubits), and to decode the block of LDPC encoded data via the qubits.

Abstract: A method for constructing an n-qubit fault tolerant encode for any k-qubit quantum gate M, in any given quantum code [n, k, C], comprising: choosing a number n?k of independent spinors Sr from the first stabilizer C and a first ordered set SC consists of the independent spinors Sr; choosing a number n?k of independent spinors ?r from a second stabilizer ? in the intrinsic coordinate and a second ordered set ?r consists of the independent spinors ?r consist; implementing an encoding Qen, wherein the encoding Qen converts the first ordered set SC to the second ordered set S?, wherein the encoding Qen is a sequential product provided by sequential operations of a number n?k of unitary operators Qr; wherein each of the unitary operator Qr is composed of a single s-rotation or a product of two s-rotations; and wherein the encoding Qen converts and maps the rth independent spinor Sr in the first ordered set SC to the rth independent spinor ?r in the second ordered set S? correspondingly; a fault tolerant action Û i

Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data components via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams. Further exemplary implementations may comprise a transformation process that includes producing an H-sized intermediary for each of the W inputs, combining the H-sized intermediaries into an H-sized result, and processing the H-sized result into the H output data structures, groups or streams.

Abstract: Preventing quantum errors using a Quantum Error Correction Algorithm Trainer (QECAT) table is disclosed herein. In one example, a processor device of a computing device is to identify a subset of a plurality of QECAT table entries of a QECAT table, wherein each QECAT table entry of the subset corresponds to an occurrence of a quantum error. The processor device is further to obtain metadata from each QECAT table entry of the subset. The processor device identifies, based on the metadata from each QECAT table entry of the subset, a common characteristic of each occurrence of the quantum error. The processor device then determines, based on the common characteristic, a preventative action to prevent a future occurrence of the quantum error.

Abstract: An ECC decoder includes a syndrome calculation block, a fast path controller, a KES block, a CSEE block, an UED, and a multiplexer. The KES block includes a plurality of KES-stages to calculate and output an error location/magnitude polynomial of a syndrome outputted from the syndrome calculation block. Each of a second to last KES-stages of the plurality of KES-stages receives the error location/magnitude polynomial from the previous KES-stage to output an error location/magnitude polynomial generated by an additional calculating operation. The additionally calculated error location/magnitude polynomial is not transmitted to the next KES-stage but directly outputted when an error location and an error magnitude are identified by the additionally calculated error location/magnitude polynomial.

Abstract: Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

Abstract: Systems and methods for improving the error floor performance in decoding generalized product codes (GPC) are described. The systems and methods can implement a two stage process to decode a GPC block code and break a stall error pattern for the decoding the block code. In the first stage, erroneuous bits in a codeword can be flagged. In the second stage, some of these bits and related bits in a codeword can be toggled to generate one or more test patterns. The test patterns can be decoded and one of them can be selected using a particular selection criteria to ultimately break the stall error pattern and improve the error floor performance.

Abstract: Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, the second and third direction being perpendicular to the first direction, the second direction being opposite to the third direction; performing entangling operations on a third set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a fourth direction, the fourth direction being opposite to the first direction; applying Hadamard gates to the measurement qubits; and measuring the measurement qubits.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.

Abstract: Methods, systems, and apparatuses for stall mitigation in iterative decoders are described. A codeword is received from a memory device. The codeword is iteratively error corrected based on a first bit flipping criterion. A stall condition in the multiple error correction iterations is detected. In response to the detection, the codeword is error corrected based on a second bit flipping criterion that is different from the first bit flipping criterion.

Abstract: Methods, systems, and apparatus for parallel optimization of continuously running quantum error correction by closed-loop feedback. In one aspect, a method includes continuously and effectively optimizing qubit performance in-situ whilst an error correction operation on the quantum system is running. The method directly monitors the output from error detection and provides this information as feedback to calibrate the quantum gates associated with the quantum system. In some implementations, the physical qubits are spatially partitioned into one or more independent hardware patterns, where the errors attributable to each hardware pattern are non-overlapping. The one or more different sets of hardware patterns are then temporarily interleaved such that all physical qubits and operations are optimized. The method allows for the optimization of each section of a hardware pattern to be performed individually and in parallel, and can result is O(1) scaling.

Abstract: Techniques for establishing a network connection via a physical medium after exiting a low-power state. The technique includes receiving circuit configuration information for configuring a circuit for establishing a network connection via a physical medium. The technique also includes determining first redundancy information based on the circuit configuration information. The technique also includes storing the determined first redundancy information and the circuit configuration information. The technique also includes entering, by the circuit, a low-power state, and exiting the low-power state. The technique also includes determining second redundancy information based on the stored circuit configuration information after the circuit has exited the low-power state. The technique also includes comparing the second redundancy information to the first redundancy information. The technique also includes detecting an error based on the comparing.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate determining a state of a qubit are described. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an output receiving component that can receive, in response to a request, output representative of a quantum state of a qubit of a quantum computing device, and a classifying component that classifies the quantum state of the qubit of the quantum computing device based on the output representative of the quantum state of the qubit. The system can further include a configuring component that can configure the classifying component based on a characteristic of the request.

Abstract: An entangled quantum cache includes a quantum store that receives a plurality of quantum states and is configured to store and order the plurality of quantum states and to provide select ones of the stored and ordered plurality of quantum states to a quantum data output at a first desired time. A fidelity system is configured to determine a fidelity of at least some of the plurality of quantum states. A classical store is coupled to the fidelity system and configured to store classical data comprising the determined fidelity information and an index that associates particular ones of classical data with particular ones of the plurality of quantum states and to supply at least some of the classical data to a classical data output at a second desired time. A processor is connected to the classical store and determines the first time based on the index.

Abstract: A processor system comprises a plurality of processing elements. Each processing element includes a corresponding convolution processor unit configured to perform a portion of a groupwise convolution. The corresponding convolution processor unit determines multiplication results by multiplying each data element of a portion of data elements in a convolution data matrix with a corresponding data element in a corresponding groupwise convolution weight matrix. The portion of data elements in the convolution data matrix that are multiplied belong to different channels and different groups. For each specific channel of the different channels, the corresponding convolution processor unit sums together at least some of the multiplication results belonging to the same specific channel to determine a corresponding channel convolution result data element.

Abstract: A processor system comprises two groups of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate matrix for each channel. Each register stores at least one data element from each matrix. The hardware channel convolution processor unit is configured to multiply each data element in a first and second portion of the first group of registers with a corresponding data element in the second group of registers to determine corresponding multiplication results and sum together the multiplication results for each specific channel to determine two corresponding channel convolution result data elements in a corresponding channel convolution result matrix.

Abstract: A data processing device includes a plurality of variable nodes configured to receive and store a plurality of target bits; a plurality of check nodes each configured to receive stored target bits from one or more corresponding variable nodes of the plurality of variable nodes, check whether received target bits have an error bit, and transmit a check result to the corresponding variable nodes; and a group state value manager configured to determine group state values of variable node groups into which the plurality of variable nodes are grouped.

Abstract: A memory controller to control a memory module includes an error correction code (ECC) engine, a central processing unit to control the ECC engine and an error managing circuit. The ECC engine performs an ECC decoding on a read codeword set from the memory module to generate a first syndrome and a second syndrome in a read operation, corrects correctable error in a user data set based on the first syndrome and the second syndrome and provides the error management circuit with the second syndrome associated with the correctable error. The error managing circuit counts error addresses associated with correctable errors detected through read operations, stores second syndromes associated with the correctable errors by accumulating the second syndromes, determines attribute of the correctable errors based on the counting and the accumulated second syndromes, and determine an error management policy on a memory region associated with the correctable errors.

Abstract: An optical mechanism and an optical system for optical-medium storage. The mechanism includes an optical-medium storage device, and an optical-medium transmission device. The optical-medium storage device is provided with an optical-medium storage module, configured to store an optical medium, and an optical-medium input-output end, configured to receive and transmit the optical medium to the optical-medium storage module and read data from the optical-medium storage module. The optical-medium receiving module is configured to receive the optical medium transmitted from outside and transmit the optical medium to the optical-medium storage module via the optical-medium input-output end, according to a receiving instruction. The optical-medium storing module is configured to form a storage path for the optical medium with the optical-medium storage module.

Abstract: The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.

Abstract: A memory controller and a storage device including the same are provided. The memory controller performs decoding by selecting a decoder of a level enough to correct bit errors in a codeword from among a plurality of error correction code (ECC) decoders based on a bit error history of a non-volatile memory device.

Abstract: Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

Abstract: Computer systems and methods for constructing a model of the noise afflicting a quantum computer comprising a plurality of qubits are provided. A graph G that describes a conditional independence structure of the noise is obtained. The graph G includes a node for each qubit in the plurality of qubits. The noise afflicting the quantum computer is logically reduced to Pauli noise. The graph G is broken into a plurality of sets. Each respective set Cj in the plurality of sets (i) corresponds a respective qubit j in the plurality of qubits and (ii) comprises a representation of the respective qubit j and the parent qubits ?+j in the graph G. For each respective set Cj in the plurality of sets, a corresponding local conditional probability distribution Pr(ej|e?+j) is characterized in which ej?j is a Pauli error on the jth qubit.

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.

Abstract: An error correction device includes a first correction unit which performs error correction decoding of data by a repetitive operation, having a full operation state in which the error correction decoding is repeated until convergence is obtained and a save operation state in which the number of times of the repetitive operation is restricted to a predetermined number. An error information estimation unit estimates an input error rate or an output error rate of the first correction unit using a decoding result of the first correction unit, and a control unit which controls transition between the full operation state and the save operation state based on at least one piece of information of the input error rate, the output error rate, and an operation time of the first correction unit. It is thus possible to provide an error correction device that can improve a transmission characteristic while suppressing power consumption.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t?2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system may transmit, to a host, target data, and, upon receiving, from the host, information indicating that at least one bit-flip has occurred in the target data, may perform an error handling operation on the at least one bit-flip in the target data. Accordingly, the memory system is able to reduce resource used in checking the bit-flip and to alleviate the constraints of the algorithms used in checking for the bit-flip.

Abstract: A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix.

Abstract: A method of transmitting a message includes, for each data block, generating a root matrix using a generator, generating a quasi-cyclic matrix H using the root matrix, encoding the block using H to create a codeword, and transmitting the codeword. The root matrix includes three submatrices: an identity matrix in an upper-left-hand portion of the root matrix, an identity matrix in a lower-left-hand portion of the root matrix, and a circulant matrix in a right-hand portion of the root matrix. The circulant matrix equals the sum of an identity matrix and an identity matrix with rows shifted once to the right. Generating H includes expanding the root matrix by replacing 0 elements in the root matrix by a square matrix of 0 elements and replacing 1 elements in the root matrix by a shifted diagonal matrix. Non-zero elements of the diagonal matrix are selected from GF(q) based on the generator.

Abstract: A memory controller performs an error recovery operation. The controller performs a read operation on a select block using a select read level; decodes data associated with the read operation to generate a syndrome value; determines whether to stop, before a maximum number of iterations, the read operation and the decoding at the select read level, using the syndrome value; when it is determined to stop the read operation and the decoding at the select read level, selects a next read level in a sequence of read levels; and uses the next read level for a subsequent read operation.

Abstract: A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Abstract: Aspects of the subject technology relate to electronic device display circuitry and methods of operating the display. The display circuitry a panel driver interface that decodes digital display data, for each display frame, received from host circuitry of the electronic device. The digital display data includes error correction and detection information for frame and line configuration information distributed in a frame packet and multiple line packets for each display frame. The frame and line configuration information facilitates, efficient, low-error, digital control of various display operational features.

Abstract: An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.

Abstract: An error correction circuit includes a syndrome calculator to calculate syndrome information of input data, an error position calculator to calculate error position information of the input data, a holder to hold the syndrome information or the error position information at a predetermined timing, an input switch to select one of error-corrected data of the input data, and the input data, and to input the selected data to the syndrome calculator, an error detection determiner to determine whether an error of the input data has been correctly detected, and an error corrector to correct the error of the input data based on information held by the holder and to output error-corrected input data when it is determined by the error detection determiner that the error has been correctly detected whereas to output the input data with no error correction when it is determined by the error detection determiner.

Abstract: A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.

Abstract: Described herein is an error correction circuit that includes a syndrome check history manager configured to maintain a history of syndrome checks corresponding to one or more iterations of the iterative decoding scheme. The error correction circuit also includes a trapping set detector configured to compare a trapping set determination policy with the history of syndrome checks to determine whether the history of syndrome checks meets criteria of the trapping set determination policy, while error correction decoding is performed, and determine that a trapping set exists when the history of syndrome checks satisfies the trapping set determination policy. The trapping set determination policy is related to at least one of a change in a syndrome vector, a number of UCNs, and a change in the number of UCNs.

Abstract: A device that includes a node engine configured to determine a core distance for a correlithm object core. The core distance identifies a maximum number of hops away from a root correlithm object. The node engine is further configured to select a correlithm object in an n-dimensional space and set the selected correlithm object as the root correlithm object. The node engine is further configured to identify a plurality of correlithm objects within the core distance from the root correlithm object and link the identified plurality of correlithm objects with the root correlithm object to generate the correlithm object core.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

Abstract: An apparatus includes an interface and a decoder. The interface is configured to receive a code word, produced in accordance with an Error Correction Code (ECC) represented by a set of parity check equations. The code word includes a data part and a redundancy part, and contains one or more errors. The decoder is configured to hold a definition of a partial subgroup of the parity check equations that, when satisfied, indicate that the data part is error-free with a likelihood of at least a predefined threshold, to decode the code word by performing an iterative decoding process on the parity check equations, so as to correct the errors, and during the iterative decoding process, to estimate whether the data part is error-free based only on the partial subgroup of the parity check equations, and if the data part is estimated to be error-free, terminate the iterative decoding process.

Abstract: A device that includes a node engine configured to determine a core distance for a correlithm object core. The node engine is further configured to select a correlithm object in an n-dimensional space and set the selected correlithm object as the root correlithm object. The node engine is further configured to identify a plurality of correlithm objects within the core distance from the root correlithm object and determine one or more correlithm objects from among the identified plurality of correlithm objects is within a core distance of a second root correlithm object. The node engine is further configured to reduce the core distance for the correlithm object core, identify a second plurality of correlithm objects within the reduced core distance from the root correlithm object, and link the second identified plurality of correlithm objects with the root correlithm object to generate the correlithm object core.

Abstract: A device that includes a node engine configured to determine a core distance for a correlithm object core. The node engine is further configured to select a first correlithm object in an n-dimensional space and set the first correlithm object as the root correlithm object. The node engine is further configured to receive a second correlithm object and determine the distance between the root correlithm object and the second correlithm object. The node engine is further configured to determine whether the distance between the root correlithm object and the second correlithm object is less than core distance for the correlithm object core. The node engine is further configured to identify the second correlithm object as a member of the correlithm object core in response to determining the distance between the root correlithm object and the second correlithm object is less than core distance for the correlithm object core.

Abstract: A device that includes a node engine configured to define a number of child correlithm objects for a string correlithm object. The node engine is further configured to select a correlithm object from an n-dimensional space and set the selected correlithm object as a parent correlithm object. The node engine is further configured to iteratively identify the defined number of child correlithm objects, where identifying the defined number of child correlithm objects involves randomly selecting correlithm objects less than the standard distance away from the parent correlithm object and defining the selected correlithm objects as a child correlithm object. The node engine is further configured to link the defined child correlithm objects with the parent correlithm object in the node table to generate the string correlithm object.

Abstract: A device that includes a node engine configured to define a number of child correlithm objects for a string correlithm object. The node engine is further configured to set a starting correlithm object as a first parent correlithm object and set an ending correlithm object as a second parent correlithm object. The node engine is further configured to randomly select a correlithm object less than the standard distance away from the first parent correlithm object, define the selected correlithm object as a child correlithm object, and link the child correlithm objects with the first parent correlithm object. The node engine is further configured to randomly select a correlithm object less than the standard distance away from the second parent correlithm object, define the selected correlithm object as a child correlithm object, and link the child correlithm objects with the second parent correlithm object.

Abstract: Enhanced error correction for data stored in storage devices are presented herein. A storage controller retrieves an initial encoded data segment stored on a storage media, computes information relating to errors resultant from decoding the initial encoded data segment, and stores the information in a cache. The storage controller retrieves subsequent encoded data segments stored on the storage media, augments a decoder using at least the information retrieved from the cache, and decodes the subsequent encoded data with the decoder to produce resultant data.

Abstract: A method for generating a signal includes: encoding, by an active stylus, transmission information into n-bit q-ary codes; performing, by the active stylus, frequency modulation on the n-bit q-ary codes, respectively, to generate a plurality of encoded frequency-modulated signals; and combining, by the active stylus, a preset fixed-frequency signal for detecting a stylus tip position with the plurality of encoded frequency-modulated signals to form an encoded signal. A method for analyzing a signal, an active stylus, and a touchscreen are also provided. The method for generating a signal, the method for analyzing a signal, the active stylus, and the touchscreen transmit more coding information within a relatively short time, thereby solving a problem of low efficiency of information transmission between an active stylus and a touch screen.

Abstract: Methods and apparatus disclosed herein may be used to establish framing more efficiently in communication protocols with block-coded forward error correction. Such protocols generally involve the check of different bit-alignments searching for positions that yield zero syndromes. The search can be undesirably slow, particularly in the presence of received errors. The presently-disclosed bit-alignment testing technique reduces this search time by checking the syndrome at each data word as if that data word was the last of a code. In other words, the word positions are effectively checked without a prior assumption as to which words are the first and last of the code. This reduces the task to the number of different bit-alignments possible within a single data word, rather than the number of bit-alignments possible in a complete FEC code. In one implementation, the lock time is reduced by approximately 50 times when compared to a straightforward solution.