Abstract: Systems and methods for managing and repairing errors occurring on a plurality of servers in an automated server build process is provided. Systems may include a first error code from a plurality of error codes. The first error code may be associated with a failure. The system may further include a plurality of sets of action codes. When the failure occurs on a server, included in the plurality of servers, during the server build process, the system may be configured to receive an error code from the server that may correspond to the failure and check the error code against previously recorded error codes recorded on an error code table. When the error code is included in the error code table, the system may retrieve the corresponding action code, assign the action code to the failure and execute the action code on the server.

Abstract: A switching circuit includes: a main switch array including multiple main switch elements respectively arranged on multiple main signal paths configured in a parallel connection, wherein the multiple main signal paths are coupled with a first circuit node; a main switch control circuit for controlling the multiple main switch elements; an auxiliary switch array including multiple auxiliary switch elements respectively arranged on multiple auxiliary signal paths configured in a parallel connection, wherein the multiple auxiliary signal paths are also coupled with the first circuit node; and an auxiliary switch control circuit for controlling the multiple auxiliary switch elements so as to maintain a total number of turned-on switch elements in the main switch array and the auxiliary switch array to be equal to or more than a threshold quantity.

Abstract: A decoder includes a syndrome calculator, a Key Equation Solver (KES) and an error corrector. The syndrome calculator receives an n-symbol code word encoded using a Reed Solomon (RS) code to include (n?k) redundancy symbols, calculates for the code word 2t syndromes Si, t=(n?k)/2 is a maximal number of correctable erroneous symbols. The KES derives an error locator polynomial {circumflex over (?)}(x) whose roots identify locations of erroneous symbols, by applying to the syndromes a number of t iterations. In each iteration the KES calculates two discrepancies between {circumflex over (?)}(x) and respective two candidates of {circumflex over (?)}(x), and derives from the two candidates an updated candidate of {circumflex over (?)}(x). The error corrector recovers the code word by correcting the erroneous symbols using the derived error locator polynomial {circumflex over (?)}(x).

Abstract: Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.

Abstract: A controller including: an initialization unit initializing values and states of variable nodes and initializing values of check nodes; a variable node update unit updating the values and states of the variable nodes; a check node update unit updating the values of the check nodes based on the updated values and states of the variable nodes; and a syndrome check unit deciding iteration of the operation of the variable node update unit and the check node update unit when the values of the check nodes are not all in a satisfied state, the variable node update unit calculates reliability values of the variable nodes and a reference flip value based on a result of a previous iteration, and the variable node update unit updates the values and states of the variable nodes based on the reference flip value and the reliability values and states of the variable nodes.

Abstract: Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.

Abstract: The invention relates to a device, in particular a router, for bundling a plurality of Internet access lines into a virtual Internet access line for the purpose of providing the sum of the bandwidths of the plurality of Internet access lines for a transmission of data via the virtual Internet access line, wherein the device divides a data packet to be transmitted among a plurality of data packets for separate transmission via the plurality of Internet access lines, wherein the device is designed to calculate redundancy information and to transmit said redundancy information along, from which redundancy information lost data packets can be restored, such that packet losses on an Internet access line do not lead to packet losses on the bundled virtual line.

Abstract: Systems and methods for performing a parity check on encoded data are disclosed. Encoded data is received. A parity check is performed based on a parity check matrix. In response to determining the first parity check is successful, a parity check number is incremented. Additional parity checks are selectively performed on subsequent portions of the array based on comparing the incremented parity check number to a threshold.

Abstract: An integrated circuit (IC) includes an encoder configured to receive input data including a plurality of data bits. The encoder includes a parity computation matrix circuit configured to arrange the data bits according to a matrix format to generate a parity computation matrix. A parity computation circuit is configured to compute a plurality of parity computation row terms corresponding to rows of the parity computation matrix respectively, compute a plurality of parity computation column terms corresponding to columns of the parity computation matrix respectively, and compute parity bits using the parity computation row terms and parity computation column terms. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory cell array in a memory.

Abstract: In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.

Abstract: Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Abstract: Techniques for decoding potentially corrupted Reed-Solomon encoded messages are provided. To decode a message, an incoming message is classified into a group based on which symbols of the message have survived (a “survival pattern”). The same inversion matrix may be used for each survival pattern associated with a single group. This reduces the amount of work required and data that is to be stored in order to perform the matrix multiplication that decodes the message.

Abstract: An example method of erasure error correction in an IC includes receiving input data from a channel coupled to the IC, determining a bit pattern indicating survived blocks and erased blocks of a plurality of blocks in the input data and determining a number of integers, in a finite set of integers, greater than or less than an integer representing the bit pattern, the finite set of integers representing a finite set of possible values of the bit pattern based on an (m, k) erasure coding scheme. The method further includes generating an address for a memory, which stores a plurality of pre-computed decoding matrices based on the (m, k) erasure coding scheme, from the determined number of integers to obtain a pre-computed decoding matrix associated with the bit pattern. The method further includes recovering the erased blocks through matrix multiplication using the pre-computed decoding matrix and the survived blocks as parametric input.

Abstract: A device, method, and computer-readable medium for correcting at least one error in readings of electricity meters, the method including receiving first readings of regular meters measuring electric energy delivered in each of a group of cables fed from a same distribution node in an electric grid during a period of time, receiving second readings of check meters measuring electric energy delivered in each of combinations of cables in the group of cables during the period of time, the combinations of cables being formed based on a redundant matrix in a generator matrix of a linear systematic block code, and correcting, in response to determining that at least one error been detected, the at least one error in the first readings of the regular meters and the second readings of the check meters.

Abstract: A device, method, and computer-readable medium for correcting at least one error in readings of electricity meters, the method including receiving first readings of regular meters measuring electric energy delivered in each of a group of cables fed from a same distribution node in an electric grid during a period of time, receiving second readings of check meters measuring electric energy delivered in each of combinations of cables in the group of cables during the period of time, the combinations of cables being formed based on a redundant matrix in a generator matrix of a linear systematic block code, and correcting, in response to determining that at least one error been detected, the at least one error in the first readings of the regular meters and the second readings of the check meters.

Abstract: An apparatus for data coding includes an encoder and a decoder. The encoder is configured to receive input data including one or more m-bit data groups that are associated with respective group indices, to generate a code word that includes the input data and an m-bit redundancy that depends on the data groups and on the respective group indices, and to send the code word over a channel. The decoder is connected to the channel and is configured to produce a syndrome that equals zero when the code word is error-free, and when the code word contains a single error caused by the channel, is indicative of an erroneous group in which the single error occurred, and of a location of the single error within the erroneous group, and to recover the input data by correcting the single error at the location in the erroneous group.

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

Abstract: A decoder includes syndrome storage and a first barrel shifter configured to bit-shift hard decision bit data to generate shifted data that is aligned with a set of syndromes from the syndrome storage. The decoder also includes a first syndrome update circuit coupled to the first barrel shifter and configured to process the set of syndromes based on the shifted data to generate an updated version of the set of syndromes. The decoder may also be configured to perform on-the-fly syndrome weight computation.

Abstract: A device, method, and computer-readable medium for correcting at least one error in readings of electricity meters, the method including receiving first readings of regular meters measuring electric energy delivered in each of a group of cables fed from a same distribution node in an electric grid during a period of time, receiving second readings of check meters measuring electric energy delivered in each of combinations of cables in the group of cables during the period of time, the combinations of cables being formed based on a redundant matrix in a generator matrix of a linear systematic block code, and correcting, in response to determining that at least one error been detected, the at least one error in the first readings of the regular meters and the second readings of the check meters.

Abstract: A method for detecting a data bit inversion (DBI) error in a memory system is disclosed. The method and system comprise calculating an error correcting code (ECC) from each of the 8 beats of a burst of data such that no more than one bit per byte is included in each ECC calculation. The method and system further include determining if there is an inversion of one byte in the burst.

Abstract: The present invention provides systems and methods to detect when hard decisions change for bit nodes of one or more layers of a layered LDPC decoder and to update accumulated partial syndrome calculations for those layers. As hard decisions of bit nodes are generated, they are compared with their previous values. If the hard decisions change, partial syndrome calculations are accumulated and updated for the layers having non-zero elements in one or more columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions. If the hard decisions for the bit nodes are unchanged, the partial syndrome calculations for the corresponding layers are not updated. Changes to hard decisions of codewords are tracked and partial syndromes are flipped for the layers of the columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions.

Abstract: The present technique relates to an information processing apparatus and a method, and a program, capable of reducing a delay time.

Abstract: A packet analyzer device and method are described herein that measure a video quality of IP multicast media. In one embodiment, the packet analyzer device and method measure a video quality of transmitted IP multicast media when the transmission of the IP multicast media involves the use of Forward Error Correction (FEC) in accordance with the FLUTE protocol.

Abstract: A block of data is partitioned into a plurality of sub-blocks each including a logical array having rows and columns of data symbols, encoded using a row linear block code and a column linear block code. Each product codeword includes a logical array of code symbols having rows which include respective row codewords and columns which include respective column codewords. The product codewords are encoded by encoding groups of L symbols, using a rate-L/(L+M) linear block code to produce a plurality of (L+M)-symbol codewords which are logically arranged in nQ encoded blocks (where n is an integer greater than zero). Each of the nQ encoded blocks includes an array having rows and columns of code symbols in which each column includes a codeword of the column code.

Abstract: A data storage device includes a memory and a decoder. In one embodiment, the decoder includes a bit-flipping stage and a second decoding stage. The decoder is configured to receive data from the memory and to process the received data at the bit-flipping stage to generate first stage result data. The data corresponds to an error correction coding (ECC) codeword of an ECC code. The data is processed at the bit-flipping stage based on parity checks of the error correction code (ECC) code that are not satisfied by the data. The data is processed at the bit-flipping stage without first attempting to decode the received data at the second decoding stage. The decoder is further configured to provide the first stage result data to an input of the second decoding stage and to initiate decoding at the second decoding stage at least partially based on the first stage result data.

Abstract: A block of data is partitioned into a plurality of sub-blocks each including a logical array having rows and columns of data symbols, encoded using a row linear block code and a column linear block code. Each product codeword includes a logical array of code symbols having rows which include respective row codewords and columns which include respective column codewords. The product codewords are encoded by encoding groups of L symbols, using a rate-L/(L+M) linear block code to produce a plurality of (L+M)-symbol codewords which are logically arranged in nQ encoded blocks (where n is an integer greater than zero). Each of the nQ encoded blocks includes an array having rows and columns of code symbols in which each column includes a codeword of the column code.

Abstract: Provided is an apparatus for designing a quantum code, which includes an analyzing unit for analyzing at least one quantum error generated in a quantum error channel as at least one binary error by using a standard form codeword stabilized quantum (CWS) code, a code generating unit for generating a binary error-correcting code which corrects the at least one binary error, a word operator generating unit for generating at least one word operator of the CWS code by using the at least one binary error-correcting code, and a codeword generating unit for generating at least one codeword including at least one entangled qubit (ebit) by using the at least one word operator.

Abstract: A hard input low density parity check decoder is provided that shares logic between a bit-flipping decoder and a syndrome calculator. The hard-decision decoder decodes one or more error-correcting (EC) codewords and comprises a bit-flipping decoder that flips one or more bit nodes connected to one or more unsatisfied parity checks; and a syndrome calculator that performs a parity check to determine whether the bit-flipping decoder has converged on a valid codeword, wherein the bit-flipping decoder and the syndrome calculator share one or more logic elements. The decoder optionally includes means for updating a parity check equation of each flipped bit. Error-correcting (EC) codewords are decoded by flipping one or more bit nodes connected to one or more unsatisfied parity checks; and updating one or more parity check equations associated with the one or more bit nodes each time the one or more bit nodes are flipped. The parity check equations are updated whenever a bit is updated.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: Apparatuses and methods associated with instant syndrome computation in a layered LDPC decoder are described. In one embodiment an apparatus includes a first hardware layer configured to compute a first group of syndrome values from one or more bit values in the codeword and a second hardware layer configured to compute a second group of syndrome values from one or more bit values in the codeword. The apparatus also includes a first physical memory associated with the first hardware layer and configured to store the first group of syndrome values until the syndrome values change due to a change in a codeword bit value. The apparatus also includes a second physical memory associated with the second hardware layer and configured to store the second group of syndrome values until the syndrome values change due to a change in a codeword bit value.

Abstract: Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.

Abstract: Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method.

Abstract: Provided is an error check and correction (ECC) circuit which includes a Chien search unit configured to determine whether there is an error in a data string. The Chien search unit includes a circuit configured to calculate a first bit string by multiplying a plurality of elements of Galois Field GF(2n) and a value of (n-k)-bit, and calculate a second bit string by multiplying the plurality of elements and a value of k-bit; and a plurality of Chien search circuits configured to combine the first bit string and the second bit string to calculate the arbitrary element. The plurality of Chien search circuits are arranged in a matrix along a row direction and a column direction. The first bit string is provided in the row direction or the column direction, and the second bit string is provided in a direction different from the direction of the first bit string.

Abstract: A beacon signal may be provided with data extensions. The data extensions permit additional information to be provided by the beacon signal, thereby reducing the traffic overhead of the network. The data extensions further permit handoffs and handoffs based on offset values. A Measurement Request field corresponding to a beacon request contains a measurement duration value and channel number for which the request applies. The beacon request permits a scan mode. In Active Scan mode, the measuring station (STA) transmits a probe request with a broadcast SSID. In Passive Scan mode, the measuring STA passively receives on the specified channel and return a beacon report containing one information element for each STA from which it detects a beacon or probe response. In Beacon Table mode, the measuring STA returns a beacon report containing the current contents of its beacon table without performing additional measurements.

Abstract: Techniques for optimizing data storage are disclosed herein. In particular, methods and systems for implementing redundancy encoding schemes with data storage systems are described. The redundancy encoding schemes may be scheduled according to system and data characteristics. The schemes may span multiple tiers or layers of a storage system. The schemes may be generated, for example, in accordance with a transaction rate requirement, a data durability requirement or in the context of the age of the stored data. The schemes may be designed to rectify entropy-related effects upon data storage. The schemes may include one or more erasure codes or erasure coding schemes. Additionally, methods and systems for improving and/or accounting for failure correlation of various components of the storage system, including that of storage devices such as hard disk drives, are described.

Abstract: Various systems and methods for media defect detection.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for perturbing soft data in a layered decoder system.

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: An error check and correction circuit includes a Chien search unit. The Chien search unit includes a calculation circuit and a plurality of Chien search circuits. The calculation circuit is configured to calculate a first bit stream by multiplying a value of (n?k) bits by a plurality of elements and a second bit stream by multiplying a value of k bits by the plurality of elements. The plurality of Chien search circuits configured to calculate the element by connecting the first bit stream and the second bit stream, and substitute the calculated element into the error correction search equation.

Abstract: A method begins by a dispersed storage (DS) processing module determining whether to send an encoded data slice of set of encoded data slices in accordance with a zero information gain (ZIG) format. When the encoded data slice is to be sent in accordance with the ZIG format, the method continues with the DS processing module selecting a partial encoding threshold number of encoded data slices of the set of encoded data slices, wherein the partial encoding threshold number of encoded data slices does not include the encoded data slice and generating a set of ZIG encoded data slices based on a ZIG function and the partial encoding threshold number of encoded data slices, wherein the set of ZIG encoded data slices represents recovery information of the encoded data slice. The method continues with the DS processing module outputting the set of ZIG encoded data slices.

Abstract: A data storage device includes a memory die, where the memory die includes a NAND flash memory and a resistive random access memory (ReRAM). The memory die also includes an interface coupled to the ReRAM and the NAND flash memory. The interface is configured to support on-chip copying of data between the NAND flash memory and the ReRAM.

Abstract: According to an embodiment, an error correction device includes first calculators, second calculators, estimators, and an inverter. Each first calculator calculates a first message representing a probability that 1-bit data that is input in a corresponding variable node is 1. Each second calculator calculates a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first messages of the variable nodes connected to the check node. Each estimator estimates a true value of the data input to the variable node to generate an estimated value by using the first and second messages. The inverter inverts the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1.

Abstract: The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

Abstract: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the 5 transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Abstract: The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.

Abstract: In an arrangement of the disclosed systems, devices, and methods, a codeword encoded with a first number of check symbols is received and asymmetrically processed according to a second number of check symbols, where the second number of check symbols is less than the first number of check symbols, to produce an error locator polynomial and an error evaluator polynomial. A derivative of the error locator polynomial is produced by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant. The derivative of the error locator polynomial is produced using a variable finite-field multiplier and without use of a divider.