Abstract: The coding apparatus, coding processing target sequence forming method and Viterbi decoding apparatus of the present invention can realize low delay processing with a minimum number of repetitive processing and suppress the degradation of the accuracy of decoding at the ends of a decoded sequence due to truncation error. In the coding apparatus mounted on the transmitting apparatus (100), a control information rearranging section (130) receives as input a control information sequence, in which a plurality of control information blocks are arranged in a predetermined order, and forms a coding processing target sequence by rearranging the order of the plurality of control information blocks to form an assembled sequence grouping control information blocks comprised of predictable bit sequences in the plurality of control information blocks, and to allocate the assembled sequence to a predetermined position in the control information sequence.

Abstract: A method for decoding a word received at a current time instant into a symbol of a trellis code. The trellis code corresponds to a trellis diagram having N states associated with the current time instant. Each of the N states corresponds to at least one incoming branch. Each of the incoming branches is associated with a symbol of the trellis code. The branch metrics are computed for the incoming branches such that a branch metric represents a distance between the received word and a symbol associated with the corresponding branch. The branch metric is represented by fewer bits than a squared Euclidian metric representation of the distance. For each of the N states, a node metric is computed based on corresponding branch metrics and one of the incoming branches associated with the state is selected. One of the N states is selected as an optimal state based on the node metrics. The symbol associated with the selected incoming branch corresponding to the optimal state is the decoded word.

Abstract: A system and method enable the fast decoding of a front end of data (e.g., a header) that is convolutionally encoded by treating the front end as a block code. The system and method receive the convolutionally encoded data; extract a finite sized block from the data; and decode the extracted block using a block error correction decoding method. A Viterbi decoder can then be used to decode the remainder of the encoded data based on the decoded block.

Abstract: A decoder decodes a code by selecting, based on a predetermined condition, a path out of paths representing a transition of each of states in a trellis diagram. A storing unit stores, when a path at time k is selected, information on a selection history of a path selected at time prior to time (k?(a constraint length of a code)+1). A path detecting unit detects a path to be excluded from a path selection candidate, based on the information stored in the storing unit and information on a state of a transition source when a state transition occurs from time k?1 to time k.

Abstract: A method for estimating the speed of a mobile device in a network is provided that includes selecting a correlation length from a plurality of possible correlation lengths. A correlation result is generated based on the selected correlation length. A speed estimate is generated for the mobile device based on the correlation result.

Abstract: This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.

Abstract: A Viterbi decoder includes a computing device, a memory and a bus. The computing device receives sets of data values and calculates distances for the received sets of data values, accumulates and compares the calculated distances according to a Viterbi algorithm, decides data values and generates control signals dependent on a plurality of decisions associated with a plurality of paths. The memory stores the decided data values and provides at least one output value. The bus connects the computing device and the memory and is configured to convey the control signals to the path memory. The computing device or the memory shifts data strings in the memory according to conditions of the Viterbi algorithm with the control signals associated with the plurality of paths.

Abstract: A vestigial sideband (VSB) modulation transmission system and a method for encoding an input signal in the system are disclosed. According to the present invention, the VSB transmission system includes a convolutional encoder for encoding an input signal, a trellis-coded modulation (TCM) encoder for encoding the convolutionally encoded signal, and a signal mapper mapping the trellis-coded signal to generate a corresponding output signal. Different types of the convolutional encoders are explored, and the experimental results showing the performances of the VSB systems incorporating each type of encoders reveals that a reliable data transmission can be achieved even at a lower input signal to noise ratio when a convolutional encoder is used as an error-correcting encoder in a VSB system.

Abstract: A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked storage stages.

Abstract: A communication device comprising an ML-APP detector coupled to at least two antennas. The ML-APP detector comprises at least one Hx unit coupled to at least one LLR unit. The Hx unit generates a portion of all possible symbols that can be received and transfers each generated symbol candidate to the LLR unit which performs a conversion operation on the transferred symbol candidate to generate another symbol candidate that is not part of the special portion. In this manner all of the possible symbol candidates are obtained by the LLR unit. The LLR unit compares the symbol candidates to a received symbol to perform a cost calculation. The symbol candidate yielding the lowest cost from the cost calculations of all possible symbol candidates is selected as the best candidate. APP decoding is then performed on the selected candidate using soft information associated with the selected candidate which soft information is generated by the LLR unit.

Abstract: A method and apparatus for performing channel compensation and symbol demodulation using an estimated channel impulse response during coherent demodulation of a received Orthogonal Frequency Division Multiplexing (OFDM) signal are provided. In the apparatus, an FFT processor IFFT-processes a received signal. A channel compensator generates a channel-compensated signal by multiplying the FFT received signal by an estimated channel impulse response and calculates the power of the estimated channel impulse response. A symbol demodulator sets the power of the estimated channel impulse response as a reference point defining a minimum distance between signal points in a signal constellation, and decides soft metric values for channel decoding using the reference point and I-channel and Q-channel signal components of the channel-compensated signal. A decoder recovers information bits by decoding the soft metric values.

Abstract: The invention relates to a maximum likelihood decoding device that performs Partial Response Maximum Likelihood decoding on a reproduced data signal from a recording media or another source. The device includes a Viterbi detector that performs bit detection from the reproduced signal. The Viterbi device can have variable setting for branch metric calculations based on the reference levels in the reproduced signal. The device measures and attempts to reduce the Euclidean distance between a maximum likelihood path selected by the Viterbi detector and a second path.

Abstract: This invention modifies Viterbi decoding to improve BER. Within the state metric unit cascade block, this invention forces the unused ACS units decision bits to a 0 for the top rail and a 1 for the bottom rail. This invention modifies the final maximum state index with the selected decision bits from the unused ACS units. This invention uses the modified final maximum state index as the initial conditions for the k?1 traceback shift register. This invention also uses the final maximum state index to mask the generated pretraceback decision bits generated from the last block of ACS units.

Abstract: A Viterbi decoding apparatus and a method thereof are disclosed. According to each partial surviving path formed by the decision information of every k continuous symbols of a symbol sequence, the apparatus can write its start trellis state and corresponding partial decoded information into a memory unit. On the other hand, the apparatus performs traceback reads and decode reads according to the content of the memory unit, thereby decoding a decoded information sequence corresponding to the symbol sequence. In this manner, memory space can be saved and the operating speed for traceback/decode reads need no acceleration. Thus, hardware cost and design complexity can be reduced simultaneously.

Abstract: A data communication system has a plurality of communication transceivers respectively coupled to a plurality of communication lines and is configured to receive payload symbols and parity symbols. The system further has logic configured to transition from non-erasure decoding to erasure decoding based on a measured communication performance of one of the communication lines coupled to one of the plurality of transceivers.

Abstract: Disclosed is a decoding apparatus for decoding an encoded signal on the basis of a plurality of state-transition trellises having differing state counts. The decoding apparatus includes a decoding section for decoding the encoded signal on the basis of a first state-transition trellis, and a mode selection section for selecting either a first operating mode based on the first state-transition trellis or a second operating mode based on a second state-transition trellis. The second state-transition trellis has a state count smaller than that of the first state-transition trellis. If the mode selection section selects the second operating mode, the decoding section decodes the encoded signal by carrying out a state transition switch from a first state transition to a second state transition.

Abstract: A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an input signal for a next stage functional block; a multiplexer (209) that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and a check logic (210) that generates said check data by calculating one of said plurality of data outputted from said multiplexer.

Abstract: A turbo decoder and a decoding method are disclosed, which use a Maximum A Posteriori (MAP) algorithm in order to perform iterative decoding. The method has the steps of sequentially receiving input data in a memory having a predetermined window size and performing a forward metric calculation for the input data so that the input data has a four window size, performing a first backward metric calculation for the input data and outputting first valid data when the data are input to the memory by twice the window size, and performing a second backward metric calculation for the input data and outputting second valid data when the data are input to the memory by three times the window size.

Abstract: A decoding device according to the one embodiment of the invention includes: a first decoder performing a first decoding based on first encoded data obtained by encoding unencoded data, and second soft-output data to generate first soft-output data; a second decoder performing a second decoding based on second encoded data obtained by interleaving the unencoded data and encoding the interleaved data, and the first soft-output data to generate the second soft-output data; and a hard decision part outputting decoded data through hard decision on the first soft-output data.

Abstract: Rate control adaptable communications. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single decoder is operable to decode each of the various rates at which the data is encoded by the encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on a variety of operational parameters including operating conditions of the communication system, a change in signal to noise ratio (SNR), etc.

Abstract: In an apparatus for recording and regenerating data, a pass metric is calculated based on a likelihood converted from a previous calculation result iteratively until all pass metrics of the same data recorded many times on a recording medium are calculated, and then data recorded on the recording medium is decoded.

Abstract: A Viterbi decoder for executing a trace-back work in parallel and a decoding method.

Abstract: Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability values using a second add-compare select unit, wherein the first and second add-compare select units process the branch metrics determined by the branch metrics unit. The first and second add-compare select units can optionally process branch metrics having a different number of bits.

Abstract: A receiver baseband processor comprises a channel estimator that generates a channel estimate from the received symbol. A phase demodulator selectively rotates the phase of the received symbol based on the channel estimate. A Viterbi decoder generates a plurality of branch metrics based on the channel estimate and selectively phase rotated received symbol and estimates a clean symbol based on the plurality of branch metrics.

Abstract: A circuit is disclosed that is designed to carry out add compare select operations for determination of state metrics. The circuit is also designed to carry out a computation operation which goes beyond an add compare select operation for state metric determination, wherein the circuit is either configurable for this purpose and/or has an output for emitting at least one circuit-internal variable which goes beyond the output variable from the add compare select operation.

Abstract: Certain embodiments provide methods and apparatus for decoding a string of data bits, encoded with a turbo encoding scheme, in a wireless communication system. One or more a-priori bit values corresponding to expected bit values at one or more identified bit locations in the string of data bits may be identified. One or more branch metrics used in a turbo decoding scheme may be manipulated to effectively remove decoding paths, from a collection of possible decoding paths, based at least on the identified one or more a-priori bit values, resulting in one or more remaining decoding paths. The string of data bits may be decoded by selecting a decoding path from the one or more remaining decoding paths.

Abstract: A method and an apparatus for encoding and decoding a modulation code are provided. The method includes: adding an error detection bit(s) to source information; performing k-constraint coding by inserting an error pattern that can be detected using an error detection code into a data stream that violates a k-constraint for a run length limited (RLL) code in a data stream comprising the error detection bit(s) and the source information, and recording the data stream after being k-constraint coded onto a recording medium; and reading the data stream recorded onto the recording medium and determining whether an error is present in the data stream.

Abstract: An approach to reducing processing of soft output is disclosed. Candidate sequences of bits can be compared to soft output decisions to reduce at least one of the candidate sequences. Branch metric calculations can be performed for remaining candidate sequences and a most likely path can be selected from the remaining candidate sequences.

Abstract: A hybrid trace back apparatus and a high-speed Viterbi decoding system having the same are disclosed. The hybrid trace back apparatus includes: a register exchanging unit for receiving survivor values of each states from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation; a first storing unit for the register exchange operation; a second storing unit for storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory; and a block trace back unit for outputting decoded data by performing a block trace back operation while writing a value of the second storing unit.

Abstract: Disclosed are a turbo decoding apparatus and method for decoding a turbo-encoded signal by repeating element decoding. The apparatus includes a plurality of element decoders for applying element decoding, e.g., MAP decoding, in parallel to respective ones of a plurality of divided signals to be decoded, and an interleaver/deinterleaver for interleaving or deinterleaving a plurality of results of element decoding collectively. Each element decoder applies element decoding to a respective one of the divided signals, and the interleaver/deinterleaver alternately interleaves and deinterleaves a plurality of results of element decoding collectively. Turbo decoding is carried out by repeating these operations a prescribed number of times.

Abstract: To provide a decoder and decoding method capable of reducing the number of times received data is decoded. A decoder according to the present invention includes: a Viterbi decoder decoding received data; a decode data length storage area storing a decode data length; a decoded data temporary storage area storing temporary storage data as decoded data up to a decode data length; a maximum data storage memory storing maximum decoded data as decoded data up to a maximum data length; a maximum-likelihood detection circuit selecting a decode data length based on likelihood information; and a decoded data reconstruction circuit replacing a part of maximum decoded data with temporary decoded data.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.

Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is disclosed for RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture, and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA).

Abstract: The disclosed invention provides a method, a system and a computer program product for the maximum likelihood sequence estimation of transmitted MSK symbols. The disclosed invention provides a set of optimizations of the Viterbi algorithm for equalizing MSK symbols. The transmitted MSK symbols are alternately real and imaginary. Therefore, based on whether the transmitted MSK symbol is real or imaginary, the disclosed invention divides the set of Viterbi states into two sets of states. The disclosed invention obtains the surviving path only for the first set of states at stages corresponding to real transmitted symbols. A real hypothesis is used to obtain the surviving paths for the first set of states. The disclosed invention also obtains the surviving path only for the second set of states at stages corresponding to imaginary transmitted symbols. An imaginary hypothesis is used to obtain the surviving paths of the second set of states.

Abstract: A reduced-state Viterbi detector is disclosed that precomputes branch metrics for a multiple-step trellis for speculative sequences of one or more channel symbols; selects one of said precomputed branch metrics for multi-step state transitions based on at least one multi-step decision from at least one corresponding state; and selects a path having a best path metric for a given state.

Abstract: A sequence of cyclic redundancy check syndromes can be produced based on a received sequence of sets of parallel data wherein different ones of the sets can have respectively different parallel data widths. Some of the syndromes are produced based on respectively corresponding ones of the sets that each have a first parallel data width. At least one of the syndromes is produced based on a corresponding at least one of the sets that has a second parallel data width that is less than the first parallel data width. The last syndrome of the sequence of syndromes corresponds to all of the data in the received sequence of sets.

Abstract: Techniques are provided herein to improve the decoding efficiency in a wireless receiver to obtain a correctly decoded data string. A state metric matrix from a received codeword is used to generate active state metric matrices for time instances of the received codeword, and then a differential metric matrix is generated from information in the active state metric matrices. Based on the differential metric matrix a maximum likelihood path and one or more alternative paths are identified. A first decoded data string corresponding to the maximum likelihood path and a plurality of second decoded data strings corresponding to the one or more alternative paths are derived. Integrity of the respective decoded data strings is examined to obtain the correct decoded data string based on the first and second decoded data strings.

Abstract: A decoding method is provided which is capable of achieving decoding of error correcting codes in a simple configuration and in a short time. In the method of decoding error correcting codes to perform iterative decoding which consists of forward processing, backward processing, and extrinsic information value calculating, a backward processing path metric value obtained in the previous decoding iteration for a window boundary is used as an initial value of the backward processing path metric value for the window boundary in the next decoding iteration.

Abstract: Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. Decoding of LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various calculations that need to be performed when updating edge messages, the calculations may be reduced to only performing product of terms functions. When implementing such functionality in hardware within a communication device that is operable to decode LDPC coded signals, this reduction in processing complexity greatly eases the actual hardware's complexity as well. A significant savings in processing resources, memory, memory management concerns, and other performance driving parameters may be made.

Abstract: A method (700) and apparatus (600) are described for performing decision voting in connection with a parallel ACS unit (110) and track buffer (112) in an Ultrawide Bandwidth (UWB) receiver having a parallel DECODER for decoding a message sequence encoded according to a convolutional code. Outputs from the track buffer can be input to a voting unit (620) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.

Abstract: The present invention relates to a method and system for providing an N-wide add-compare-select instruction includes decoding an instruction as an N-wide add-compare-select instruction and selecting a plurality of branch metrics. The method also includes combining the plurality of branch metrics with a plurality of source operands and outputting a pair of maximum values.

Abstract: Systems and methods for improving the performance of decoders of forward error correcting codes use the information contained in late packet arrivals to update (or recompute) the state of the decoder. These systems and methods are generally applicable to decoders that maintain state information in decoding successive bits or information frames so as to improve the performance (i.e., the bit error rate) of the decoder since the recomputed state is exactly the state that the decoder would have had if the information contained in the late packet had originally arrived on time and been decoded in a usual manner. In effect, the updating of the decoder state following a late packet arrival terminates the propagation in time of the effect of the late packet erasure on the state of the decoder.

Abstract: An E2PR4 Viterbi detector includes a recovery circuit and receives a signal that represents a sequence of values, the sequence having a potential state. The recovery circuit recovers the sequence from the signal by identifying a surviving path to the potential state and, after identifying the surviving path, adding a modified branch metric to the path metric of the surviving path to generate an updated path metric for the potential state. Updating the path metric of the surviving path after the surviving path is selected allows the E2PR4 Viterbi detector to be smaller and/or faster than an E2PR4 Viterbi detector that updates the path metric before selecting the surviving path.

Abstract: Sliding block traceback decoding of block codes. Block by block basis decoding is performed in which a single block, and its corresponding overlap portion, are processed during a given time. The traceback saves a record of decision (e.g., among possible trellis branches between various trellis stages) and constructs only the surviving paths through each individual block. Since only one block (by also employing its corresponding overlap portion) is decoded per time, the traceback through the coded block signal is short. One block of the coded block signal is decoded at a time, and certain resulting information (e.g., bit estimates and/or states) of a first decoded block can be leveraged when decoding a second/adjacent block.

Abstract: An information reproduction apparatus using maximum likelihood decoding for calculating likelihood of a value of a reproducing signal to a plurality of reference values, the reproducing signal obtained from a recording medium, to decode the reproducing signal on the basis of the likelihood, the apparatus includes a circuit for detecting the reproducing signal from the recording medium, a circuit for detecting the reference values corresponding to a characteristic of the reproducing signal, and a correction circuit for correcting the reproducing signal or the calculated likelihood according to the detected reference values.

Abstract: A path-select-signal memory section in the Viterbi detector outputs each decoded data B?Sik corresponding to a branch that occurred a prescribed time ago in a surviving path to each state at a present time, in response to path select signals SEL0, SEL1. A shift register stores the path select signals SEL0, SEL1 in order of time. A binary output unit outputs a decoded bit corresponding to a branch that occurred a prescribed time ago in a surviving path. Output signal lines of the binary output unit and a selector train are connected according to a trellis diagram that corresponds to encoding operation.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Abstract: Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. The decoding can be performed on signals whose various symbols have been mapped to multiple modulations (constellations and mappings) according to a rate control sequence. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding to generate the signal that is subsequently decoded. Either one or both of an encoder that generates the signal and a decoder that decodes the signal may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).

Abstract: A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.