Abstract: A method and system are disclosed that provide a more efficient decoder for decoding block codes such as a complementary code keying (CCK) code. A receiver receives a signal containing at least one block codeword. A decoder decodes the block codeword contained in the received signal by finding a path in a trellis diagram with a calculated path metric that accounts for intersymbol interference (ISI). The path metric can be based on a branch metric that is calculated according to a decision feedback sequence estimation algorithm.

Abstract: The invention concerns a method for jointly decoding and equalizing a digital signal protected by a trellis-defined code and transmitted though a channel. The method consists in carrying out a maximum likelihood estimate of each current bit xn by minimizing the quadratic error between the observed symbol Vn and the current symbol in the channel output zn, the quadratic error being calculated (1002) from the set of observed symbols based on the branch metric of the last transition en1(X)?en(X) according to the relationship (I); wherein k represents the rank of the coefficients of transverse filtering introduced by the radioelectric channel. The branch metric is calculated by backtracking through the successive states and the error propagating process is inhibited (1003) while backtracking through the successive states by storing at each node S survivors and by updating each survivor at the next time.

Abstract: A method executed in a receiver that combines a decoder with an equalizer in a single module, comprising receiving at time k a signal r(k) in the receiver. Selecting as a signal transmitted by a transmitter a signal that minimizes the following equation metric ? j ? ( k ) = ? r ? ( k ) - ? l = L 1 + 1 L 1 ? h _ j ? ( l ) ? s ~ ? ( k - l ) - ? l = L 1 + 1 L + 1 ? h ~ j ? ( l ) ? s ^ ? ( k - l ) ? 2 where {tilde over (h)}j(l) is related to both the transmission channel and to the encoding structure in the transmitter, {tilde over (s)}(k) is a trial symbol specified by a selected trellis transition and ?(k) is a symbol that was previously decided. Applying the selected signal to the decoder to decode received symbols.

Abstract: A method and apparatus for decoding convolutional codes used in error-correcting circuitry for digital data communication. To increase the speed and precision of the decoding process, the branch and/or state metrics are normalized during the soft decision calculations, whereby the dynamic range of the decoder is better utilized. Another aspect of the invention relates to decreasing the time and memory required to calculate the log-likelihood ratio by sending some of the soft decision values directly to a calculator without first storing them in memory.

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed that uses precomputation (look-ahead) to increase throughput, with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation. Precomputing the branch metrics for all possible symbol combinations in the channel memory makes it possible to remove the branch metrics unit and decision-feedback unit from the feedback loop, thereby reducing the critical path. A set of multiplexers select the appropriate branch metrics based on the survivor symbols in the corresponding survivor path cells. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately.

Abstract: In a data recording apparatus, values of parity bits to be additionally provided every one predetermined length block in data obtained by demodulating the original data are determined so as to satisfy a part of or an entire the predetermined run length limitation rule in ranges of a current predetermined length block, the plurality of parity bits, and a next predetermined length block that is positioned next to the current block. The parity bits having the values are additionally provided to the current block.

Abstract: A signal processor and method therein that is arranged and constructed to recover a sequence of symbols from a received signal is discussed. The processor includes a symbol selector for selecting a symbol based on the received signal over a time period including previous symbol periods, said symbol period, and a number of additional symbol periods, where said number of additional symbol periods depends on the inter symbol interference associated with the received signal. The processor utilizes an MLSE approach that is adapted to be especially calculation efficient.

Abstract: A filter bank (10) and receiver including the filter bank (10) that is designed for processing a baseband signal of a received continuous phase modulated signal S(t) with an integer modulation index. The filter bank (10) has outputs for providing a plurality of decision variable values (d1,d2,d3,d4) each representing a likelihood value of a symbol, from a group of predefined symbols that are likely to be present in the continuous phase modulated signal S(t). The filter bank 10 has filter units (12,14,16,18) each having an impulse response determined by a complex main pulse containing a majority of signal energy of one of the predefined symbols that is likely to be in the continuous phase modulated signal S(t).

Abstract: The present inventive system and method relate to the computation of branch metrics in Trellis Coded Modulation communication systems, specifically one that uses a Viterbi decoder. As described herein, the branch metrics are located in a look-up table which is indexed by at least one polar coordinate. The use of the look-up table relieves the computational burden of calculating branch metrics from the receiver processor thereby allowing the receiver to decode highly complex waveforms without an increase in processor computational capacity and attendant increase in power consumption. Angular offset values or polar coordinates that are otherwise calculated by the receiver processor are used to enter the look-up table and extract the appropriate branch metric for use by the Viterbi decoder. The inventive system and method can be used with any modulated digital signal and specifically can be used with a MIL-STD-188-181b signal.

Abstract: A demapping system and method for demapping symbols into bits, is provided. An embodiment of the system comprises a processor, and a memory that is coupled to the processor. The memory comprises a memory module that comprises a program that finds a hard demapper output d based on a received symbol r; finds a challenger ci for each i, the challenger ci is a challenger of the hard demapper output d, i is an integer whose maximum value is a number of bits of the challenger ci; calculates reliability mi for each i, the reliability mi is the reliability of the hard demapper output d; and calculates soft bit xi for each i, the soft bit xi is calculated based on the reliability mi.

Abstract: A device and method for performing SISO decoding. The method comprising the steps of: (a) providing a trellis representative of an output of a convolutional encoder, the convolutional encoder has a coding rate of R, the trellis having a block length T. (b) assigning an initial conditions to each starting node of the trellis for a forward iteration through the trellis. (c) computing a forward metric for each node, starting from the start of the trellis and advancing forward through the trellis and storing forward metrics of nodes of a plurality of starting stages of windows. (d) repeating stages d(1)-d(3) until all lambdas of the trellis are calculated; d(1) retrieving forward metrics of nodes of a starting stage of a window, the retrieved forward metrics were computed and stored during step (c). d(2) computing and storing forward metrics for each node, starting from a second stage of the window and ending at the ending stage of the window.

Abstract: A method for decoding an encoded signal. A first step generates a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics. A second step generates a plurality of second precision state metrics for a selected subset of the first precision state metrics in response to a plurality of second precision branch metrics. A third step replaces the selected subset of first precision state metrics with the second precision state metrics. A fourth step stores the first precision state metrics and the second precision state metrics.

Abstract: A communication system is composed of an encoder encoding an input sequence to sequentially generate output codes X0, X1, . . . , and a decoder decoding the output codes by a MLSD (Maximum Likelihood Sequence Detection) method with a trellis memory length being L. The output code Xk of the output codes X0, X1, . . . is determined based on the input sequence for k that is not equal to i(N+1) with i being any of natural numbers and with N being a natural number. The output code Xi(N+1) of the output codes X0, X1, . . . are uniquely determined based on a subset of a set consisting of the output codes Xi(N+1)?L+1, Xi(N+1)?L+2, . . . , Xi(N+1)?1 of the output codes X0, X1, . . . The subset includes the output code X1(N+1)?L+1 of the output codes Xi(N+1)?L+1, Xi(N+1)?L+2, . . . , X1 (N+1)?1.

Abstract: A method for decoding a word received at a current time instant into a symbol of a trellis code. The trellis code corresponds to a trellis diagram having N states associated with the current time instant. Each of the N states corresponds to at least one incoming branch. Each of the incoming branches is associated with a symbol of the trellis code. The branch metrics are computed for the incoming branches such that a branch metric represents a distance between the received word and a symbol associated with the corresponding branch. The branch metric is represented by fewer bits than a squared Euclidian metric representation of the distance. For each of the N states, a node metric is computed based on corresponding branch metrics and one of the incoming branches associated with the state is selected. One of the N states is selected as an optimal state based on the node metrics. The symbol associated with the selected incoming branch corresponding to the optimal state is the decoded word.

Abstract: By utilizing an additional counter and monitoring the maximum state metric at each stage, only forward progressing modulo wrap-arounds will occur and these can be counted. After decoding this count information, it can be used with the initial and final state metric values from the decoder to compute the desired full path metric. The method only requires monitoring state metric wrap-arounds moving in one direction and hence only needs to increment the extra counter as opposed to having to do likewise in the opposite direction. In another embodiment, the method can handle both forward and backward progressions by incrementing and decrementing a counter.

Abstract: The traceback operation for a Viterbi algorithm can be minimized by producing optimal path values for each state in the trellis, and updating the optimal path values at each state for each symbol. The optimal path value can be used to quickly determine the output values for the system without requiring a traceback which would typically require a memory read for each transmitted symbol.

Abstract: The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates.

Abstract: A method and apparatus are provided for implementing soft-input soft-output iterative detectors/decoders. Soft-input information is added directly to incoming channel samples. Input signals comprising the received incoming channel samples with the added soft-input information are detected using a detector trellis. Branch metric terms are transformed to shift all time varying terms with the added soft-input information and some constant terms after an add compare select (ACS) unit. The shifted time varying terms with the added soft-input information and the shifted constant terms are added directly to state metric terms. The soft-input information is added directly to incoming channel samples and the computation of branch metrics is not affected. This allows optimization of a dual-max detector and soft-input soft-output Viterbi detector architectures to minimize hardware complexity and power consumption.

Abstract: A Viterbi equalizer includes a digital signal processor with has a first and a second associated hardware data path. The first data path is intended for carrying out ACS operations and calculates state metrics of target states in a trellis diagram. Depending on the configuration, the second hardware data path calculates either transition metrics from previous states to target states in the trellis diagram, or soft output values.

Abstract: An apparatus and method for channel encoding/decoding are provided which vary an iterative decoding number according to service type, data class and channel condition. A message information receiver receives information about a message to be received. A controller determines an iterative decoding number according to the message information received. A decoder iteratively decodes the received message according to the determined iterative decoding number. The message information includes a class of received data, and the class includes a bit error rate (BER). The iterative decoding number is increased for a low BER as compared to a predetermined BER. Further, the class includes a permissible time delay, and the iterative decoding number is increased for a long permissible time delay as compared to a predetermined permissible time delay.

Abstract: A decoder generally comprising a branch metrics circuit and a state metrics circuit. The branch metrics circuit may be configured to generate a plurality of branch metric signals. The state metrics circuit may be configured to (i) add the branch metric signals to a plurality of state metric signals to generate a plurality of intermediate signals, (ii) determine a next state metric signal to the state metric signals, (iii) determine a normalization signal in response to the intermediate signals, and (iv) normalize the state metric signals in response to the normalization signal.

Abstract: The present invention discloses a butterfly processor capable of performing convolutional decoding and LogMAP decoding in telecommunications systems. First and second add-compare-select modules are provided for receiving input path metrics. A branch metric calculator is also provided for receiving input data and extrinsic data. The branch metric calculator generates output branch metrics to each of the first and second add-compare-select modules. Each of the add-compare-select modules includes a log-sum correction means coupled to compare and select components. A controllable switch selectively couples outputs of the select components and the log-sum corrections means to enable either one of convolutional or LogMAP decoding.

Abstract: Systems and related methods are described for (1) determining one or more state probabilities for one or more states in a trellis representation; (2) determining an estimate of or extrinsic output for one or more bits using a trellis representation; (3) determining a branch metric for a branch in a trellis representation; (4) performing a MAX*2->1 operation; (5) performing a MAX*2p->1 operation, where p is an integer of two or more, through a hierarchical arrangement of MAX*2->1 operations; and (6) computing forward state probabilities in a forward mode of operation and computing backward state probabilities in a backward mode of operation. Combinations of the foregoing are also described.

Abstract: A turbo decoder for decoding a data signal transmitted via a disturbed channel has a symbol estimator. The symbol estimator contains a computing device, which, with knowledge of the error protection code used at the transmitter end, calculates transition metric values, forward and reverse recursion metric values and the output values (LLR). The computing device includes at least one hardware computing chip constructed of combinatorial logic for generating at least one type of the values.

Abstract: A method of calculating recursive state metric vectors of a block of symbols wherein, the state metric vectors being supplied to an output calculating unit. The method includes calculating the state metric vectors from a first side of the block, and calculating for a second time at least some of the state metric vectors from the first side of the block.

Abstract: Briefly, a method to decode a block of information of a turbo code to produce a decoded block. The method may determine from a structure of an error detection code one or more possible error patterns and may generate a reliability metric based on one or more of the one or more possible error patterns and the decoded block.

Abstract: A method of determining branch metric values in a detector is provided. The method includes receiving time variant signal samples, and computing the branch metric values as a function of transition jitter statistics corresponding to the signal samples. A detector configured to determine branch metric values as a function of transition jitter statistics corresponding to signal samples is also provided.

Abstract: Briefly, a configurable decoder to decode signals of communication systems is provided. The configurable decoder may include a programmable metric data generator to reconfigure an add-compare-select unit according to a predetermined data structure provided by a desired communication protocol and a programmable traceback unit to provide decoded data according to the desired communication protocol.

Abstract: A grid coordinator which has been configured for autonomic failover can include a monitor communicatively linked to a multiplicity of grid hosts in a services grid. A metrics store can be coupled to the monitor and configured to store service metrics for individual service instances in the grid hosts. Optimization logic can be programmed to compute a best-fit between metrics stored for a set of service instances in a failed grid host, and platform metrics determined for a proposed replacement grid host. Finally, a failover processor can be coupled to the monitor and the optimization logic and communicatively linked to the grid hosts to create a new set of service instances in the proposed replacement grid host to replace the set of service instances in the failed grid host according to the best-fit in the optimization logic.

Abstract: The present invention discloses method and apparatus for decoding multi-level trellis coded modulation having improved efficiency by parallel processing when decodes multi-level trellis coded modulation. The method and apparatus according to the present invention divide branches having the next state periodically using commonness among branches divided from the current state to the next state, and improve efficiency of decoder by the parallel processing unit for addition comparison selection according to the rate of code and the size of binding field based on this periodicity. And, the feature of the present invention is having the simplicity for hardware and the facility for constitution when constitutes the decoder to the large scale integrated circuit, by constituting data to be able to the series processing, produced from the operation of the unit for parallel addition comparison selection.

Abstract: Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics. More generally, iterative detection is performed by receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module, and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure.

Abstract: An improved error correction code process takes advantage of information available from a post processor. This information is a list of highly probable error event patterns and locations found by employing a list Viterbi or a set of matched filters on Viterbi data. This list of possible errors can be used by the error correction code decoder in an iterative process whenever the correction power of the error correction code decoder is exceeded. If the error correction code decoder cannot correct the data on its first unassisted try, an iterative process is employed which, in essence, modifies the data with potential errors identified from the list created by the post processor and tries the correction process over again. An algorithm may be employed to try each error singly or in combination with other errors. This iterative process continues until a correctable indication is given by the error correction code decoder algorithm.

Abstract: A Reduced-State Sequence Estimation (RSSE) method is disclosed, whereby states in a trellis structure associated, for example, with a Viterbi algorithm are partitioned into a plurality of hyper-states. During a hyper-state decision interval, a hyper-soft value is calculated. The calculated hyper-soft value is a measurement of the accuracy of the hyper-state decision made. The calculated hyper-soft value can be used by an equalizer to generate soft-value information for decoding. A soft-value generated from such a hyper-soft value combined with bit soft-value in an RSSE algorithm is significantly more accurate than a soft-value that can be generated for a DFSE algorithm (i.e., without such a hyper-soft value).

Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.

Abstract: The method of the present invention decodes a received symbol that represents data bits including message bits and parity-check bits. The method comprises (a) mapping the symbol onto a received signal point in a signal space, the signal point having an in-phase component (I) and a quadrature phase component (Q) in the signal space; (b) computing reliability information for each data bit, the reliability information associated with a distance di={square root over ((I−Ii)2+(Q−Qi)2)} between the received signal point (I, Q) and a reference constellation point (Ii, Qi) in the signal space, where i=0, 1, . . .

Abstract: An architecture for a turbo decoder performs a faster max* computation. In this architecture, one or more lookup tables begin processing a digital signal prior to the most significant bit of the digital signal stabilizes. This technique allows processing in the lookup table to be accomplished during a period of time in which processing could not be accomplished previously. As a result, the architecture performs the max* computations at a faster rate than previous architectures.

Abstract: A method and apparatus for Viterbi detector state metric re-normalization. The method includes fabricating a Viterbi detector (138) having a predetermined number of states, wherein the Viterbi detector (138) stores a state metric value and a branch metric value for each state, and wherein the Viterbi detector (138) implements a trellis diagram. The method includes constructing a Viterbi detector (138) which can support a state metric value having g+h′ number of bits. The number of bits needed to represent the branch metric value is represented by (g) and the additional number of bits needed to represent the state metric value is represented by (h′). The additional number of bits (h′) is less than the additional number of bits (h) determined using the following inequality: 2h−1−h≧K−1, wherein K represent the constraint length of the trellis diagram.

Abstract: An optical disc reproducing apparatus including a viterbi detector for an optical disc in which digital data is stored includes an optical pick-up for reading digital data stored in the optical disc and for generating a high frequency signal, an analog-to-digital converter for sampling and quantizing the high frequency signal, and a viterbi detector for decoding a quantized signal output from the analog-to digital converter and reproducing an eight to fourteen modulation (EFM)/EFM+signal. The viterbi detector includes a branch metric calculator for receiving a signal constituted of n bits, for comparing the signal with previously set three variables, and for calculating a branch metric with respect to the input signal. A path metric update and storage unit receives the branch metric, adds the branch metric to values stored therein, compares the error content of all the possible paths with each other, and stores a metric with respect to the path having the smallest amount of errors.

Abstract: This invention presents a unique implementation of the extrinsic block the turbo decoder that solves the problem of generation and use of precision extension and normalization in the alpha and beta metrics blocks. Both alpha metric inputs and beta metric inputs are processed via a circle boundary detector indicating the quadrant of the two's complement input and a precision extend block receiving an input and a corresponding circle boundary input. An extrinsics block includes a two's complement adder of the precision extended alpha and beta metrics inputs. The proposed solution obviates the need for normalization in the alpha and beta metric blocks.

Abstract: Disclosed are a turbo decoder, which applies a base-2 binary LogMAP algorithm in implementing a turbo decoder to thereby reduce the hardware requirement and implement a high-speed turbo decoder, which comprising a split for splitting the sum of two input state metrics into an integral and a decimal part; a comparator for comparing the integral parts of the two state metrics to extract a maximum and a minimum integer; a subtractor for obtaining a difference between the original integral part and the maximum or minimum integer value; a lookup table for calculating the sum of exponential terms of base-2 function in the decimal parts; a shifter for shifting only a decimal part with a smaller integral part by the difference; an adder for adding the decimal part and a decimal part with a larger integral part; a log pre-processing block for applying a base-2 logarithm on the decimal part to thereby obtain a final value for the decimal part; and an adder for adding the maximum integral value and the final value for t

Abstract: A digital signal decoding device according to an aspect of the present invention is a digital signal decoding device for generating a binary code sequence by maximum likelihood estimation from a convolutionally encoded input signal sequence, includes an add-compare-select unit configured to compare only two metric values one unit time before the calculation time of a predetermined branch metric value calculated from the input signal sequence at two successive times at each time, to add the predetermined branch metric value to the two metric values independently of the compare process, to select one of the two sums in accordance with the comparison result of the two metric values, and to output the selected value as a metric value to be used at the next time.

Abstract: An encoder for turbo coded trellis code modulation comprises an encoder data block for storing incoming data, and at least two recursive systematic convolutional encoders, said convolutional encoders being connected to receive data in parallel from said encoder data block. The decoder also employs a parallel implementation.

Abstract: In a conventional turbo-code decoding apparatus, there is a need for calculating a state transition probability for MAP decoding of convolutional codes composing turbo codes in an error correcting decoder and a channel state needs to be measured based on soft decision information to calculate the probability, by which an arithmetic operation amount is enormously increased. Turbo-code error correction decoding is performed by executing operations in a branch metric based forward path metric calculation step of calculating a forward path metric based on a branch metric with calculating the branch metric for a transition to an adjacent time point and a soft decision information calculation step of calculating N bits of soft decision information based on the branch metric, the forward path metric, and a backward path metric with calculating the backward path metric based on the branch metric.

Abstract: A magnetic recording and/or reproducing apparatus performing efficient decoding to lower a decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes a modulation SISO decoder 63 for modulation decoding data modulation-encoded in a predetermined fashion by a modulation coder 52. In the magnetic recording and/or reproducing apparatus 50, the modulation SISO decoder 63 is a soft input soft output (SISO) type modulation decoder fed with a soft input signal and issuing a soft output signal. The modulation SISO decoder 63 is fed with a trellis soft output signal D64 supplied from a trellis SISO decoder 62 to find a soft decision value for an error correction coding data D52 fed to the modulation coder 52 of the recording system to generate a modulated soft decision signal D65. The modulation SISO decoder 63 routes the so-generated modulated soft decision signal D65 to a downstream side error correction soft decoder 64.

Abstract: A method for decoding a word received at a current time instant into a symbol of a trellis code. The trellis code corresponds to a trellis diagram having N states associated with the current time instant. Each of the N states corresponds to at least one incoming branch. Each of the incoming branches is associated with a symbol of the trellis code. The branch metrics are computed for the incoming branches such that a branch metric represents a distance between the received word and a symbol associated with the corresponding branch. The branch metric is represented by fewer bits than a squared Euclidian metric representation of the distance. For each of the N states, a node metric is computed based on corresponding branch metrics and one of the incoming branches associated with the state is selected. One of the N states is selected as an optimal state based on the node metrics. The symbol associated with the selected incoming branch corresponding to the optimal state is the decoded word.

Abstract: Single stage implementation of min*, max*, min and/or max to perform state metric calculation in soft-in soft-out (SISO) decoder. This allows for calculation of state metrics in an extremely efficient, fast manner. When performing min or max calculations, comparisons are made using 2 element combinations of the available inputs. Subsequently, logic circuitry employs the results of the 2 element comparisons the smallest (min) or largest (max) input. The max or min implementations may be employed as part of the max* and/or min* implementations. For max* and/or min* implementations, simultaneous calculation of appropriate values is performed while determining which input is the smallest or largest. Thereafter, the determination of which input is the smallest or largest is used to select the appropriate resultant value (of the values calculated) for max* and/or min*. Various degrees of precision are employed for the log correction values within the max* and/or min* implementations.

Abstract: The present invention provides an error correction circuit for receiving and decoding a trellis-encoded signal of a series of data Zq, Zq−1, . . . ,Z1 which comprises convolutional-encoded bits and unencoded bits, the convolutional-encoded bits being obtained by convolutional-encoding lower t bits Xt, Xt−1, . . . ,X1 of an input p-bit series of data Xp, Xp−1, . . . , X1 (where p≧2, q≧p, and p>t≧1), and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The circuit includes: a maximum likelihood decoder for preselecting one of m parallel paths of transition from state x at time k to state y at time k+1.

Abstract: A method of monitoring the performance of a Viterbi detector by using the deviations from the noiseless case of the path difference of the two branches entering the minimal state for a number of samples.

Abstract: A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams.