Majority Decision/voter Circuit Patents (Class 714/797)
  • Patent number: 10320575
    Abstract: The invention relates to a message exchange controller structure (1) comprising means (3) forming a message exchange controller, associated with a member (4) forming a storage/exchange buffer, a member (5) forming interfaces for multiple connections to several message production/consumption units, and a member (6) forming interfaces for connecting to several external buses; which is characterized in that the means exchange controller-forming means (3) are able to recover redundant messages from external buses, store those messages in the storage/exchange buffer-forming member (4), recover those messages from the storage/exchange buffer-forming member (4), and process those messages so as to generate a resultant message (MF), to send it to at least one consumption unit.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: June 11, 2019
    Assignee: THALES
    Inventors: Patrice Toillon, Tarik Aegerter, Xavier Moreau
  • Patent number: 10205562
    Abstract: Error detection and correction techniques are employed in many digital communication systems. There may be multiple error detection and correction stages in a single communication system to provide a good balance of latency and retransmissions for reliable communication. Despite multiple levels of error detection and correction, there may be some residual errors. Many applications may require completely error free communication. A method and apparatus are disclosed for a receiver that may use the already received erroneous versions of transmitted and retransmitted packet or file to perform error correction without requesting additional retransmissions.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: February 12, 2019
    Assignee: MBIT WIRELESS, INC.
    Inventor: Bhaskar Patel
  • Patent number: 10173692
    Abstract: A microcontroller system for safety-critical motor vehicle systems is provided. The microcontroller system includes a plurality of subsystems arranged on a common chip. At least one of the subsystems has more than one channel and is designed to carry out a plurality of operating modes. The subsystems, in a first operating mode, are operated independently of each other and communicate with each other via an on-chip interface. In a second operating mode, at least one of the subsystems is operated by data transmission means and using non-local resources of at least one further subsystem and/or at least one of the subsystems is operating and at least one further subsystem is inactive. A method for operating such a microcontroller system and to the use thereof is also provided.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: January 8, 2019
    Assignee: Continental Teves AG & Co. OHG
    Inventors: Daniel Baumeister, Adrian Traskov
  • Patent number: 10025647
    Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventor: Thanunathan Rangarajan
  • Patent number: 9710012
    Abstract: A dynamic bus inversion (DBI) circuit disposed between a transmitter and a receiver for generating an inversion control signal that is communicated to the receiver and used to perform inversion control on data communicated along a data path between the transmitter and the receiver includes a delay data setup circuit to receive the data from the transmitter. A majority vote function circuit is used to perform majority voting for consecutive bits of data output by the delay data setup circuit to generate majority data output. An inversion control circuit receives the majority data output, retrieves feedback data from a preceding inversion control output and interprets the two data to generate inversion control signal, which is used to perform inversion control on data along the data path before being communicated to the receiver. The inversion control signal is used by the receiver to interpret the data received from the data path.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 18, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Efraim Dalumi, Eitan Lerner, Baruch Cohen
  • Patent number: 9672128
    Abstract: Provided is a multi-core device. The multi-core device includes: a plurality of cores outputting a test response value by receiving a test pattern value; a majority analyzer outputting a value corresponding to a majority of the test response value by analyzing the test response value; and a determination unit determining a core outputting a test response value different from the value corresponding to the majority among the plurality of cores.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: June 6, 2017
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Sungho Kang, Taewoo Han
  • Patent number: 9537591
    Abstract: Embodiments of the present disclosure relate to a Zero traffic hit synchronization switch over technique in a telecommunication network. The switch over is carried out by switching input reference of the receiver from one or more master (1) to at least one slave (2), wherein said slave (2) becomes new master (2) and said one or more master (1) becomes new slave (1) after switching. Now, the new master (2) locks to the new slave (1) for predetermined time period. Once the predetermined is elapsed, the new master (2) is disconnected from the new slave (1), wherein said new master (2) selects its own network reference clock upon disconnection of the new slave (1). The new slave (1) is locked to the new master (2) to synchronize the switchover in redundant systems.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: January 3, 2017
    Assignee: TEJAS NETWORKS LTD
    Inventors: Srinivas Rao, Gajendra Singh Ranka
  • Patent number: 9501370
    Abstract: In a timer module having at least two output channels, the at least two output channels are configurable in such a way that they generate redundant output signals, and the generation of the redundant output signals begins synchronously. In addition, the timer module has provides a comparison of the redundant output signals by an EXOR logic operation and stores a result of the EXOR logic operation in a way that allows the result to be retained for an erroneous comparison until it is reset by an access.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: November 22, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Eberhard Boehl, Stephen Schmitt, Juergen Hanisch
  • Patent number: 9116531
    Abstract: A system includes a triple modular redundant (TMR) control system comprising three controllers. Each controller of the three controllers includes a current driver system configured to detect and regulate a portion of a total current output of the TMR control system, and a universal input-output (UIO) system comprising a plurality of universal input-output (UIO) ports, wherein the universal input-output (UIO) system is configured to detect the portion of the total current output and the total current output of the TMR control system via one or more of the plurality of the UIO ports, compare the portion of the total current output and the total current output of the TMR control system, and adjust the portion of the total current output according to a predetermined total current output threshold.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: August 25, 2015
    Assignee: General Electric Company
    Inventor: Daniel Milton Alley
  • Patent number: 9032276
    Abstract: The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Wu Chang, Fan Zhang, Yang Han, Ming Jin
  • Patent number: 8909998
    Abstract: Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: December 9, 2014
    Assignee: Infineon Technologies AG
    Inventors: Otto Schumacher, Martin Maier, Thomas Hein, Aaron John Nygren
  • Publication number: 20140359403
    Abstract: A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.
    Type: Application
    Filed: August 18, 2014
    Publication date: December 4, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Koichi NAKAMURA
  • Publication number: 20140359402
    Abstract: A majority determination circuit includes a first determination unit suitable for determining a first majority between bits of a first logic value and a second logic value in a first odd-bit data, wherein the first odd-bit data is an even-bit data with absence of first bit, a second determination unit suitable for determining a second majority between bits of the first logic value and the second logic value in a second odd-bit data, wherein the second odd-bit data is the even-bit data with absence of second bit, and a result combination unit suitable for determining a third majority between bits of the first logic value and the second logic value in an even-bit data based on the first majority and the second majority.
    Type: Application
    Filed: December 15, 2013
    Publication date: December 4, 2014
    Applicant: SK hynix Inc.
    Inventor: Yong-Woo LEE
  • Patent number: 8898541
    Abstract: A storage controller includes an error correcting code managing portion, an address managing portion and an error correcting portion. The error correcting code managing portion manages a correspondence relationship between predetermined plural pieces of unit data, and a second error code corresponding to the plural pieces of unit data every entry when plural pieces of unit data and a second error correcting code are stored in a storage portion. The address managing portion manages a correspondence relationship between logical addresses and the entries in the error correcting code managing portion. The error correcting portion acquires the entry in the error correction managing portion corresponding to the logical address as an object of read from the address managing portion, and carries out error correction based on the plural pieces of unit data managed in the entry concerned, and the second error correcting code.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventors: Hideaki Okubo, Keiichi Tsutsui, Kenichi Nakanishi, Yasushi Fujinami, Makiko Yamamoto, Naohiro Adachi
  • Patent number: 8856603
    Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 7, 2014
    Assignees: European Aeronautic Defence And Space Company EADS France, Astrium SAS
    Inventors: Florent Miller, Thierry Carriere, Antonin Bougerol
  • Publication number: 20140298146
    Abstract: Electronic apparatus and fabrication of the electronic apparatus that includes detection of the majority of values in a plurality of data bits may be used in a variety of applications. Embodiments include application of majority bit detection to process data bits in a device for further analysis in the device based on the results of the majority bit detection. In an embodiment, such further processing in a memory device after majority bit detection may include data bit inversion prior to outputting the data from the memory device.
    Type: Application
    Filed: June 17, 2014
    Publication date: October 2, 2014
    Inventors: Jason M. Brown, Venkatraghavan Bringivijayaraghavan
  • Publication number: 20140245113
    Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.
    Type: Application
    Filed: May 5, 2014
    Publication date: August 28, 2014
    Applicant: Altera Corporation
    Inventor: Yanzhong Xu
  • Patent number: 8739010
    Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: May 27, 2014
    Assignee: Altera Corporation
    Inventor: Yanzhong Xu
  • Patent number: 8729923
    Abstract: Data words from a parallel communication channel are interleaved to two majority vote blocks that operate out of phase, using a divided clock signal that has half the clock frequency of the clock signal associated with the parallel communication channel. As one majority vote block evaluates a data word and outputs a result, the other majority vote block is in pre-charge mode awaiting the next data for evaluation.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 20, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Venkatesh Ramachandra
  • Patent number: 8700970
    Abstract: A system and method for decoding data. Multi-dimensional encoded data may be received that potentially has errors. The multi-dimensional encoded data may encode each input bit in a set of input bits multiple times in multiple different dimensions to generate encoded bits. The encoded bits may be decoded in at least one of the multiple dimensions. If one or more errors are detected in a plurality of encoded bits in the at least one of the multiple dimensions, an intersection sub-set of the encoded data may be decoded that includes data encoding the same input bits encoded by the plurality of encoded bits in at least a second dimension of the multiple dimensions. The values of the input bits by decoding the intersection sub-set may be changed.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: April 15, 2014
    Assignee: Densbits Technologies Ltd.
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 8631310
    Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. For example, the method further includes: within the data read at different times at the same address, temporarily storing all of the data except for data of a last time into buffering regions/buffers, respectively, with the majority vote data being temporarily stored into a second buffering region/buffer to utilize a latest generated portion within the majority vote data to replace a latest retrieved portion within data in the second buffering region/buffer. An associated memory device and the controller thereof are further provided.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: January 14, 2014
    Assignee: Silicon Motion Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 8631290
    Abstract: An automated guardband compensation system automatically compensates for degradation in the guardband of a clocked data processing circuit while that circuit is connected within a data processing system. A control circuit automatically and repeatedly requests: a switching circuit to switch a critical path within the clocked data processing circuit out of a data processing pathway within the data processing system while the clocked data processing circuit is connected within the data processing system; a guardband test circuit to test the guardband of the critical path while the critical path is switched out of the data processing pathway; a guardband compensation circuit to increase the guardband when the results of the test indicate a material degradation in the guardband; and a switching circuit to switch the critical path back into the data processing pathway after the test.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 14, 2014
    Assignee: University of Southern California
    Inventors: Bardia Zandian, Murali Annavaram
  • Patent number: 8612843
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a media defect detector circuit. The media defect detector circuit is operable to compare a data input derived from a medium against at least a first defect level to yield a first level output, and a second defect level to yield a second level output; and provide a combination of the first level output and the second level output as a defect quality output. A value of the defect quality output corresponds to a likelihood of a defect of the medium.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Ming Jin, Haitao Xia, Lei Chen
  • Patent number: 8589767
    Abstract: A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: November 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Beom Kang, Chul Woo Park, Hyun Ho Choi, Ho Jung Kim
  • Patent number: 8570061
    Abstract: This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N?1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: October 29, 2013
    Assignee: Honeywell International Inc.
    Inventor: Keith Golke
  • Patent number: 8572390
    Abstract: A method for transmitting data, a receiving method, related devices, and an aircraft equipped with the devices. The method includes determining an authentication word of the data; processing the data to obtain processed data; and transmitting the processed data on a transmission channel.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: October 29, 2013
    Assignee: Airbus Operations S.A.S.
    Inventors: Agnes Leclercq, Cecile Colle-Morlec
  • Patent number: 8516354
    Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. An associated memory device and the controller thereof are further provided.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: August 20, 2013
    Assignee: Silicon Motion Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 8402328
    Abstract: An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: March 19, 2013
    Assignee: STARDFX Technologies, Inc.
    Inventors: Laung-Terng Wang, Nur A. Touba, Zhigang Jiang
  • Patent number: 8392810
    Abstract: In general, techniques are described for performing majority vote error correction techniques. In operation, a communication device comprising a control unit implements the majority vote error correction techniques. The control unit includes a link management module to request a first retransmission of a first communication received over a wireless communication medium in response to detecting a first uncorrectable error in the first communication, requests a second retransmission of the first communication in response to detecting a second uncorrectable error in a second communication received in response to the first retransmission request and receives a third communication in response to the second retransmission. The control unit also includes a majority vote module to, in response to detecting a third uncorrectable error in the third communication, perform a bit-wise majority vote on corresponding bits of the first, second and third communications to generate an error-corrected communication.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: March 5, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Joel Linsky, Sang-Uk Ryu
  • Patent number: 8362799
    Abstract: A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: January 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hideaki Arima
  • Patent number: 8327248
    Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: December 4, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Harold William Satterfield, Grady M. Wood
  • Patent number: 8255780
    Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: August 28, 2012
    Assignee: Saankhya Labs Pvt Ltd.
    Inventors: Anindya Saha, Hemant Mallapur, Santhosh Billava, Smitha Banavikal Math Veerabhadresh
  • Patent number: 8214625
    Abstract: One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: July 3, 2012
    Assignee: NVIDIA Corporation
    Inventors: John R. Nickolls, Lars Nyland, Peter C. Mills, Jeremy Sugerman, Timothy Foley, Brian Fahs, Michael Garland, David P. Luebke
  • Patent number: 8209591
    Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: June 26, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Harold William Satterfield, Grady Wood
  • Patent number: 8200947
    Abstract: One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: June 12, 2012
    Assignee: NVIDIA Corporation
    Inventors: John R. Nickolls, Lars Nyland, Peter C. Mills, Jeremy Sugerman, Timothy Foley, Brian Fahs, Michael Garland, David P. Luebke
  • Publication number: 20120131424
    Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.
    Type: Application
    Filed: November 19, 2010
    Publication date: May 24, 2012
    Inventor: Yanzhong Xu
  • Patent number: 8179258
    Abstract: In a method for reading a tag, the tag is interrogated with a reader device having an antenna. A waveform of the signal received from the tag in response to the interrogation is analyzed through application of a numerical analysis technique. The signal is analyzed to estimate a bit pattern in the waveform.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: May 15, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Alan McReynolds, Cyril Brignone
  • Patent number: 8145984
    Abstract: A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: March 27, 2012
    Assignee: Anobit Technologies Ltd.
    Inventors: Naftali Sommer, Ofir Shalvi, Dotan Sokolov
  • Patent number: 8127180
    Abstract: An electronic adapter device and an electronic system that comprises the electronic adapter device are described. The electronic adapter device comprises a device and a redundant device able to receive data from a first plurality of electronic devices and redundant data from a second plurality of electronic devices, and able to select therefrom first data and first redundant data respectively. The electronic adapter device also comprises a controller able to receive the selected first data and the selected first redundant data and is able to generate therefrom an error signal indicating a fault in an electronic device of the first plurality or a fault in the device.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: February 28, 2012
    Assignees: STMicroelectronics S.R.L., PARADES S.C.A.R.L.
    Inventors: Massimo Baleani, Marco Losi, Alberto Ferrari, Leonardo Mangeruca
  • Patent number: 8095841
    Abstract: Method and apparatus for testing semiconductor devices with autonomous expected value generation is described. Examples of the invention can relate to apparatus for interfacing a tester and a semiconductor device under test (DUT). An apparatus can include output processing logic configured to receive test result signals from the DUT responsive to testing by the tester, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value; and memory configured to store indications of whether each of the test result signals has the correct logic value.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: January 10, 2012
    Assignee: FormFactor, Inc.
    Inventor: Todd Ryland Kemmerling
  • Patent number: 8086944
    Abstract: A hard disk drive with a disk that has a plurality of data bits. The drive includes a circuit that reads each data bit n times and selects a value for the bit based on a reliability factor. The circuit may select a bit based at least in part on the most frequent occurrence of one of a plurality of values. For example, if more 0s occurred than 1s the bit would be set to 0. The reliability factor may be a ratio of the occurrence of 0s to the occurrence of 1s. A bit can be not selected or deselected if the reliability factor exceeds a threshold value.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yawshing Tang
  • Patent number: 8078920
    Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Limited
    Inventors: Atsushi Morosawa, Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Yuka Hosokawa, Takeshi Owaki, Takashi Yamamoto, Daisuke Itou
  • Patent number: 8020081
    Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: September 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Jin Kong, Sung Chung Park, Yun Tae Lee, Young Hwan Lee, Si Hoon Hong, Jae Woong Hyun, Dong Ku Kang
  • Publication number: 20110214039
    Abstract: A system and method for decoding data. Multi-dimensional encoded data may be received that potentially has errors. The multi-dimensional encoded data may encode each input bit in a set of input bits multiple times in multiple different dimensions to generate encoded bits. The encoded bits may be decoded in at least one of the multiple dimensions. If one or more errors are detected in a plurality of encoded bits in the at least one of the multiple dimensions, an intersection sub-set of the encoded data may be decoded that includes data encoding the same input bits encoded by the plurality of encoded bits in at least a second dimension of the multiple dimensions. The values of the input bits by decoding the intersection sub-set may be changed.
    Type: Application
    Filed: February 28, 2011
    Publication date: September 1, 2011
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 8006157
    Abstract: Outlier detection methods and apparatus have light computational resources requirement, especially on the storage requirement, and yet achieve a state-of-the-art predictive performance. The outlier detection problem is first reduced to that of a classification learning problem, and then selective sampling based on uncertainty of prediction is applied to further reduce the amount of data required for data analysis, resulting in enhanced predictive performance. The reduction to classification essentially consists in using the unlabeled normal data as positive examples, and randomly generated synthesized examples as negative examples. Application of selective sampling makes use of an underlying, arbitrary classification learning algorithm, the data labeled by the above procedure, and proceeds iteratively.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 23, 2011
    Assignee: International Business Machines Corporation
    Inventors: Naoki Abe, John Langford
  • Patent number: 8001452
    Abstract: Methods and apparatus are provided for soft decision decoding using reliability values based on a log base two function. A signal is processed to determine one or more reliability values for a soft decision decoder by computing one or more log-likelihood ratio (LLR) values using a log base two function. The soft decision decoder may employ, for example, a belief propagation algorithm. The soft decision decoder can decode, for example, Low-Density Parity Check codes or turbo codes.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: August 16, 2011
    Assignee: Agere Systems Inc.
    Inventor: Kameran Azadet
  • Publication number: 20110185248
    Abstract: In general, techniques are described for performing majority vote error correction techniques. In operation, a communication device comprising a control unit implements the majority vote error correction techniques. The control unit includes a link management module to request a first retransmission of a first communication received over a wireless communication medium in response to detecting a first uncorrectable error in the first communication, requests a second retransmission of the first communication in response to detecting a second uncorrectable error in a second communication received in response to the first retransmission request and receives a third communication in response to the second retransmission. The control unit also includes a majority vote module to, in response to detecting a third uncorrectable error in the third communication, perform a bit-wise majority vote on corresponding bits of the first, second and third communications to generate an error-corrected communication.
    Type: Application
    Filed: January 25, 2010
    Publication date: July 28, 2011
    Applicant: QUAL COMM Incorporated
    Inventors: Joel Linskey, Sang-Uk Ryu
  • Publication number: 20110161787
    Abstract: Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.
    Type: Application
    Filed: December 28, 2009
    Publication date: June 30, 2011
    Applicant: NXP B.V.
    Inventors: Andries Pieter Hekstra, Weihua Tang
  • Patent number: 7962841
    Abstract: A majority voting Viterbi decoder includes a branch metric calculator (BMC) for measuring a difference between a received symbol and a reference symbol and outputting branch metrics from the difference; an add-compare-selection (ACS) unit for determining an optimal path using the branch metrics; a survival path memory unit for outputting decoded symbols by performing decoding based on the optimal path; and a majority voting unit for determining a final decoded symbol by performing majority voting for the decoded symbols output from the survival path memory unit. Accordingly, by adding the majority voting unit, a decoding depth can be reduced without the loss of an encoding gain required in a system, and by reducing the decoding depth, miniaturization is possible, power consumption can be reduced, and a processing delay in a memory can be minimized.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shi-Chang Rho, Jun Jin Kong
  • Publication number: 20110138254
    Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. An associated memory device and the controller thereof are further provided.
    Type: Application
    Filed: May 6, 2010
    Publication date: June 9, 2011
    Inventor: Tsung-Chieh Yang